| blob | 0f4c9ec2c3a619523108360f315b1fc0dd83fa73 |
1 /*
2 * GE Fanuc SBC310 Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
17 /*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
19 */
21 /dts-v1/;
23 / {
24 model = "GEF_SBC310";
25 compatible = "gef,sbc310";
26 #address-cells = <1>;
27 #size-cells = <1>;
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
70 localbus@fef05000 {
71 #address-cells = <2>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>;
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe0000000 0x08000000 // Paged Flash 0
80 2 0 0xe8000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00010000>; // FPGA
84 /* flash@0,0 is a mirror of part of the memory in flash@1,0
85 flash@0,0 {
86 compatible = "cfi-flash";
87 reg = <0 0 0x01000000>;
88 bank-width = <2>;
89 device-width = <2>;
90 #address-cells = <1>;
91 #size-cells = <1>;
92 partition@0 {
93 label = "firmware";
94 reg = <0x00000000 0x01000000>;
95 read-only;
96 };
97 };
98 */
100 flash@1,0 {
101 compatible = "cfi-flash";
102 reg = <1 0 0x8000000>;
103 bank-width = <2>;
104 device-width = <2>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 partition@0 {
108 label = "user";
109 reg = <0x00000000 0x07800000>;
110 };
111 partition@7800000 {
112 label = "firmware";
113 reg = <0x07800000 0x00800000>;
114 read-only;
115 };
116 };
118 fpga@4,0 {
119 compatible = "gef,fpga-regs";
120 reg = <0x4 0x0 0x40>;
121 };
123 wdt@4,2000 {
124 #interrupt-cells = <2>;
125 device_type = "watchdog";
126 compatible = "gef,fpga-wdt";
127 reg = <0x4 0x2000 0x8>;
128 interrupts = <0x1a 0x4>;
129 interrupt-parent = <&gef_pic>;
130 };
131 /*
132 wdt@4,2010 {
133 #interrupt-cells = <2>;
134 device_type = "watchdog";
135 compatible = "gef,fpga-wdt";
136 reg = <0x4 0x2010 0x8>;
137 interrupts = <0x1b 0x4>;
138 interrupt-parent = <&gef_pic>;
139 };
140 */
141 gef_pic: pic@4,4000 {
142 #interrupt-cells = <1>;
143 interrupt-controller;
144 compatible = "gef,fpga-pic";
145 reg = <0x4 0x4000 0x20>;
146 interrupts = <0x8
147 0x9>;
148 interrupt-parent = <&mpic>;
150 };
151 gef_gpio: gpio@4,8000 {
152 #gpio-cells = <2>;
153 compatible = "gef,sbc310-gpio";
154 reg = <0x4 0x8000 0x24>;
155 gpio-controller;
156 };
157 };
159 soc@fef00000 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 #interrupt-cells = <2>;
163 device_type = "soc";
164 compatible = "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>;
166 bus-frequency = <33333333>;
168 mcm-law@0 {
169 compatible = "fsl,mcm-law";
170 reg = <0x0 0x1000>;
171 fsl,num-laws = <10>;
172 };
174 mcm@1000 {
175 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
176 reg = <0x1000 0x1000>;
177 interrupts = <17 2>;
178 interrupt-parent = <&mpic>;
179 };
181 i2c1: i2c@3000 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "fsl-i2c";
185 reg = <0x3000 0x100>;
186 interrupts = <0x2b 0x2>;
187 interrupt-parent = <&mpic>;
188 dfsrr;
190 rtc@51 {
191 compatible = "epson,rx8581";
192 reg = <0x00000051>;
193 };
194 };
196 i2c2: i2c@3100 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3100 0x100>;
201 interrupts = <0x2b 0x2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
205 hwmon@48 {
206 compatible = "national,lm92";
207 reg = <0x48>;
208 };
210 hwmon@4c {
211 compatible = "adi,adt7461";
212 reg = <0x4c>;
213 };
215 eti@6b {
216 compatible = "dallas,ds1682";
217 reg = <0x6b>;
218 };
219 };
221 dma@21300 {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
225 reg = <0x21300 0x4>;
226 ranges = <0x0 0x21100 0x200>;
227 cell-index = <0>;
228 dma-channel@0 {
229 compatible = "fsl,mpc8641-dma-channel",
230 "fsl,eloplus-dma-channel";
231 reg = <0x0 0x80>;
232 cell-index = <0>;
233 interrupt-parent = <&mpic>;
234 interrupts = <20 2>;
235 };
236 dma-channel@80 {
237 compatible = "fsl,mpc8641-dma-channel",
238 "fsl,eloplus-dma-channel";
239 reg = <0x80 0x80>;
240 cell-index = <1>;
241 interrupt-parent = <&mpic>;
242 interrupts = <21 2>;
243 };
244 dma-channel@100 {
245 compatible = "fsl,mpc8641-dma-channel",
246 "fsl,eloplus-dma-channel";
247 reg = <0x100 0x80>;
248 cell-index = <2>;
249 interrupt-parent = <&mpic>;
250 interrupts = <22 2>;
251 };
252 dma-channel@180 {
253 compatible = "fsl,mpc8641-dma-channel",
254 "fsl,eloplus-dma-channel";
255 reg = <0x180 0x80>;
256 cell-index = <3>;
257 interrupt-parent = <&mpic>;
258 interrupts = <23 2>;
259 };
260 };
262 enet0: ethernet@24000 {
263 #address-cells = <1>;
264 #size-cells = <1>;
265 device_type = "network";
266 model = "eTSEC";
267 compatible = "gianfar";
268 reg = <0x24000 0x1000>;
269 ranges = <0x0 0x24000 0x1000>;
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
272 interrupt-parent = <&mpic>;
273 phy-handle = <&phy0>;
274 phy-connection-type = "gmii";
276 mdio@520 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "fsl,gianfar-mdio";
280 reg = <0x520 0x20>;
282 phy0: ethernet-phy@0 {
283 interrupt-parent = <&gef_pic>;
284 interrupts = <0x9 0x4>;
285 reg = <1>;
286 };
287 phy2: ethernet-phy@2 {
288 interrupt-parent = <&gef_pic>;
289 interrupts = <0x8 0x4>;
290 reg = <3>;
291 };
292 };
293 };
295 enet1: ethernet@26000 {
296 device_type = "network";
297 model = "eTSEC";
298 compatible = "gianfar";
299 reg = <0x26000 0x1000>;
300 local-mac-address = [ 00 00 00 00 00 00 ];
301 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
302 interrupt-parent = <&mpic>;
303 phy-handle = <&phy2>;
304 phy-connection-type = "gmii";
305 };
307 serial0: serial@4500 {
308 cell-index = <0>;
309 device_type = "serial";
310 compatible = "ns16550";
311 reg = <0x4500 0x100>;
312 clock-frequency = <0>;
313 interrupts = <0x2a 0x2>;
314 interrupt-parent = <&mpic>;
315 };
317 serial1: serial@4600 {
318 cell-index = <1>;
319 device_type = "serial";
320 compatible = "ns16550";
321 reg = <0x4600 0x100>;
322 clock-frequency = <0>;
323 interrupts = <0x1c 0x2>;
324 interrupt-parent = <&mpic>;
325 };
327 mpic: pic@40000 {
328 clock-frequency = <0>;
329 interrupt-controller;
330 #address-cells = <0>;
331 #interrupt-cells = <2>;
332 reg = <0x40000 0x40000>;
333 compatible = "chrp,open-pic";
334 device_type = "open-pic";
335 };
337 global-utilities@e0000 {
338 compatible = "fsl,mpc8641-guts";
339 reg = <0xe0000 0x1000>;
340 fsl,has-rstcr;
341 };
342 };
344 pci0: pcie@fef08000 {
345 compatible = "fsl,mpc8641-pcie";
346 device_type = "pci";
347 #interrupt-cells = <1>;
348 #size-cells = <2>;
349 #address-cells = <3>;
350 reg = <0xfef08000 0x1000>;
351 bus-range = <0x0 0xff>;
352 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
353 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
354 clock-frequency = <33333333>;
355 interrupt-parent = <&mpic>;
356 interrupts = <0x18 0x2>;
357 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
358 interrupt-map = <
359 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
360 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
361 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
362 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
363 >;
365 pcie@0 {
366 reg = <0 0 0 0 0>;
367 #size-cells = <2>;
368 #address-cells = <3>;
369 device_type = "pci";
370 ranges = <0x02000000 0x0 0x80000000
371 0x02000000 0x0 0x80000000
372 0x0 0x40000000
374 0x01000000 0x0 0x00000000
375 0x01000000 0x0 0x00000000
376 0x0 0x00400000>;
377 };
378 };
379 };