| blob | 848320e4d3c4060049e6d78b1449aa24a62b8606 |
1 /*
2 * MPC8641 HPCN Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 /*
30 * Only one of Rapid IO or PCI can be present due to HW limitations and
31 * due to the fact that the 2 now share address space in the new memory
32 * map. The most likely case is that we have PCI, so comment out the
33 * rapidio node. Leave it here for reference.
34 */
35 /* rapidio0 = &rapidio0; */
36 };
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
42 PowerPC,8641@0 {
43 device_type = "cpu";
44 reg = <0>;
45 d-cache-line-size = <32>;
46 i-cache-line-size = <32>;
47 d-cache-size = <32768>; // L1
48 i-cache-size = <32768>; // L1
49 timebase-frequency = <0>; // From uboot
50 bus-frequency = <0>; // From uboot
51 clock-frequency = <0>; // From uboot
52 };
53 PowerPC,8641@1 {
54 device_type = "cpu";
55 reg = <1>;
56 d-cache-line-size = <32>;
57 i-cache-line-size = <32>;
58 d-cache-size = <32768>;
59 i-cache-size = <32768>;
60 timebase-frequency = <0>; // From uboot
61 bus-frequency = <0>; // From uboot
62 clock-frequency = <0>; // From uboot
63 };
64 };
66 memory {
67 device_type = "memory";
68 reg = <0x00000000 0x40000000>; // 1G at 0x0
69 };
71 localbus@ffe05000 {
72 #address-cells = <2>;
73 #size-cells = <1>;
74 compatible = "fsl,mpc8641-localbus", "simple-bus";
75 reg = <0xffe05000 0x1000>;
76 interrupts = <19 2>;
77 interrupt-parent = <&mpic>;
79 ranges = <0 0 0xef800000 0x00800000
80 2 0 0xffdf8000 0x00008000
81 3 0 0xffdf0000 0x00008000>;
83 flash@0,0 {
84 compatible = "cfi-flash";
85 reg = <0 0 0x00800000>;
86 bank-width = <2>;
87 device-width = <2>;
88 #address-cells = <1>;
89 #size-cells = <1>;
90 partition@0 {
91 label = "kernel";
92 reg = <0x00000000 0x00300000>;
93 };
94 partition@300000 {
95 label = "firmware b";
96 reg = <0x00300000 0x00100000>;
97 read-only;
98 };
99 partition@400000 {
100 label = "fs";
101 reg = <0x00400000 0x00300000>;
102 };
103 partition@700000 {
104 label = "firmware a";
105 reg = <0x00700000 0x00100000>;
106 read-only;
107 };
108 };
109 };
111 soc8641@ffe00000 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 device_type = "soc";
115 compatible = "simple-bus";
116 ranges = <0x00000000 0xffe00000 0x00100000>;
117 bus-frequency = <0>;
119 mcm-law@0 {
120 compatible = "fsl,mcm-law";
121 reg = <0x0 0x1000>;
122 fsl,num-laws = <10>;
123 };
125 mcm@1000 {
126 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
127 reg = <0x1000 0x1000>;
128 interrupts = <17 2>;
129 interrupt-parent = <&mpic>;
130 };
132 i2c@3000 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 cell-index = <0>;
136 compatible = "fsl-i2c";
137 reg = <0x3000 0x100>;
138 interrupts = <43 2>;
139 interrupt-parent = <&mpic>;
140 dfsrr;
141 };
143 i2c@3100 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 cell-index = <1>;
147 compatible = "fsl-i2c";
148 reg = <0x3100 0x100>;
149 interrupts = <43 2>;
150 interrupt-parent = <&mpic>;
151 dfsrr;
152 };
154 dma@21300 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
158 reg = <0x21300 0x4>;
159 ranges = <0x0 0x21100 0x200>;
160 cell-index = <0>;
161 dma-channel@0 {
162 compatible = "fsl,mpc8641-dma-channel",
163 "fsl,eloplus-dma-channel";
164 reg = <0x0 0x80>;
165 cell-index = <0>;
166 interrupt-parent = <&mpic>;
167 interrupts = <20 2>;
168 };
169 dma-channel@80 {
170 compatible = "fsl,mpc8641-dma-channel",
171 "fsl,eloplus-dma-channel";
172 reg = <0x80 0x80>;
173 cell-index = <1>;
174 interrupt-parent = <&mpic>;
175 interrupts = <21 2>;
176 };
177 dma-channel@100 {
178 compatible = "fsl,mpc8641-dma-channel",
179 "fsl,eloplus-dma-channel";
180 reg = <0x100 0x80>;
181 cell-index = <2>;
182 interrupt-parent = <&mpic>;
183 interrupts = <22 2>;
184 };
185 dma-channel@180 {
186 compatible = "fsl,mpc8641-dma-channel",
187 "fsl,eloplus-dma-channel";
188 reg = <0x180 0x80>;
189 cell-index = <3>;
190 interrupt-parent = <&mpic>;
191 interrupts = <23 2>;
192 };
193 };
195 enet0: ethernet@24000 {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 cell-index = <0>;
199 device_type = "network";
200 model = "TSEC";
201 compatible = "gianfar";
202 reg = <0x24000 0x1000>;
203 ranges = <0x0 0x24000 0x1000>;
204 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupts = <29 2 30 2 34 2>;
206 interrupt-parent = <&mpic>;
207 tbi-handle = <&tbi0>;
208 phy-handle = <&phy0>;
209 phy-connection-type = "rgmii-id";
211 mdio@520 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,gianfar-mdio";
215 reg = <0x520 0x20>;
217 phy0: ethernet-phy@0 {
218 interrupt-parent = <&mpic>;
219 interrupts = <10 1>;
220 reg = <0>;
221 device_type = "ethernet-phy";
222 };
223 phy1: ethernet-phy@1 {
224 interrupt-parent = <&mpic>;
225 interrupts = <10 1>;
226 reg = <1>;
227 device_type = "ethernet-phy";
228 };
229 phy2: ethernet-phy@2 {
230 interrupt-parent = <&mpic>;
231 interrupts = <10 1>;
232 reg = <2>;
233 device_type = "ethernet-phy";
234 };
235 phy3: ethernet-phy@3 {
236 interrupt-parent = <&mpic>;
237 interrupts = <10 1>;
238 reg = <3>;
239 device_type = "ethernet-phy";
240 };
241 tbi0: tbi-phy@11 {
242 reg = <0x11>;
243 device_type = "tbi-phy";
244 };
245 };
246 };
248 enet1: ethernet@25000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 cell-index = <1>;
252 device_type = "network";
253 model = "TSEC";
254 compatible = "gianfar";
255 reg = <0x25000 0x1000>;
256 ranges = <0x0 0x25000 0x1000>;
257 local-mac-address = [ 00 00 00 00 00 00 ];
258 interrupts = <35 2 36 2 40 2>;
259 interrupt-parent = <&mpic>;
260 tbi-handle = <&tbi1>;
261 phy-handle = <&phy1>;
262 phy-connection-type = "rgmii-id";
264 mdio@520 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "fsl,gianfar-tbi";
268 reg = <0x520 0x20>;
270 tbi1: tbi-phy@11 {
271 reg = <0x11>;
272 device_type = "tbi-phy";
273 };
274 };
275 };
277 enet2: ethernet@26000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <2>;
281 device_type = "network";
282 model = "TSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 ranges = <0x0 0x26000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <31 2 32 2 33 2>;
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi2>;
290 phy-handle = <&phy2>;
291 phy-connection-type = "rgmii-id";
293 mdio@520 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,gianfar-tbi";
297 reg = <0x520 0x20>;
299 tbi2: tbi-phy@11 {
300 reg = <0x11>;
301 device_type = "tbi-phy";
302 };
303 };
304 };
306 enet3: ethernet@27000 {
307 #address-cells = <1>;
308 #size-cells = <1>;
309 cell-index = <3>;
310 device_type = "network";
311 model = "TSEC";
312 compatible = "gianfar";
313 reg = <0x27000 0x1000>;
314 ranges = <0x0 0x27000 0x1000>;
315 local-mac-address = [ 00 00 00 00 00 00 ];
316 interrupts = <37 2 38 2 39 2>;
317 interrupt-parent = <&mpic>;
318 tbi-handle = <&tbi3>;
319 phy-handle = <&phy3>;
320 phy-connection-type = "rgmii-id";
322 mdio@520 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 compatible = "fsl,gianfar-tbi";
326 reg = <0x520 0x20>;
328 tbi3: tbi-phy@11 {
329 reg = <0x11>;
330 device_type = "tbi-phy";
331 };
332 };
333 };
335 serial0: serial@4500 {
336 cell-index = <0>;
337 device_type = "serial";
338 compatible = "ns16550";
339 reg = <0x4500 0x100>;
340 clock-frequency = <0>;
341 interrupts = <42 2>;
342 interrupt-parent = <&mpic>;
343 };
345 serial1: serial@4600 {
346 cell-index = <1>;
347 device_type = "serial";
348 compatible = "ns16550";
349 reg = <0x4600 0x100>;
350 clock-frequency = <0>;
351 interrupts = <28 2>;
352 interrupt-parent = <&mpic>;
353 };
355 mpic: pic@40000 {
356 interrupt-controller;
357 #address-cells = <0>;
358 #interrupt-cells = <2>;
359 reg = <0x40000 0x40000>;
360 compatible = "chrp,open-pic";
361 device_type = "open-pic";
362 };
364 global-utilities@e0000 {
365 compatible = "fsl,mpc8641-guts";
366 reg = <0xe0000 0x1000>;
367 fsl,has-rstcr;
368 };
369 };
371 pci0: pcie@ffe08000 {
372 compatible = "fsl,mpc8641-pcie";
373 device_type = "pci";
374 #interrupt-cells = <1>;
375 #size-cells = <2>;
376 #address-cells = <3>;
377 reg = <0xffe08000 0x1000>;
378 bus-range = <0x0 0xff>;
379 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
380 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
381 clock-frequency = <33333333>;
382 interrupt-parent = <&mpic>;
383 interrupts = <24 2>;
384 interrupt-map-mask = <0xff00 0 0 7>;
385 interrupt-map = <
386 /* IDSEL 0x11 func 0 - PCI slot 1 */
387 0x8800 0 0 1 &mpic 2 1
388 0x8800 0 0 2 &mpic 3 1
389 0x8800 0 0 3 &mpic 4 1
390 0x8800 0 0 4 &mpic 1 1
392 /* IDSEL 0x11 func 1 - PCI slot 1 */
393 0x8900 0 0 1 &mpic 2 1
394 0x8900 0 0 2 &mpic 3 1
395 0x8900 0 0 3 &mpic 4 1
396 0x8900 0 0 4 &mpic 1 1
398 /* IDSEL 0x11 func 2 - PCI slot 1 */
399 0x8a00 0 0 1 &mpic 2 1
400 0x8a00 0 0 2 &mpic 3 1
401 0x8a00 0 0 3 &mpic 4 1
402 0x8a00 0 0 4 &mpic 1 1
404 /* IDSEL 0x11 func 3 - PCI slot 1 */
405 0x8b00 0 0 1 &mpic 2 1
406 0x8b00 0 0 2 &mpic 3 1
407 0x8b00 0 0 3 &mpic 4 1
408 0x8b00 0 0 4 &mpic 1 1
410 /* IDSEL 0x11 func 4 - PCI slot 1 */
411 0x8c00 0 0 1 &mpic 2 1
412 0x8c00 0 0 2 &mpic 3 1
413 0x8c00 0 0 3 &mpic 4 1
414 0x8c00 0 0 4 &mpic 1 1
416 /* IDSEL 0x11 func 5 - PCI slot 1 */
417 0x8d00 0 0 1 &mpic 2 1
418 0x8d00 0 0 2 &mpic 3 1
419 0x8d00 0 0 3 &mpic 4 1
420 0x8d00 0 0 4 &mpic 1 1
422 /* IDSEL 0x11 func 6 - PCI slot 1 */
423 0x8e00 0 0 1 &mpic 2 1
424 0x8e00 0 0 2 &mpic 3 1
425 0x8e00 0 0 3 &mpic 4 1
426 0x8e00 0 0 4 &mpic 1 1
428 /* IDSEL 0x11 func 7 - PCI slot 1 */
429 0x8f00 0 0 1 &mpic 2 1
430 0x8f00 0 0 2 &mpic 3 1
431 0x8f00 0 0 3 &mpic 4 1
432 0x8f00 0 0 4 &mpic 1 1
434 /* IDSEL 0x12 func 0 - PCI slot 2 */
435 0x9000 0 0 1 &mpic 3 1
436 0x9000 0 0 2 &mpic 4 1
437 0x9000 0 0 3 &mpic 1 1
438 0x9000 0 0 4 &mpic 2 1
440 /* IDSEL 0x12 func 1 - PCI slot 2 */
441 0x9100 0 0 1 &mpic 3 1
442 0x9100 0 0 2 &mpic 4 1
443 0x9100 0 0 3 &mpic 1 1
444 0x9100 0 0 4 &mpic 2 1
446 /* IDSEL 0x12 func 2 - PCI slot 2 */
447 0x9200 0 0 1 &mpic 3 1
448 0x9200 0 0 2 &mpic 4 1
449 0x9200 0 0 3 &mpic 1 1
450 0x9200 0 0 4 &mpic 2 1
452 /* IDSEL 0x12 func 3 - PCI slot 2 */
453 0x9300 0 0 1 &mpic 3 1
454 0x9300 0 0 2 &mpic 4 1
455 0x9300 0 0 3 &mpic 1 1
456 0x9300 0 0 4 &mpic 2 1
458 /* IDSEL 0x12 func 4 - PCI slot 2 */
459 0x9400 0 0 1 &mpic 3 1
460 0x9400 0 0 2 &mpic 4 1
461 0x9400 0 0 3 &mpic 1 1
462 0x9400 0 0 4 &mpic 2 1
464 /* IDSEL 0x12 func 5 - PCI slot 2 */
465 0x9500 0 0 1 &mpic 3 1
466 0x9500 0 0 2 &mpic 4 1
467 0x9500 0 0 3 &mpic 1 1
468 0x9500 0 0 4 &mpic 2 1
470 /* IDSEL 0x12 func 6 - PCI slot 2 */
471 0x9600 0 0 1 &mpic 3 1
472 0x9600 0 0 2 &mpic 4 1
473 0x9600 0 0 3 &mpic 1 1
474 0x9600 0 0 4 &mpic 2 1
476 /* IDSEL 0x12 func 7 - PCI slot 2 */
477 0x9700 0 0 1 &mpic 3 1
478 0x9700 0 0 2 &mpic 4 1
479 0x9700 0 0 3 &mpic 1 1
480 0x9700 0 0 4 &mpic 2 1
482 // IDSEL 0x1c USB
483 0xe000 0 0 1 &i8259 12 2
484 0xe100 0 0 2 &i8259 9 2
485 0xe200 0 0 3 &i8259 10 2
486 0xe300 0 0 4 &i8259 11 2
488 // IDSEL 0x1d Audio
489 0xe800 0 0 1 &i8259 6 2
491 // IDSEL 0x1e Legacy
492 0xf000 0 0 1 &i8259 7 2
493 0xf100 0 0 1 &i8259 7 2
495 // IDSEL 0x1f IDE/SATA
496 0xf800 0 0 1 &i8259 14 2
497 0xf900 0 0 1 &i8259 5 2
498 >;
500 pcie@0 {
501 reg = <0 0 0 0 0>;
502 #size-cells = <2>;
503 #address-cells = <3>;
504 device_type = "pci";
505 ranges = <0x02000000 0x0 0x80000000
506 0x02000000 0x0 0x80000000
507 0x0 0x20000000
509 0x01000000 0x0 0x00000000
510 0x01000000 0x0 0x00000000
511 0x0 0x00010000>;
512 uli1575@0 {
513 reg = <0 0 0 0 0>;
514 #size-cells = <2>;
515 #address-cells = <3>;
516 ranges = <0x02000000 0x0 0x80000000
517 0x02000000 0x0 0x80000000
518 0x0 0x20000000
519 0x01000000 0x0 0x00000000
520 0x01000000 0x0 0x00000000
521 0x0 0x00010000>;
522 isa@1e {
523 device_type = "isa";
524 #interrupt-cells = <2>;
525 #size-cells = <1>;
526 #address-cells = <2>;
527 reg = <0xf000 0 0 0 0>;
528 ranges = <1 0 0x01000000 0 0
529 0x00001000>;
530 interrupt-parent = <&i8259>;
532 i8259: interrupt-controller@20 {
533 reg = <1 0x20 2
534 1 0xa0 2
535 1 0x4d0 2>;
536 interrupt-controller;
537 device_type = "interrupt-controller";
538 #address-cells = <0>;
539 #interrupt-cells = <2>;
540 compatible = "chrp,iic";
541 interrupts = <9 2>;
542 interrupt-parent = <&mpic>;
543 };
545 i8042@60 {
546 #size-cells = <0>;
547 #address-cells = <1>;
548 reg = <1 0x60 1 1 0x64 1>;
549 interrupts = <1 3 12 3>;
550 interrupt-parent =
551 <&i8259>;
553 keyboard@0 {
554 reg = <0>;
555 compatible = "pnpPNP,303";
556 };
558 mouse@1 {
559 reg = <1>;
560 compatible = "pnpPNP,f03";
561 };
562 };
564 rtc@70 {
565 compatible =
566 "pnpPNP,b00";
567 reg = <1 0x70 2>;
568 };
570 gpio@400 {
571 reg = <1 0x400 0x80>;
572 };
573 };
574 };
575 };
577 };
579 pci1: pcie@ffe09000 {
580 compatible = "fsl,mpc8641-pcie";
581 device_type = "pci";
582 #interrupt-cells = <1>;
583 #size-cells = <2>;
584 #address-cells = <3>;
585 reg = <0xffe09000 0x1000>;
586 bus-range = <0 0xff>;
587 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
588 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
589 clock-frequency = <33333333>;
590 interrupt-parent = <&mpic>;
591 interrupts = <25 2>;
592 interrupt-map-mask = <0xf800 0 0 7>;
593 interrupt-map = <
594 /* IDSEL 0x0 */
595 0x0000 0 0 1 &mpic 4 1
596 0x0000 0 0 2 &mpic 5 1
597 0x0000 0 0 3 &mpic 6 1
598 0x0000 0 0 4 &mpic 7 1
599 >;
600 pcie@0 {
601 reg = <0 0 0 0 0>;
602 #size-cells = <2>;
603 #address-cells = <3>;
604 device_type = "pci";
605 ranges = <0x02000000 0x0 0xa0000000
606 0x02000000 0x0 0xa0000000
607 0x0 0x20000000
609 0x01000000 0x0 0x00000000
610 0x01000000 0x0 0x00000000
611 0x0 0x00010000>;
612 };
613 };
614 /*
615 rapidio0: rapidio@ffec0000 {
616 #address-cells = <2>;
617 #size-cells = <2>;
618 compatible = "fsl,rapidio-delta";
619 reg = <0xffec0000 0x20000>;
620 ranges = <0 0 0x80000000 0 0x20000000>;
621 interrupt-parent = <&mpic>;
622 // err_irq bell_outb_irq bell_inb_irq
623 // msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq
624 interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;
625 };
626 */
628 };