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Linux 2.6.31.6
[linux/fpc-iii.git] / arch / powerpc / kernel / ppc970-pmu.c
blob75dccb71a04337fc3f26dd0902de37e279886651
1 /*
2 * Performance counter support for PPC970-family processors.
3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11 #include <linux/string.h>
12 #include <linux/perf_counter.h>
13 #include <asm/reg.h>
14 #include <asm/cputable.h>
15
16 /*
17 * Bits in event code for PPC970
18 */
19 #define PM_PMC_SH 12 /* PMC number (1-based) for direct events */
20 #define PM_PMC_MSK 0xf
21 #define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */
22 #define PM_UNIT_MSK 0xf
23 #define PM_SPCSEL_SH 6
24 #define PM_SPCSEL_MSK 3
25 #define PM_BYTE_SH 4 /* Byte number of event bus to use */
26 #define PM_BYTE_MSK 3
27 #define PM_PMCSEL_MSK 0xf
28
29 /* Values in PM_UNIT field */
30 #define PM_NONE 0
31 #define PM_FPU 1
32 #define PM_VPU 2
33 #define PM_ISU 3
34 #define PM_IFU 4
35 #define PM_IDU 5
36 #define PM_STS 6
37 #define PM_LSU0 7
38 #define PM_LSU1U 8
39 #define PM_LSU1L 9
40 #define PM_LASTUNIT 9
41
42 /*
43 * Bits in MMCR0 for PPC970
44 */
45 #define MMCR0_PMC1SEL_SH 8
46 #define MMCR0_PMC2SEL_SH 1
47 #define MMCR_PMCSEL_MSK 0x1f
48
49 /*
50 * Bits in MMCR1 for PPC970
51 */
52 #define MMCR1_TTM0SEL_SH 62
53 #define MMCR1_TTM1SEL_SH 59
54 #define MMCR1_TTM3SEL_SH 53
55 #define MMCR1_TTMSEL_MSK 3
56 #define MMCR1_TD_CP_DBG0SEL_SH 50
57 #define MMCR1_TD_CP_DBG1SEL_SH 48
58 #define MMCR1_TD_CP_DBG2SEL_SH 46
59 #define MMCR1_TD_CP_DBG3SEL_SH 44
60 #define MMCR1_PMC1_ADDER_SEL_SH 39
61 #define MMCR1_PMC2_ADDER_SEL_SH 38
62 #define MMCR1_PMC6_ADDER_SEL_SH 37
63 #define MMCR1_PMC5_ADDER_SEL_SH 36
64 #define MMCR1_PMC8_ADDER_SEL_SH 35
65 #define MMCR1_PMC7_ADDER_SEL_SH 34
66 #define MMCR1_PMC3_ADDER_SEL_SH 33
67 #define MMCR1_PMC4_ADDER_SEL_SH 32
68 #define MMCR1_PMC3SEL_SH 27
69 #define MMCR1_PMC4SEL_SH 22
70 #define MMCR1_PMC5SEL_SH 17
71 #define MMCR1_PMC6SEL_SH 12
72 #define MMCR1_PMC7SEL_SH 7
73 #define MMCR1_PMC8SEL_SH 2
74
75 static short mmcr1_adder_bits[8] = {
76 MMCR1_PMC1_ADDER_SEL_SH,
77 MMCR1_PMC2_ADDER_SEL_SH,
78 MMCR1_PMC3_ADDER_SEL_SH,
79 MMCR1_PMC4_ADDER_SEL_SH,
80 MMCR1_PMC5_ADDER_SEL_SH,
81 MMCR1_PMC6_ADDER_SEL_SH,
82 MMCR1_PMC7_ADDER_SEL_SH,
83 MMCR1_PMC8_ADDER_SEL_SH
84 };
85
86 /*
87 * Bits in MMCRA
88 */
89
90 /*
91 * Layout of constraint bits:
92 * 6666555555555544444444443333333333222222222211111111110000000000
93 * 3210987654321098765432109876543210987654321098765432109876543210
94 * <><><>[ >[ >[ >< >< >< >< ><><><><><><><><>
95 * SPT0T1 UC PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8
96 *
97 * SP - SPCSEL constraint
98 * 48-49: SPCSEL value 0x3_0000_0000_0000
99 *
100 * T0 - TTM0 constraint
101 * 46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
102 *
103 * T1 - TTM1 constraint
104 * 44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
105 *
106 * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS
107 * 43: UC3 error 0x0800_0000_0000
108 * 42: FPU|IFU|VPU events needed 0x0400_0000_0000
109 * 41: ISU events needed 0x0200_0000_0000
110 * 40: IDU|STS events needed 0x0100_0000_0000
111 *
112 * PS1
113 * 39: PS1 error 0x0080_0000_0000
114 * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
115 *
116 * PS2
117 * 35: PS2 error 0x0008_0000_0000
118 * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
119 *
120 * B0
121 * 28-31: Byte 0 event source 0xf000_0000
122 * Encoding as for the event code
123 *
124 * B1, B2, B3
125 * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
126 *
127 * P1
128 * 15: P1 error 0x8000
129 * 14-15: Count of events needing PMC1
130 *
131 * P2..P8
132 * 0-13: Count of events needing PMC2..PMC8
133 */
134
135 static unsigned char direct_marked_event[8] = {
136 (1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
137 (1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
138 (1<<3) | (1<<5), /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */
139 (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
140 (1<<4) | (1<<5), /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
141 (1<<3) | (1<<4) | (1<<5),
142 /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
143 (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
144 (1<<4) /* PMC8: PM_MRK_LSU_FIN */
145 };
146
147 /*
148 * Returns 1 if event counts things relating to marked instructions
149 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
150 */
151 static int p970_marked_instr_event(u64 event)
152 {
153 int pmc, psel, unit, byte, bit;
154 unsigned int mask;
155
156 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
157 psel = event & PM_PMCSEL_MSK;
158 if (pmc) {
159 if (direct_marked_event[pmc - 1] & (1 << psel))
160 return 1;
161 if (psel == 0) /* add events */
162 bit = (pmc <= 4)? pmc - 1: 8 - pmc;
163 else if (psel == 7 || psel == 13) /* decode events */
164 bit = 4;
165 else
166 return 0;
167 } else
168 bit = psel;
169
170 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
171 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
172 mask = 0;
173 switch (unit) {
174 case PM_VPU:
175 mask = 0x4c; /* byte 0 bits 2,3,6 */
176 case PM_LSU0:
177 /* byte 2 bits 0,2,3,4,6; all of byte 1 */
178 mask = 0x085dff00;
179 case PM_LSU1L:
180 mask = 0x50 << 24; /* byte 3 bits 4,6 */
181 break;
182 }
183 return (mask >> (byte * 8 + bit)) & 1;
184 }
185
186 /* Masks and values for using events from the various units */
187 static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
188 [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull },
189 [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull },
190 [PM_ISU] = { 0x080000000000ull, 0x020000000000ull },
191 [PM_IFU] = { 0xc80000000000ull, 0x840000000000ull },
192 [PM_IDU] = { 0x380000000000ull, 0x010000000000ull },
193 [PM_STS] = { 0x380000000000ull, 0x310000000000ull },
194 };
195
196 static int p970_get_constraint(u64 event, unsigned long *maskp,
197 unsigned long *valp)
198 {
199 int pmc, byte, unit, sh, spcsel;
200 unsigned long mask = 0, value = 0;
201 int grp = -1;
202
203 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
204 if (pmc) {
205 if (pmc > 8)
206 return -1;
207 sh = (pmc - 1) * 2;
208 mask |= 2 << sh;
209 value |= 1 << sh;
210 grp = ((pmc - 1) >> 1) & 1;
211 }
212 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
213 if (unit) {
214 if (unit > PM_LASTUNIT)
215 return -1;
216 mask |= unit_cons[unit][0];
217 value |= unit_cons[unit][1];
218 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
219 /*
220 * Bus events on bytes 0 and 2 can be counted
221 * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
222 */
223 if (!pmc)
224 grp = byte & 1;
225 /* Set byte lane select field */
226 mask |= 0xfULL << (28 - 4 * byte);
227 value |= (unsigned long)unit << (28 - 4 * byte);
228 }
229 if (grp == 0) {
230 /* increment PMC1/2/5/6 field */
231 mask |= 0x8000000000ull;
232 value |= 0x1000000000ull;
233 } else if (grp == 1) {
234 /* increment PMC3/4/7/8 field */
235 mask |= 0x800000000ull;
236 value |= 0x100000000ull;
237 }
238 spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
239 if (spcsel) {
240 mask |= 3ull << 48;
241 value |= (unsigned long)spcsel << 48;
242 }
243 *maskp = mask;
244 *valp = value;
245 return 0;
246 }
247
248 static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
249 {
250 alt[0] = event;
251
252 /* 2 alternatives for LSU empty */
253 if (event == 0x2002 || event == 0x3002) {
254 alt[1] = event ^ 0x1000;
255 return 2;
256 }
257
258 return 1;
259 }
260
261 static int p970_compute_mmcr(u64 event[], int n_ev,
262 unsigned int hwc[], unsigned long mmcr[])
263 {
264 unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
265 unsigned int pmc, unit, byte, psel;
266 unsigned int ttm, grp;
267 unsigned int pmc_inuse = 0;
268 unsigned int pmc_grp_use[2];
269 unsigned char busbyte[4];
270 unsigned char unituse[16];
271 unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };
272 unsigned char ttmuse[2];
273 unsigned char pmcsel[8];
274 int i;
275 int spcsel;
276
277 if (n_ev > 8)
278 return -1;
279
280 /* First pass to count resource use */
281 pmc_grp_use[0] = pmc_grp_use[1] = 0;
282 memset(busbyte, 0, sizeof(busbyte));
283 memset(unituse, 0, sizeof(unituse));
284 for (i = 0; i < n_ev; ++i) {
285 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
286 if (pmc) {
287 if (pmc_inuse & (1 << (pmc - 1)))
288 return -1;
289 pmc_inuse |= 1 << (pmc - 1);
290 /* count 1/2/5/6 vs 3/4/7/8 use */
291 ++pmc_grp_use[((pmc - 1) >> 1) & 1];
292 }
293 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
294 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
295 if (unit) {
296 if (unit > PM_LASTUNIT)
297 return -1;
298 if (!pmc)
299 ++pmc_grp_use[byte & 1];
300 if (busbyte[byte] && busbyte[byte] != unit)
301 return -1;
302 busbyte[byte] = unit;
303 unituse[unit] = 1;
304 }
305 }
306 if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
307 return -1;
308
309 /*
310 * Assign resources and set multiplexer selects.
311 *
312 * PM_ISU can go either on TTM0 or TTM1, but that's the only
313 * choice we have to deal with.
314 */
315 if (unituse[PM_ISU] &
316 (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU]))
317 unitmap[PM_ISU] = 2 | 4; /* move ISU to TTM1 */
318 /* Set TTM[01]SEL fields. */
319 ttmuse[0] = ttmuse[1] = 0;
320 for (i = PM_FPU; i <= PM_STS; ++i) {
321 if (!unituse[i])
322 continue;
323 ttm = unitmap[i];
324 ++ttmuse[(ttm >> 2) & 1];
325 mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH;
326 }
327 /* Check only one unit per TTMx */
328 if (ttmuse[0] > 1 || ttmuse[1] > 1)
329 return -1;
330
331 /* Set byte lane select fields and TTM3SEL. */
332 for (byte = 0; byte < 4; ++byte) {
333 unit = busbyte[byte];
334 if (!unit)
335 continue;
336 if (unit <= PM_STS)
337 ttm = (unitmap[unit] >> 2) & 1;
338 else if (unit == PM_LSU0)
339 ttm = 2;
340 else {
341 ttm = 3;
342 if (unit == PM_LSU1L && byte >= 2)
343 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
344 }
345 mmcr1 |= (unsigned long)ttm
346 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
347 }
348
349 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
350 memset(pmcsel, 0x8, sizeof(pmcsel)); /* 8 means don't count */
351 for (i = 0; i < n_ev; ++i) {
352 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
353 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
354 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
355 psel = event[i] & PM_PMCSEL_MSK;
356 if (!pmc) {
357 /* Bus event or any-PMC direct event */
358 if (unit)
359 psel |= 0x10 | ((byte & 2) << 2);
360 else
361 psel |= 8;
362 for (pmc = 0; pmc < 8; ++pmc) {
363 if (pmc_inuse & (1 << pmc))
364 continue;
365 grp = (pmc >> 1) & 1;
366 if (unit) {
367 if (grp == (byte & 1))
368 break;
369 } else if (pmc_grp_use[grp] < 4) {
370 ++pmc_grp_use[grp];
371 break;
372 }
373 }
374 pmc_inuse |= 1 << pmc;
375 } else {
376 /* Direct event */
377 --pmc;
378 if (psel == 0 && (byte & 2))
379 /* add events on higher-numbered bus */
380 mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
381 }
382 pmcsel[pmc] = psel;
383 hwc[i] = pmc;
384 spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
385 mmcr1 |= spcsel;
386 if (p970_marked_instr_event(event[i]))
387 mmcra |= MMCRA_SAMPLE_ENABLE;
388 }
389 for (pmc = 0; pmc < 2; ++pmc)
390 mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
391 for (; pmc < 8; ++pmc)
392 mmcr1 |= (unsigned long)pmcsel[pmc]
393 << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
394 if (pmc_inuse & 1)
395 mmcr0 |= MMCR0_PMC1CE;
396 if (pmc_inuse & 0xfe)
397 mmcr0 |= MMCR0_PMCjCE;
398
399 mmcra |= 0x2000; /* mark only one IOP per PPC instruction */
400
401 /* Return MMCRx values */
402 mmcr[0] = mmcr0;
403 mmcr[1] = mmcr1;
404 mmcr[2] = mmcra;
405 return 0;
406 }
407
408 static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[])
409 {
410 int shift, i;
411
412 if (pmc <= 1) {
413 shift = MMCR0_PMC1SEL_SH - 7 * pmc;
414 i = 0;
415 } else {
416 shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
417 i = 1;
418 }
419 /*
420 * Setting the PMCxSEL field to 0x08 disables PMC x.
421 */
422 mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift);
423 }
424
425 static int ppc970_generic_events[] = {
426 [PERF_COUNT_HW_CPU_CYCLES] = 7,
427 [PERF_COUNT_HW_INSTRUCTIONS] = 1,
428 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x8810, /* PM_LD_REF_L1 */
429 [PERF_COUNT_HW_CACHE_MISSES] = 0x3810, /* PM_LD_MISS_L1 */
430 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x431, /* PM_BR_ISSUED */
431 [PERF_COUNT_HW_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */
432 };
433
434 #define C(x) PERF_COUNT_HW_CACHE_##x
435
436 /*
437 * Table of generalized cache-related events.
438 * 0 means not supported, -1 means nonsensical, other values
439 * are event codes.
440 */
441 static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
442 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
443 [C(OP_READ)] = { 0x8810, 0x3810 },
444 [C(OP_WRITE)] = { 0x7810, 0x813 },
445 [C(OP_PREFETCH)] = { 0x731, 0 },
446 },
447 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
448 [C(OP_READ)] = { 0, 0 },
449 [C(OP_WRITE)] = { -1, -1 },
450 [C(OP_PREFETCH)] = { 0, 0 },
451 },
452 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
453 [C(OP_READ)] = { 0, 0 },
454 [C(OP_WRITE)] = { 0, 0 },
455 [C(OP_PREFETCH)] = { 0x733, 0 },
456 },
457 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
458 [C(OP_READ)] = { 0, 0x704 },
459 [C(OP_WRITE)] = { -1, -1 },
460 [C(OP_PREFETCH)] = { -1, -1 },
461 },
462 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
463 [C(OP_READ)] = { 0, 0x700 },
464 [C(OP_WRITE)] = { -1, -1 },
465 [C(OP_PREFETCH)] = { -1, -1 },
466 },
467 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
468 [C(OP_READ)] = { 0x431, 0x327 },
469 [C(OP_WRITE)] = { -1, -1 },
470 [C(OP_PREFETCH)] = { -1, -1 },
471 },
472 };
473
474 static struct power_pmu ppc970_pmu = {
475 .name = "PPC970/FX/MP",
476 .n_counter = 8,
477 .max_alternatives = 2,
478 .add_fields = 0x001100005555ull,
479 .test_adder = 0x013300000000ull,
480 .compute_mmcr = p970_compute_mmcr,
481 .get_constraint = p970_get_constraint,
482 .get_alternatives = p970_get_alternatives,
483 .disable_pmc = p970_disable_pmc,
484 .n_generic = ARRAY_SIZE(ppc970_generic_events),
485 .generic_events = ppc970_generic_events,
486 .cache_events = &ppc970_cache_events,
487 };
488
489 static int init_ppc970_pmu(void)
490 {
491 if (!cur_cpu_spec->oprofile_cpu_type ||
492 (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970")
493 && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970MP")))
494 return -ENODEV;
495
496 return register_power_pmu(&ppc970_pmu);
497 }
498
499 arch_initcall(init_ppc970_pmu);
Linux with added FPC-III support