arch/powerpc/mm/pgtable.c

   1 /*
   2  * This file contains common routines for dealing with free of page tables
   3  * Along with common page table handling code
   4  *
   5  *  Derived from arch/powerpc/mm/tlb_64.c:
   6  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   7  *
   8  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
   9  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  10  *    Copyright (C) 1996 Paul Mackerras
  11  *
  12  *  Derived from "arch/i386/mm/init.c"
  13  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  14  *
  15  *  Dave Engebretsen <engebret@us.ibm.com>
  16  *      Rework for PPC64 port.
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/init.h>
  27 #include <linux/percpu.h>
  28 #include <linux/hardirq.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/tlbflush.h>
  31 #include <asm/tlb.h>
  32
  33 #include "mmu_decl.h"
  34
  35 static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
  36 static unsigned long pte_freelist_forced_free;
  37
  38 struct pte_freelist_batch
  39 {
  40         struct rcu_head rcu;
  41         unsigned int    index;
  42         pgtable_free_t  tables[0];
  43 };
  44
  45 #define PTE_FREELIST_SIZE \
  46         ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
  47           / sizeof(pgtable_free_t))
  48
  49 static void pte_free_smp_sync(void *arg)
  50 {
  51         /* Do nothing, just ensure we sync with all CPUs */
  52 }
  53
  54 /* This is only called when we are critically out of memory
  55  * (and fail to get a page in pte_free_tlb).
  56  */
  57 static void pgtable_free_now(pgtable_free_t pgf)
  58 {
  59         pte_freelist_forced_free++;
  60
  61         smp_call_function(pte_free_smp_sync, NULL, 1);
  62
  63         pgtable_free(pgf);
  64 }
  65
  66 static void pte_free_rcu_callback(struct rcu_head *head)
  67 {
  68         struct pte_freelist_batch *batch =
  69                 container_of(head, struct pte_freelist_batch, rcu);
  70         unsigned int i;
  71
  72         for (i = 0; i < batch->index; i++)
  73                 pgtable_free(batch->tables[i]);
  74
  75         free_page((unsigned long)batch);
  76 }
  77
  78 static void pte_free_submit(struct pte_freelist_batch *batch)
  79 {
  80         INIT_RCU_HEAD(&batch->rcu);
  81         call_rcu(&batch->rcu, pte_free_rcu_callback);
  82 }
  83
  84 void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
  85 {
  86         /* This is safe since tlb_gather_mmu has disabled preemption */
  87         struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
  88
  89         if (atomic_read(&tlb->mm->mm_users) < 2 ||
  90             cpumask_equal(mm_cpumask(tlb->mm), cpumask_of(smp_processor_id()))){
  91                 pgtable_free(pgf);
  92                 return;
  93         }
  94
  95         if (*batchp == NULL) {
  96                 *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
  97                 if (*batchp == NULL) {
  98                         pgtable_free_now(pgf);
  99                         return;
 100                 }
 101                 (*batchp)->index = 0;
 102         }
 103         (*batchp)->tables[(*batchp)->index++] = pgf;
 104         if ((*batchp)->index == PTE_FREELIST_SIZE) {
 105                 pte_free_submit(*batchp);
 106                 *batchp = NULL;
 107         }
 108 }
 109
 110 void pte_free_finish(void)
 111 {
 112         /* This is safe since tlb_gather_mmu has disabled preemption */
 113         struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
 114
 115         if (*batchp == NULL)
 116                 return;
 117         pte_free_submit(*batchp);
 118         *batchp = NULL;
 119 }
 120
 121 /*
 122  * Handle i/d cache flushing, called from set_pte_at() or ptep_set_access_flags()
 123  */
 124 static pte_t do_dcache_icache_coherency(pte_t pte, unsigned long addr)
 125 {
 126         unsigned long pfn = pte_pfn(pte);
 127         struct page *page;
 128
 129         if (unlikely(!pfn_valid(pfn)))
 130                 return pte;
 131         page = pfn_to_page(pfn);
 132
 133 #ifdef CONFIG_8xx
 134        /* On 8xx, cache control instructions (particularly
 135         * "dcbst" from flush_dcache_icache) fault as write
 136         * operation if there is an unpopulated TLB entry
 137         * for the address in question. To workaround that,
 138         * we invalidate the TLB here, thus avoiding dcbst
 139         * misbehaviour.
 140         */
 141        _tlbil_va(addr, 0 /* 8xx doesn't care about PID */);
 142 #endif
 143
 144         if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)) {
 145                 pr_devel("do_dcache_icache_coherency... flushing\n");
 146                 flush_dcache_icache_page(page);
 147                 set_bit(PG_arch_1, &page->flags);
 148         }
 149         else
 150                 pr_devel("do_dcache_icache_coherency... already clean\n");
 151         return __pte(pte_val(pte) | _PAGE_HWEXEC);
 152 }
 153
 154 static inline int is_exec_fault(void)
 155 {
 156         return current->thread.regs && TRAP(current->thread.regs) == 0x400;
 157 }
 158
 159 /* We only try to do i/d cache coherency on stuff that looks like
 160  * reasonably "normal" PTEs. We currently require a PTE to be present
 161  * and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE
 162  */
 163 static inline int pte_looks_normal(pte_t pte)
 164 {
 165         return (pte_val(pte) &
 166                 (_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE)) ==
 167                 (_PAGE_PRESENT);
 168 }
 169
 170 #if defined(CONFIG_PPC_STD_MMU)
 171 /* Server-style MMU handles coherency when hashing if HW exec permission
 172  * is supposed per page (currently 64-bit only). Else, we always flush
 173  * valid PTEs in set_pte.
 174  */
 175 static inline int pte_need_exec_flush(pte_t pte, int set_pte)
 176 {
 177         return set_pte && pte_looks_normal(pte) &&
 178                 !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
 179                   cpu_has_feature(CPU_FTR_NOEXECUTE));
 180 }
 181 #elif _PAGE_HWEXEC == 0
 182 /* Embedded type MMU without HW exec support (8xx only so far), we flush
 183  * the cache for any present PTE
 184  */
 185 static inline int pte_need_exec_flush(pte_t pte, int set_pte)
 186 {
 187         return set_pte && pte_looks_normal(pte);
 188 }
 189 #else
 190 /* Other embedded CPUs with HW exec support per-page, we flush on exec
 191  * fault if HWEXEC is not set
 192  */
 193 static inline int pte_need_exec_flush(pte_t pte, int set_pte)
 194 {
 195         return pte_looks_normal(pte) && is_exec_fault() &&
 196                 !(pte_val(pte) & _PAGE_HWEXEC);
 197 }
 198 #endif
 199
 200 /*
 201  * set_pte stores a linux PTE into the linux page table.
 202  */
 203 void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
 204 {
 205 #ifdef CONFIG_DEBUG_VM
 206         WARN_ON(pte_present(*ptep));
 207 #endif
 208         /* Note: mm->context.id might not yet have been assigned as
 209          * this context might not have been activated yet when this
 210          * is called.
 211          */
 212         pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
 213         if (pte_need_exec_flush(pte, 1))
 214                 pte = do_dcache_icache_coherency(pte, addr);
 215
 216         /* Perform the setting of the PTE */
 217         __set_pte_at(mm, addr, ptep, pte, 0);
 218 }
 219
 220 /*
 221  * This is called when relaxing access to a PTE. It's also called in the page
 222  * fault path when we don't hit any of the major fault cases, ie, a minor
 223  * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
 224  * handled those two for us, we additionally deal with missing execute
 225  * permission here on some processors
 226  */
 227 int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
 228                           pte_t *ptep, pte_t entry, int dirty)
 229 {
 230         int changed;
 231         if (!dirty && pte_need_exec_flush(entry, 0))
 232                 entry = do_dcache_icache_coherency(entry, address);
 233         changed = !pte_same(*(ptep), entry);
 234         if (changed) {
 235                 if (!(vma->vm_flags & VM_HUGETLB))
 236                         assert_pte_locked(vma->vm_mm, address);
 237                 __ptep_set_access_flags(ptep, entry);
 238                 flush_tlb_page_nohash(vma, address);
 239         }
 240         return changed;
 241 }
 242
 243 #ifdef CONFIG_DEBUG_VM
 244 void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
 245 {
 246         pgd_t *pgd;
 247         pud_t *pud;
 248         pmd_t *pmd;
 249
 250         if (mm == &init_mm)
 251                 return;
 252         pgd = mm->pgd + pgd_index(addr);
 253         BUG_ON(pgd_none(*pgd));
 254         pud = pud_offset(pgd, addr);
 255         BUG_ON(pud_none(*pud));
 256         pmd = pmd_offset(pud, addr);
 257         BUG_ON(!pmd_present(*pmd));
 258         BUG_ON(!spin_is_locked(pte_lockptr(mm, pmd)));
 259 }
 260 #endif /* CONFIG_DEBUG_VM */
 261