Linux 2.6.31.6
[linux/fpc-iii.git] / arch / x86 / kernel / visws_quirks.c
blob31ffc24eec4d6f7e3a84cd7d5a11cc8a5b6e18d2
1 /*
2 * SGI Visual Workstation support and quirks, unmaintained.
4 * Split out from setup.c by davej@suse.de
6 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
8 * SGI Visual Workstation interrupt controller
10 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
11 * which serves as the main interrupt controller in the system. Non-legacy
12 * hardware in the system uses this controller directly. Legacy devices
13 * are connected to the PIIX4 which in turn has its 8259(s) connected to
14 * a of the Cobalt APIC entry.
16 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
18 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/smp.h>
25 #include <asm/visws/cobalt.h>
26 #include <asm/visws/piix4.h>
27 #include <asm/io_apic.h>
28 #include <asm/fixmap.h>
29 #include <asm/reboot.h>
30 #include <asm/setup.h>
31 #include <asm/apic.h>
32 #include <asm/e820.h>
33 #include <asm/io.h>
35 #include <linux/kernel_stat.h>
37 #include <asm/i8259.h>
38 #include <asm/irq_vectors.h>
39 #include <asm/visws/lithium.h>
41 #include <linux/sched.h>
42 #include <linux/kernel.h>
43 #include <linux/pci.h>
44 #include <linux/pci_ids.h>
46 extern int no_broadcast;
48 char visws_board_type = -1;
49 char visws_board_rev = -1;
51 int is_visws_box(void)
53 return visws_board_type >= 0;
56 static int __init visws_time_init(void)
58 printk(KERN_INFO "Starting Cobalt Timer system clock\n");
60 /* Set the countdown value */
61 co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
63 /* Start the timer */
64 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
66 /* Enable (unmask) the timer interrupt */
67 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
70 * Zero return means the generic timer setup code will set up
71 * the standard vector:
73 return 0;
76 static int __init visws_pre_intr_init(void)
78 init_VISWS_APIC_irqs();
81 * We dont want ISA irqs to be set up by the generic code:
83 return 1;
86 /* Quirk for machine specific memory setup. */
88 #define MB (1024 * 1024)
90 unsigned long sgivwfb_mem_phys;
91 unsigned long sgivwfb_mem_size;
92 EXPORT_SYMBOL(sgivwfb_mem_phys);
93 EXPORT_SYMBOL(sgivwfb_mem_size);
95 long long mem_size __initdata = 0;
97 static char * __init visws_memory_setup(void)
99 long long gfx_mem_size = 8 * MB;
101 mem_size = boot_params.alt_mem_k;
103 if (!mem_size) {
104 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
105 mem_size = 128 * MB;
109 * this hardcodes the graphics memory to 8 MB
110 * it really should be sized dynamically (or at least
111 * set as a boot param)
113 if (!sgivwfb_mem_size) {
114 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
115 sgivwfb_mem_size = 8 * MB;
119 * Trim to nearest MB
121 sgivwfb_mem_size &= ~((1 << 20) - 1);
122 sgivwfb_mem_phys = mem_size - gfx_mem_size;
124 e820_add_region(0, LOWMEMSIZE(), E820_RAM);
125 e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
126 e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
128 return "PROM";
131 static void visws_machine_emergency_restart(void)
134 * Visual Workstations restart after this
135 * register is poked on the PIIX4
137 outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
140 static void visws_machine_power_off(void)
142 unsigned short pm_status;
143 /* extern unsigned int pci_bus0; */
145 while ((pm_status = inw(PMSTS_PORT)) & 0x100)
146 outw(pm_status, PMSTS_PORT);
148 outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
150 mdelay(10);
152 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
153 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
155 /* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
156 outl(PIIX_SPECIAL_STOP, 0xCFC);
159 static int __init visws_get_smp_config(unsigned int early)
162 * Prevent MP-table parsing by the generic code:
164 return 1;
168 * The Visual Workstation is Intel MP compliant in the hardware
169 * sense, but it doesn't have a BIOS(-configuration table).
170 * No problem for Linux.
173 static void __init MP_processor_info(struct mpc_cpu *m)
175 int ver, logical_apicid;
176 physid_mask_t apic_cpus;
178 if (!(m->cpuflag & CPU_ENABLED))
179 return;
181 logical_apicid = m->apicid;
182 printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
183 m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
184 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
185 (m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);
187 if (m->cpuflag & CPU_BOOTPROCESSOR)
188 boot_cpu_physical_apicid = m->apicid;
190 ver = m->apicver;
191 if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
192 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
193 m->apicid, MAX_APICS);
194 return;
197 apic_cpus = apic->apicid_to_cpu_present(m->apicid);
198 physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
200 * Validate version
202 if (ver == 0x0) {
203 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
204 "fixing up to 0x10. (tell your hw vendor)\n",
205 m->apicid);
206 ver = 0x10;
208 apic_version[m->apicid] = ver;
211 static int __init visws_find_smp_config(unsigned int reserve)
213 struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
214 unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
216 if (ncpus > CO_CPU_MAX) {
217 printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
218 ncpus, mp);
220 ncpus = CO_CPU_MAX;
223 if (ncpus > setup_max_cpus)
224 ncpus = setup_max_cpus;
226 #ifdef CONFIG_X86_LOCAL_APIC
227 smp_found_config = 1;
228 #endif
229 while (ncpus--)
230 MP_processor_info(mp++);
232 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
234 return 1;
237 static int visws_trap_init(void);
239 static struct x86_quirks visws_x86_quirks __initdata = {
240 .arch_time_init = visws_time_init,
241 .arch_pre_intr_init = visws_pre_intr_init,
242 .arch_memory_setup = visws_memory_setup,
243 .arch_intr_init = NULL,
244 .arch_trap_init = visws_trap_init,
245 .mach_get_smp_config = visws_get_smp_config,
246 .mach_find_smp_config = visws_find_smp_config,
249 void __init visws_early_detect(void)
251 int raw;
253 visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
254 >> PIIX_GPI_BD_SHIFT;
256 if (visws_board_type < 0)
257 return;
260 * Install special quirks for timer, interrupt and memory setup:
261 * Fall back to generic behavior for traps:
262 * Override generic MP-table parsing:
264 x86_quirks = &visws_x86_quirks;
267 * Install reboot quirks:
269 pm_power_off = visws_machine_power_off;
270 machine_ops.emergency_restart = visws_machine_emergency_restart;
273 * Do not use broadcast IPIs:
275 no_broadcast = 0;
277 #ifdef CONFIG_X86_IO_APIC
279 * Turn off IO-APIC detection and initialization:
281 skip_ioapic_setup = 1;
282 #endif
285 * Get Board rev.
286 * First, we have to initialize the 307 part to allow us access
287 * to the GPIO registers. Let's map them at 0x0fc0 which is right
288 * after the PIIX4 PM section.
290 outb_p(SIO_DEV_SEL, SIO_INDEX);
291 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
293 outb_p(SIO_DEV_MSB, SIO_INDEX);
294 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
296 outb_p(SIO_DEV_LSB, SIO_INDEX);
297 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
299 outb_p(SIO_DEV_ENB, SIO_INDEX);
300 outb_p(1, SIO_DATA); /* Enable GPIO registers. */
303 * Now, we have to map the power management section to write
304 * a bit which enables access to the GPIO registers.
305 * What lunatic came up with this shit?
307 outb_p(SIO_DEV_SEL, SIO_INDEX);
308 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
310 outb_p(SIO_DEV_MSB, SIO_INDEX);
311 outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
313 outb_p(SIO_DEV_LSB, SIO_INDEX);
314 outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
316 outb_p(SIO_DEV_ENB, SIO_INDEX);
317 outb_p(1, SIO_DATA); /* Enable PM registers. */
320 * Now, write the PM register which enables the GPIO registers.
322 outb_p(SIO_PM_FER2, SIO_PM_INDEX);
323 outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
326 * Now, initialize the GPIO registers.
327 * We want them all to be inputs which is the
328 * power on default, so let's leave them alone.
329 * So, let's just read the board rev!
331 raw = inb_p(SIO_GP_DATA1);
332 raw &= 0x7f; /* 7 bits of valid board revision ID. */
334 if (visws_board_type == VISWS_320) {
335 if (raw < 0x6) {
336 visws_board_rev = 4;
337 } else if (raw < 0xc) {
338 visws_board_rev = 5;
339 } else {
340 visws_board_rev = 6;
342 } else if (visws_board_type == VISWS_540) {
343 visws_board_rev = 2;
344 } else {
345 visws_board_rev = raw;
348 printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
349 (visws_board_type == VISWS_320 ? "320" :
350 (visws_board_type == VISWS_540 ? "540" :
351 "unknown")), visws_board_rev);
354 #define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
355 #define BCD (LI_INTB | LI_INTC | LI_INTD)
356 #define ALLDEVS (A01234 | BCD)
358 static __init void lithium_init(void)
360 set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
361 set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
363 if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
364 (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
365 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
366 /* panic("This machine is not SGI Visual Workstation 320/540"); */
369 if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
370 (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
371 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
372 /* panic("This machine is not SGI Visual Workstation 320/540"); */
375 li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
376 li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
379 static __init void cobalt_init(void)
382 * On normal SMP PC this is used only with SMP, but we have to
383 * use it and set it up here to start the Cobalt clock
385 set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
386 setup_local_APIC();
387 printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
388 (unsigned int)apic_read(APIC_LVR),
389 (unsigned int)apic_read(APIC_ID));
391 set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
392 set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
393 printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
394 co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
396 /* Enable Cobalt APIC being careful to NOT change the ID! */
397 co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
399 printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
400 co_apic_read(CO_APIC_ID));
403 static int __init visws_trap_init(void)
405 lithium_init();
406 cobalt_init();
408 return 1;
412 * IRQ controller / APIC support:
415 static DEFINE_SPINLOCK(cobalt_lock);
418 * Set the given Cobalt APIC Redirection Table entry to point
419 * to the given IDT vector/index.
421 static inline void co_apic_set(int entry, int irq)
423 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
424 co_apic_write(CO_APIC_HI(entry), 0);
428 * Cobalt (IO)-APIC functions to handle PCI devices.
430 static inline int co_apic_ide0_hack(void)
432 extern char visws_board_type;
433 extern char visws_board_rev;
435 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
436 return 5;
437 return CO_APIC_IDE0;
440 static int is_co_apic(unsigned int irq)
442 if (IS_CO_APIC(irq))
443 return CO_APIC(irq);
445 switch (irq) {
446 case 0: return CO_APIC_CPU;
447 case CO_IRQ_IDE0: return co_apic_ide0_hack();
448 case CO_IRQ_IDE1: return CO_APIC_IDE1;
449 default: return -1;
455 * This is the SGI Cobalt (IO-)APIC:
458 static void enable_cobalt_irq(unsigned int irq)
460 co_apic_set(is_co_apic(irq), irq);
463 static void disable_cobalt_irq(unsigned int irq)
465 int entry = is_co_apic(irq);
467 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
468 co_apic_read(CO_APIC_LO(entry));
472 * "irq" really just serves to identify the device. Here is where we
473 * map this to the Cobalt APIC entry where it's physically wired.
474 * This is called via request_irq -> setup_irq -> irq_desc->startup()
476 static unsigned int startup_cobalt_irq(unsigned int irq)
478 unsigned long flags;
479 struct irq_desc *desc = irq_to_desc(irq);
481 spin_lock_irqsave(&cobalt_lock, flags);
482 if ((desc->status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
483 desc->status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
484 enable_cobalt_irq(irq);
485 spin_unlock_irqrestore(&cobalt_lock, flags);
486 return 0;
489 static void ack_cobalt_irq(unsigned int irq)
491 unsigned long flags;
493 spin_lock_irqsave(&cobalt_lock, flags);
494 disable_cobalt_irq(irq);
495 apic_write(APIC_EOI, APIC_EIO_ACK);
496 spin_unlock_irqrestore(&cobalt_lock, flags);
499 static void end_cobalt_irq(unsigned int irq)
501 unsigned long flags;
502 struct irq_desc *desc = irq_to_desc(irq);
504 spin_lock_irqsave(&cobalt_lock, flags);
505 if (!(desc->status & (IRQ_DISABLED | IRQ_INPROGRESS)))
506 enable_cobalt_irq(irq);
507 spin_unlock_irqrestore(&cobalt_lock, flags);
510 static struct irq_chip cobalt_irq_type = {
511 .typename = "Cobalt-APIC",
512 .startup = startup_cobalt_irq,
513 .shutdown = disable_cobalt_irq,
514 .enable = enable_cobalt_irq,
515 .disable = disable_cobalt_irq,
516 .ack = ack_cobalt_irq,
517 .end = end_cobalt_irq,
522 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
523 * -- not the manner expected by the code in i8259.c.
525 * there is a 'master' physical interrupt source that gets sent to
526 * the CPU. But in the chipset there are various 'virtual' interrupts
527 * waiting to be handled. We represent this to Linux through a 'master'
528 * interrupt controller type, and through a special virtual interrupt-
529 * controller. Device drivers only see the virtual interrupt sources.
531 static unsigned int startup_piix4_master_irq(unsigned int irq)
533 init_8259A(0);
535 return startup_cobalt_irq(irq);
538 static void end_piix4_master_irq(unsigned int irq)
540 unsigned long flags;
542 spin_lock_irqsave(&cobalt_lock, flags);
543 enable_cobalt_irq(irq);
544 spin_unlock_irqrestore(&cobalt_lock, flags);
547 static struct irq_chip piix4_master_irq_type = {
548 .typename = "PIIX4-master",
549 .startup = startup_piix4_master_irq,
550 .ack = ack_cobalt_irq,
551 .end = end_piix4_master_irq,
555 static struct irq_chip piix4_virtual_irq_type = {
556 .typename = "PIIX4-virtual",
557 .shutdown = disable_8259A_irq,
558 .enable = enable_8259A_irq,
559 .disable = disable_8259A_irq,
564 * PIIX4-8259 master/virtual functions to handle interrupt requests
565 * from legacy devices: floppy, parallel, serial, rtc.
567 * None of these get Cobalt APIC entries, neither do they have IDT
568 * entries. These interrupts are purely virtual and distributed from
569 * the 'master' interrupt source: CO_IRQ_8259.
571 * When the 8259 interrupts its handler figures out which of these
572 * devices is interrupting and dispatches to its handler.
574 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
575 * enable_irq gets the right irq. This 'master' irq is never directly
576 * manipulated by any driver.
578 static irqreturn_t piix4_master_intr(int irq, void *dev_id)
580 int realirq;
581 struct irq_desc *desc;
582 unsigned long flags;
584 spin_lock_irqsave(&i8259A_lock, flags);
586 /* Find out what's interrupting in the PIIX4 master 8259 */
587 outb(0x0c, 0x20); /* OCW3 Poll command */
588 realirq = inb(0x20);
591 * Bit 7 == 0 means invalid/spurious
593 if (unlikely(!(realirq & 0x80)))
594 goto out_unlock;
596 realirq &= 7;
598 if (unlikely(realirq == 2)) {
599 outb(0x0c, 0xa0);
600 realirq = inb(0xa0);
602 if (unlikely(!(realirq & 0x80)))
603 goto out_unlock;
605 realirq = (realirq & 7) + 8;
608 /* mask and ack interrupt */
609 cached_irq_mask |= 1 << realirq;
610 if (unlikely(realirq > 7)) {
611 inb(0xa1);
612 outb(cached_slave_mask, 0xa1);
613 outb(0x60 + (realirq & 7), 0xa0);
614 outb(0x60 + 2, 0x20);
615 } else {
616 inb(0x21);
617 outb(cached_master_mask, 0x21);
618 outb(0x60 + realirq, 0x20);
621 spin_unlock_irqrestore(&i8259A_lock, flags);
623 desc = irq_to_desc(realirq);
626 * handle this 'virtual interrupt' as a Cobalt one now.
628 kstat_incr_irqs_this_cpu(realirq, desc);
630 if (likely(desc->action != NULL))
631 handle_IRQ_event(realirq, desc->action);
633 if (!(desc->status & IRQ_DISABLED))
634 enable_8259A_irq(realirq);
636 return IRQ_HANDLED;
638 out_unlock:
639 spin_unlock_irqrestore(&i8259A_lock, flags);
640 return IRQ_NONE;
643 static struct irqaction master_action = {
644 .handler = piix4_master_intr,
645 .name = "PIIX4-8259",
648 static struct irqaction cascade_action = {
649 .handler = no_action,
650 .name = "cascade",
654 void init_VISWS_APIC_irqs(void)
656 int i;
658 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
659 struct irq_desc *desc = irq_to_desc(i);
661 desc->status = IRQ_DISABLED;
662 desc->action = 0;
663 desc->depth = 1;
665 if (i == 0) {
666 desc->chip = &cobalt_irq_type;
668 else if (i == CO_IRQ_IDE0) {
669 desc->chip = &cobalt_irq_type;
671 else if (i == CO_IRQ_IDE1) {
672 desc->chip = &cobalt_irq_type;
674 else if (i == CO_IRQ_8259) {
675 desc->chip = &piix4_master_irq_type;
677 else if (i < CO_IRQ_APIC0) {
678 desc->chip = &piix4_virtual_irq_type;
680 else if (IS_CO_APIC(i)) {
681 desc->chip = &cobalt_irq_type;
685 setup_irq(CO_IRQ_8259, &master_action);
686 setup_irq(2, &cascade_action);