?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 2.6.31.6
[linux/fpc-iii.git] / arch / x86 / kvm / svm.c
blob4ac68999c7b074b2ab5a5dd5c614eca4aee27640
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "kvm_svm.h"
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29
30 #include <asm/desc.h>
31
32 #include <asm/virtext.h>
33
34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
35
36 MODULE_AUTHOR("Qumranet");
37 MODULE_LICENSE("GPL");
38
39 #define IOPM_ALLOC_ORDER 2
40 #define MSRPM_ALLOC_ORDER 1
41
42 #define SEG_TYPE_LDT 2
43 #define SEG_TYPE_BUSY_TSS16 3
44
45 #define SVM_FEATURE_NPT (1 << 0)
46 #define SVM_FEATURE_LBRV (1 << 1)
47 #define SVM_FEATURE_SVML (1 << 2)
48
49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
50
51 /* Turn on to get debugging output*/
52 /* #define NESTED_DEBUG */
53
54 #ifdef NESTED_DEBUG
55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
56 #else
57 #define nsvm_printk(fmt, args...) do {} while(0)
58 #endif
59
60 /* enable NPT for AMD64 and X86 with PAE */
61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
62 static bool npt_enabled = true;
63 #else
64 static bool npt_enabled = false;
65 #endif
66 static int npt = 1;
67
68 module_param(npt, int, S_IRUGO);
69
70 static int nested = 0;
71 module_param(nested, int, S_IRUGO);
72
73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
74
75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
76 static int nested_svm_vmexit(struct vcpu_svm *svm);
77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
78 void *arg2, void *opaque);
79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
80 bool has_error_code, u32 error_code);
81
82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
83 {
84 return container_of(vcpu, struct vcpu_svm, vcpu);
85 }
86
87 static inline bool is_nested(struct vcpu_svm *svm)
88 {
89 return svm->nested_vmcb;
90 }
91
92 static unsigned long iopm_base;
93
94 struct kvm_ldttss_desc {
95 u16 limit0;
96 u16 base0;
97 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
98 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
99 u32 base3;
100 u32 zero1;
101 } __attribute__((packed));
102
103 struct svm_cpu_data {
104 int cpu;
105
106 u64 asid_generation;
107 u32 max_asid;
108 u32 next_asid;
109 struct kvm_ldttss_desc *tss_desc;
110
111 struct page *save_area;
112 };
113
114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
115 static uint32_t svm_features;
116
117 struct svm_init_data {
118 int cpu;
119 int r;
120 };
121
122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
123
124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
125 #define MSRS_RANGE_SIZE 2048
126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
127
128 #define MAX_INST_SIZE 15
129
130 static inline u32 svm_has(u32 feat)
131 {
132 return svm_features & feat;
133 }
134
135 static inline void clgi(void)
136 {
137 asm volatile (__ex(SVM_CLGI));
138 }
139
140 static inline void stgi(void)
141 {
142 asm volatile (__ex(SVM_STGI));
143 }
144
145 static inline void invlpga(unsigned long addr, u32 asid)
146 {
147 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
148 }
149
150 static inline unsigned long kvm_read_cr2(void)
151 {
152 unsigned long cr2;
153
154 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
155 return cr2;
156 }
157
158 static inline void kvm_write_cr2(unsigned long val)
159 {
160 asm volatile ("mov %0, %%cr2" :: "r" (val));
161 }
162
163 static inline void force_new_asid(struct kvm_vcpu *vcpu)
164 {
165 to_svm(vcpu)->asid_generation--;
166 }
167
168 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
169 {
170 force_new_asid(vcpu);
171 }
172
173 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
174 {
175 if (!npt_enabled && !(efer & EFER_LMA))
176 efer &= ~EFER_LME;
177
178 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
179 vcpu->arch.shadow_efer = efer;
180 }
181
182 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
183 bool has_error_code, u32 error_code)
184 {
185 struct vcpu_svm *svm = to_svm(vcpu);
186
187 /* If we are within a nested VM we'd better #VMEXIT and let the
188 guest handle the exception */
189 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
190 return;
191
192 svm->vmcb->control.event_inj = nr
193 | SVM_EVTINJ_VALID
194 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
195 | SVM_EVTINJ_TYPE_EXEPT;
196 svm->vmcb->control.event_inj_err = error_code;
197 }
198
199 static int is_external_interrupt(u32 info)
200 {
201 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
202 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
203 }
204
205 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
206 {
207 struct vcpu_svm *svm = to_svm(vcpu);
208 u32 ret = 0;
209
210 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
211 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
212 return ret & mask;
213 }
214
215 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
216 {
217 struct vcpu_svm *svm = to_svm(vcpu);
218
219 if (mask == 0)
220 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
221 else
222 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
223
224 }
225
226 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
227 {
228 struct vcpu_svm *svm = to_svm(vcpu);
229
230 if (!svm->next_rip) {
231 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
232 EMULATE_DONE)
233 printk(KERN_DEBUG "%s: NOP\n", __func__);
234 return;
235 }
236 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
237 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
238 __func__, kvm_rip_read(vcpu), svm->next_rip);
239
240 kvm_rip_write(vcpu, svm->next_rip);
241 svm_set_interrupt_shadow(vcpu, 0);
242 }
243
244 static int has_svm(void)
245 {
246 const char *msg;
247
248 if (!cpu_has_svm(&msg)) {
249 printk(KERN_INFO "has_svm: %s\n", msg);
250 return 0;
251 }
252
253 return 1;
254 }
255
256 static void svm_hardware_disable(void *garbage)
257 {
258 cpu_svm_disable();
259 }
260
261 static void svm_hardware_enable(void *garbage)
262 {
263
264 struct svm_cpu_data *svm_data;
265 uint64_t efer;
266 struct desc_ptr gdt_descr;
267 struct desc_struct *gdt;
268 int me = raw_smp_processor_id();
269
270 if (!has_svm()) {
271 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
272 return;
273 }
274 svm_data = per_cpu(svm_data, me);
275
276 if (!svm_data) {
277 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
278 me);
279 return;
280 }
281
282 svm_data->asid_generation = 1;
283 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
284 svm_data->next_asid = svm_data->max_asid + 1;
285
286 asm volatile ("sgdt %0" : "=m"(gdt_descr));
287 gdt = (struct desc_struct *)gdt_descr.address;
288 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
289
290 rdmsrl(MSR_EFER, efer);
291 wrmsrl(MSR_EFER, efer | EFER_SVME);
292
293 wrmsrl(MSR_VM_HSAVE_PA,
294 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
295 }
296
297 static void svm_cpu_uninit(int cpu)
298 {
299 struct svm_cpu_data *svm_data
300 = per_cpu(svm_data, raw_smp_processor_id());
301
302 if (!svm_data)
303 return;
304
305 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
306 __free_page(svm_data->save_area);
307 kfree(svm_data);
308 }
309
310 static int svm_cpu_init(int cpu)
311 {
312 struct svm_cpu_data *svm_data;
313 int r;
314
315 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
316 if (!svm_data)
317 return -ENOMEM;
318 svm_data->cpu = cpu;
319 svm_data->save_area = alloc_page(GFP_KERNEL);
320 r = -ENOMEM;
321 if (!svm_data->save_area)
322 goto err_1;
323
324 per_cpu(svm_data, cpu) = svm_data;
325
326 return 0;
327
328 err_1:
329 kfree(svm_data);
330 return r;
331
332 }
333
334 static void set_msr_interception(u32 *msrpm, unsigned msr,
335 int read, int write)
336 {
337 int i;
338
339 for (i = 0; i < NUM_MSR_MAPS; i++) {
340 if (msr >= msrpm_ranges[i] &&
341 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
342 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
343 msrpm_ranges[i]) * 2;
344
345 u32 *base = msrpm + (msr_offset / 32);
346 u32 msr_shift = msr_offset % 32;
347 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
348 *base = (*base & ~(0x3 << msr_shift)) |
349 (mask << msr_shift);
350 return;
351 }
352 }
353 BUG();
354 }
355
356 static void svm_vcpu_init_msrpm(u32 *msrpm)
357 {
358 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
359
360 #ifdef CONFIG_X86_64
361 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
362 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
363 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
364 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
365 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
366 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
367 #endif
368 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
369 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
370 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
371 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
372 }
373
374 static void svm_enable_lbrv(struct vcpu_svm *svm)
375 {
376 u32 *msrpm = svm->msrpm;
377
378 svm->vmcb->control.lbr_ctl = 1;
379 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
380 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
381 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
382 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
383 }
384
385 static void svm_disable_lbrv(struct vcpu_svm *svm)
386 {
387 u32 *msrpm = svm->msrpm;
388
389 svm->vmcb->control.lbr_ctl = 0;
390 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
391 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
392 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
393 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
394 }
395
396 static __init int svm_hardware_setup(void)
397 {
398 int cpu;
399 struct page *iopm_pages;
400 void *iopm_va;
401 int r;
402
403 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
404
405 if (!iopm_pages)
406 return -ENOMEM;
407
408 iopm_va = page_address(iopm_pages);
409 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
410 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
411
412 if (boot_cpu_has(X86_FEATURE_NX))
413 kvm_enable_efer_bits(EFER_NX);
414
415 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
416 kvm_enable_efer_bits(EFER_FFXSR);
417
418 if (nested) {
419 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
420 kvm_enable_efer_bits(EFER_SVME);
421 }
422
423 for_each_online_cpu(cpu) {
424 r = svm_cpu_init(cpu);
425 if (r)
426 goto err;
427 }
428
429 svm_features = cpuid_edx(SVM_CPUID_FUNC);
430
431 if (!svm_has(SVM_FEATURE_NPT))
432 npt_enabled = false;
433
434 if (npt_enabled && !npt) {
435 printk(KERN_INFO "kvm: Nested Paging disabled\n");
436 npt_enabled = false;
437 }
438
439 if (npt_enabled) {
440 printk(KERN_INFO "kvm: Nested Paging enabled\n");
441 kvm_enable_tdp();
442 } else
443 kvm_disable_tdp();
444
445 return 0;
446
447 err:
448 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
449 iopm_base = 0;
450 return r;
451 }
452
453 static __exit void svm_hardware_unsetup(void)
454 {
455 int cpu;
456
457 for_each_online_cpu(cpu)
458 svm_cpu_uninit(cpu);
459
460 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
461 iopm_base = 0;
462 }
463
464 static void init_seg(struct vmcb_seg *seg)
465 {
466 seg->selector = 0;
467 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
468 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
469 seg->limit = 0xffff;
470 seg->base = 0;
471 }
472
473 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
474 {
475 seg->selector = 0;
476 seg->attrib = SVM_SELECTOR_P_MASK | type;
477 seg->limit = 0xffff;
478 seg->base = 0;
479 }
480
481 static void init_vmcb(struct vcpu_svm *svm)
482 {
483 struct vmcb_control_area *control = &svm->vmcb->control;
484 struct vmcb_save_area *save = &svm->vmcb->save;
485
486 control->intercept_cr_read = INTERCEPT_CR0_MASK |
487 INTERCEPT_CR3_MASK |
488 INTERCEPT_CR4_MASK;
489
490 control->intercept_cr_write = INTERCEPT_CR0_MASK |
491 INTERCEPT_CR3_MASK |
492 INTERCEPT_CR4_MASK |
493 INTERCEPT_CR8_MASK;
494
495 control->intercept_dr_read = INTERCEPT_DR0_MASK |
496 INTERCEPT_DR1_MASK |
497 INTERCEPT_DR2_MASK |
498 INTERCEPT_DR3_MASK;
499
500 control->intercept_dr_write = INTERCEPT_DR0_MASK |
501 INTERCEPT_DR1_MASK |
502 INTERCEPT_DR2_MASK |
503 INTERCEPT_DR3_MASK |
504 INTERCEPT_DR5_MASK |
505 INTERCEPT_DR7_MASK;
506
507 control->intercept_exceptions = (1 << PF_VECTOR) |
508 (1 << UD_VECTOR) |
509 (1 << MC_VECTOR);
510
511
512 control->intercept = (1ULL << INTERCEPT_INTR) |
513 (1ULL << INTERCEPT_NMI) |
514 (1ULL << INTERCEPT_SMI) |
515 (1ULL << INTERCEPT_CPUID) |
516 (1ULL << INTERCEPT_INVD) |
517 (1ULL << INTERCEPT_HLT) |
518 (1ULL << INTERCEPT_INVLPG) |
519 (1ULL << INTERCEPT_INVLPGA) |
520 (1ULL << INTERCEPT_IOIO_PROT) |
521 (1ULL << INTERCEPT_MSR_PROT) |
522 (1ULL << INTERCEPT_TASK_SWITCH) |
523 (1ULL << INTERCEPT_SHUTDOWN) |
524 (1ULL << INTERCEPT_VMRUN) |
525 (1ULL << INTERCEPT_VMMCALL) |
526 (1ULL << INTERCEPT_VMLOAD) |
527 (1ULL << INTERCEPT_VMSAVE) |
528 (1ULL << INTERCEPT_STGI) |
529 (1ULL << INTERCEPT_CLGI) |
530 (1ULL << INTERCEPT_SKINIT) |
531 (1ULL << INTERCEPT_WBINVD) |
532 (1ULL << INTERCEPT_MONITOR) |
533 (1ULL << INTERCEPT_MWAIT);
534
535 control->iopm_base_pa = iopm_base;
536 control->msrpm_base_pa = __pa(svm->msrpm);
537 control->tsc_offset = 0;
538 control->int_ctl = V_INTR_MASKING_MASK;
539
540 init_seg(&save->es);
541 init_seg(&save->ss);
542 init_seg(&save->ds);
543 init_seg(&save->fs);
544 init_seg(&save->gs);
545
546 save->cs.selector = 0xf000;
547 /* Executable/Readable Code Segment */
548 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
549 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
550 save->cs.limit = 0xffff;
551 /*
552 * cs.base should really be 0xffff0000, but vmx can't handle that, so
553 * be consistent with it.
554 *
555 * Replace when we have real mode working for vmx.
556 */
557 save->cs.base = 0xf0000;
558
559 save->gdtr.limit = 0xffff;
560 save->idtr.limit = 0xffff;
561
562 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
563 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
564
565 save->efer = EFER_SVME;
566 save->dr6 = 0xffff0ff0;
567 save->dr7 = 0x400;
568 save->rflags = 2;
569 save->rip = 0x0000fff0;
570 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
571
572 /*
573 * cr0 val on cpu init should be 0x60000010, we enable cpu
574 * cache by default. the orderly way is to enable cache in bios.
575 */
576 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
577 save->cr4 = X86_CR4_PAE;
578 /* rdx = ?? */
579
580 if (npt_enabled) {
581 /* Setup VMCB for Nested Paging */
582 control->nested_ctl = 1;
583 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
584 (1ULL << INTERCEPT_INVLPG));
585 control->intercept_exceptions &= ~(1 << PF_VECTOR);
586 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
587 INTERCEPT_CR3_MASK);
588 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
589 INTERCEPT_CR3_MASK);
590 save->g_pat = 0x0007040600070406ULL;
591 /* enable caching because the QEMU Bios doesn't enable it */
592 save->cr0 = X86_CR0_ET;
593 save->cr3 = 0;
594 save->cr4 = 0;
595 }
596 force_new_asid(&svm->vcpu);
597
598 svm->nested_vmcb = 0;
599 svm->vcpu.arch.hflags = HF_GIF_MASK;
600 }
601
602 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
603 {
604 struct vcpu_svm *svm = to_svm(vcpu);
605
606 init_vmcb(svm);
607
608 if (vcpu->vcpu_id != 0) {
609 kvm_rip_write(vcpu, 0);
610 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
611 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
612 }
613 vcpu->arch.regs_avail = ~0;
614 vcpu->arch.regs_dirty = ~0;
615
616 return 0;
617 }
618
619 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
620 {
621 struct vcpu_svm *svm;
622 struct page *page;
623 struct page *msrpm_pages;
624 struct page *hsave_page;
625 struct page *nested_msrpm_pages;
626 int err;
627
628 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
629 if (!svm) {
630 err = -ENOMEM;
631 goto out;
632 }
633
634 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
635 if (err)
636 goto free_svm;
637
638 page = alloc_page(GFP_KERNEL);
639 if (!page) {
640 err = -ENOMEM;
641 goto uninit;
642 }
643
644 err = -ENOMEM;
645 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
646 if (!msrpm_pages)
647 goto uninit;
648
649 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
650 if (!nested_msrpm_pages)
651 goto uninit;
652
653 svm->msrpm = page_address(msrpm_pages);
654 svm_vcpu_init_msrpm(svm->msrpm);
655
656 hsave_page = alloc_page(GFP_KERNEL);
657 if (!hsave_page)
658 goto uninit;
659 svm->hsave = page_address(hsave_page);
660
661 svm->nested_msrpm = page_address(nested_msrpm_pages);
662
663 svm->vmcb = page_address(page);
664 clear_page(svm->vmcb);
665 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
666 svm->asid_generation = 0;
667 init_vmcb(svm);
668
669 fx_init(&svm->vcpu);
670 svm->vcpu.fpu_active = 1;
671 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
672 if (svm->vcpu.vcpu_id == 0)
673 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
674
675 return &svm->vcpu;
676
677 uninit:
678 kvm_vcpu_uninit(&svm->vcpu);
679 free_svm:
680 kmem_cache_free(kvm_vcpu_cache, svm);
681 out:
682 return ERR_PTR(err);
683 }
684
685 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
686 {
687 struct vcpu_svm *svm = to_svm(vcpu);
688
689 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
690 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
691 __free_page(virt_to_page(svm->hsave));
692 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
693 kvm_vcpu_uninit(vcpu);
694 kmem_cache_free(kvm_vcpu_cache, svm);
695 }
696
697 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
698 {
699 struct vcpu_svm *svm = to_svm(vcpu);
700 int i;
701
702 if (unlikely(cpu != vcpu->cpu)) {
703 u64 tsc_this, delta;
704
705 /*
706 * Make sure that the guest sees a monotonically
707 * increasing TSC.
708 */
709 rdtscll(tsc_this);
710 delta = vcpu->arch.host_tsc - tsc_this;
711 svm->vmcb->control.tsc_offset += delta;
712 if (is_nested(svm))
713 svm->hsave->control.tsc_offset += delta;
714 vcpu->cpu = cpu;
715 kvm_migrate_timers(vcpu);
716 svm->asid_generation = 0;
717 }
718
719 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
720 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
721 }
722
723 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
724 {
725 struct vcpu_svm *svm = to_svm(vcpu);
726 int i;
727
728 ++vcpu->stat.host_state_reload;
729 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
730 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
731
732 rdtscll(vcpu->arch.host_tsc);
733 }
734
735 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
736 {
737 return to_svm(vcpu)->vmcb->save.rflags;
738 }
739
740 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
741 {
742 to_svm(vcpu)->vmcb->save.rflags = rflags;
743 }
744
745 static void svm_set_vintr(struct vcpu_svm *svm)
746 {
747 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
748 }
749
750 static void svm_clear_vintr(struct vcpu_svm *svm)
751 {
752 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
753 }
754
755 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
756 {
757 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
758
759 switch (seg) {
760 case VCPU_SREG_CS: return &save->cs;
761 case VCPU_SREG_DS: return &save->ds;
762 case VCPU_SREG_ES: return &save->es;
763 case VCPU_SREG_FS: return &save->fs;
764 case VCPU_SREG_GS: return &save->gs;
765 case VCPU_SREG_SS: return &save->ss;
766 case VCPU_SREG_TR: return &save->tr;
767 case VCPU_SREG_LDTR: return &save->ldtr;
768 }
769 BUG();
770 return NULL;
771 }
772
773 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
774 {
775 struct vmcb_seg *s = svm_seg(vcpu, seg);
776
777 return s->base;
778 }
779
780 static void svm_get_segment(struct kvm_vcpu *vcpu,
781 struct kvm_segment *var, int seg)
782 {
783 struct vmcb_seg *s = svm_seg(vcpu, seg);
784
785 var->base = s->base;
786 var->limit = s->limit;
787 var->selector = s->selector;
788 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
789 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
790 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
791 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
792 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
793 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
794 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
795 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
796
797 /* AMD's VMCB does not have an explicit unusable field, so emulate it
798 * for cross vendor migration purposes by "not present"
799 */
800 var->unusable = !var->present || (var->type == 0);
801
802 switch (seg) {
803 case VCPU_SREG_CS:
804 /*
805 * SVM always stores 0 for the 'G' bit in the CS selector in
806 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
807 * Intel's VMENTRY has a check on the 'G' bit.
808 */
809 var->g = s->limit > 0xfffff;
810 break;
811 case VCPU_SREG_TR:
812 /*
813 * Work around a bug where the busy flag in the tr selector
814 * isn't exposed
815 */
816 var->type |= 0x2;
817 break;
818 case VCPU_SREG_DS:
819 case VCPU_SREG_ES:
820 case VCPU_SREG_FS:
821 case VCPU_SREG_GS:
822 /*
823 * The accessed bit must always be set in the segment
824 * descriptor cache, although it can be cleared in the
825 * descriptor, the cached bit always remains at 1. Since
826 * Intel has a check on this, set it here to support
827 * cross-vendor migration.
828 */
829 if (!var->unusable)
830 var->type |= 0x1;
831 break;
832 case VCPU_SREG_SS:
833 /* On AMD CPUs sometimes the DB bit in the segment
834 * descriptor is left as 1, although the whole segment has
835 * been made unusable. Clear it here to pass an Intel VMX
836 * entry check when cross vendor migrating.
837 */
838 if (var->unusable)
839 var->db = 0;
840 break;
841 }
842 }
843
844 static int svm_get_cpl(struct kvm_vcpu *vcpu)
845 {
846 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
847
848 return save->cpl;
849 }
850
851 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
852 {
853 struct vcpu_svm *svm = to_svm(vcpu);
854
855 dt->limit = svm->vmcb->save.idtr.limit;
856 dt->base = svm->vmcb->save.idtr.base;
857 }
858
859 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
860 {
861 struct vcpu_svm *svm = to_svm(vcpu);
862
863 svm->vmcb->save.idtr.limit = dt->limit;
864 svm->vmcb->save.idtr.base = dt->base ;
865 }
866
867 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
868 {
869 struct vcpu_svm *svm = to_svm(vcpu);
870
871 dt->limit = svm->vmcb->save.gdtr.limit;
872 dt->base = svm->vmcb->save.gdtr.base;
873 }
874
875 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
876 {
877 struct vcpu_svm *svm = to_svm(vcpu);
878
879 svm->vmcb->save.gdtr.limit = dt->limit;
880 svm->vmcb->save.gdtr.base = dt->base ;
881 }
882
883 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
884 {
885 }
886
887 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
888 {
889 struct vcpu_svm *svm = to_svm(vcpu);
890
891 #ifdef CONFIG_X86_64
892 if (vcpu->arch.shadow_efer & EFER_LME) {
893 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
894 vcpu->arch.shadow_efer |= EFER_LMA;
895 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
896 }
897
898 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
899 vcpu->arch.shadow_efer &= ~EFER_LMA;
900 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
901 }
902 }
903 #endif
904 if (npt_enabled)
905 goto set;
906
907 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
908 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
909 vcpu->fpu_active = 1;
910 }
911
912 vcpu->arch.cr0 = cr0;
913 cr0 |= X86_CR0_PG | X86_CR0_WP;
914 if (!vcpu->fpu_active) {
915 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
916 cr0 |= X86_CR0_TS;
917 }
918 set:
919 /*
920 * re-enable caching here because the QEMU bios
921 * does not do it - this results in some delay at
922 * reboot
923 */
924 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
925 svm->vmcb->save.cr0 = cr0;
926 }
927
928 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
929 {
930 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
931 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
932
933 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
934 force_new_asid(vcpu);
935
936 vcpu->arch.cr4 = cr4;
937 if (!npt_enabled)
938 cr4 |= X86_CR4_PAE;
939 cr4 |= host_cr4_mce;
940 to_svm(vcpu)->vmcb->save.cr4 = cr4;
941 }
942
943 static void svm_set_segment(struct kvm_vcpu *vcpu,
944 struct kvm_segment *var, int seg)
945 {
946 struct vcpu_svm *svm = to_svm(vcpu);
947 struct vmcb_seg *s = svm_seg(vcpu, seg);
948
949 s->base = var->base;
950 s->limit = var->limit;
951 s->selector = var->selector;
952 if (var->unusable)
953 s->attrib = 0;
954 else {
955 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
956 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
957 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
958 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
959 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
960 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
961 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
962 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
963 }
964 if (seg == VCPU_SREG_CS)
965 svm->vmcb->save.cpl
966 = (svm->vmcb->save.cs.attrib
967 >> SVM_SELECTOR_DPL_SHIFT) & 3;
968
969 }
970
971 static void update_db_intercept(struct kvm_vcpu *vcpu)
972 {
973 struct vcpu_svm *svm = to_svm(vcpu);
974
975 svm->vmcb->control.intercept_exceptions &=
976 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
977
978 if (vcpu->arch.singlestep)
979 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
980
981 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
982 if (vcpu->guest_debug &
983 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
984 svm->vmcb->control.intercept_exceptions |=
985 1 << DB_VECTOR;
986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
987 svm->vmcb->control.intercept_exceptions |=
988 1 << BP_VECTOR;
989 } else
990 vcpu->guest_debug = 0;
991 }
992
993 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
994 {
995 int old_debug = vcpu->guest_debug;
996 struct vcpu_svm *svm = to_svm(vcpu);
997
998 vcpu->guest_debug = dbg->control;
999
1000 update_db_intercept(vcpu);
1001
1002 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1003 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1004 else
1005 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1006
1007 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1008 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1009 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1010 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1011
1012 return 0;
1013 }
1014
1015 static void load_host_msrs(struct kvm_vcpu *vcpu)
1016 {
1017 #ifdef CONFIG_X86_64
1018 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1019 #endif
1020 }
1021
1022 static void save_host_msrs(struct kvm_vcpu *vcpu)
1023 {
1024 #ifdef CONFIG_X86_64
1025 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1026 #endif
1027 }
1028
1029 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1030 {
1031 if (svm_data->next_asid > svm_data->max_asid) {
1032 ++svm_data->asid_generation;
1033 svm_data->next_asid = 1;
1034 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1035 }
1036
1037 svm->asid_generation = svm_data->asid_generation;
1038 svm->vmcb->control.asid = svm_data->next_asid++;
1039 }
1040
1041 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1042 {
1043 struct vcpu_svm *svm = to_svm(vcpu);
1044 unsigned long val;
1045
1046 switch (dr) {
1047 case 0 ... 3:
1048 val = vcpu->arch.db[dr];
1049 break;
1050 case 6:
1051 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1052 val = vcpu->arch.dr6;
1053 else
1054 val = svm->vmcb->save.dr6;
1055 break;
1056 case 7:
1057 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1058 val = vcpu->arch.dr7;
1059 else
1060 val = svm->vmcb->save.dr7;
1061 break;
1062 default:
1063 val = 0;
1064 }
1065
1066 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1067 return val;
1068 }
1069
1070 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1071 int *exception)
1072 {
1073 struct vcpu_svm *svm = to_svm(vcpu);
1074
1075 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1076
1077 *exception = 0;
1078
1079 switch (dr) {
1080 case 0 ... 3:
1081 vcpu->arch.db[dr] = value;
1082 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1083 vcpu->arch.eff_db[dr] = value;
1084 return;
1085 case 4 ... 5:
1086 if (vcpu->arch.cr4 & X86_CR4_DE)
1087 *exception = UD_VECTOR;
1088 return;
1089 case 6:
1090 if (value & 0xffffffff00000000ULL) {
1091 *exception = GP_VECTOR;
1092 return;
1093 }
1094 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1095 return;
1096 case 7:
1097 if (value & 0xffffffff00000000ULL) {
1098 *exception = GP_VECTOR;
1099 return;
1100 }
1101 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1102 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1103 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1104 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1105 }
1106 return;
1107 default:
1108 /* FIXME: Possible case? */
1109 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1110 __func__, dr);
1111 *exception = UD_VECTOR;
1112 return;
1113 }
1114 }
1115
1116 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1117 {
1118 u64 fault_address;
1119 u32 error_code;
1120
1121 fault_address = svm->vmcb->control.exit_info_2;
1122 error_code = svm->vmcb->control.exit_info_1;
1123
1124 if (!npt_enabled)
1125 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1126 (u32)fault_address, (u32)(fault_address >> 32),
1127 handler);
1128 else
1129 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1130 (u32)fault_address, (u32)(fault_address >> 32),
1131 handler);
1132 /*
1133 * FIXME: Tis shouldn't be necessary here, but there is a flush
1134 * missing in the MMU code. Until we find this bug, flush the
1135 * complete TLB here on an NPF
1136 */
1137 if (npt_enabled)
1138 svm_flush_tlb(&svm->vcpu);
1139 else {
1140 if (kvm_event_needs_reinjection(&svm->vcpu))
1141 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1142 }
1143 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1144 }
1145
1146 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1147 {
1148 if (!(svm->vcpu.guest_debug &
1149 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1150 !svm->vcpu.arch.singlestep) {
1151 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1152 return 1;
1153 }
1154
1155 if (svm->vcpu.arch.singlestep) {
1156 svm->vcpu.arch.singlestep = false;
1157 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1158 svm->vmcb->save.rflags &=
1159 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1160 update_db_intercept(&svm->vcpu);
1161 }
1162
1163 if (svm->vcpu.guest_debug &
1164 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1165 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1166 kvm_run->debug.arch.pc =
1167 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1168 kvm_run->debug.arch.exception = DB_VECTOR;
1169 return 0;
1170 }
1171
1172 return 1;
1173 }
1174
1175 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1176 {
1177 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1178 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1179 kvm_run->debug.arch.exception = BP_VECTOR;
1180 return 0;
1181 }
1182
1183 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1184 {
1185 int er;
1186
1187 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1188 if (er != EMULATE_DONE)
1189 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1190 return 1;
1191 }
1192
1193 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1194 {
1195 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1196 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1197 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1198 svm->vcpu.fpu_active = 1;
1199
1200 return 1;
1201 }
1202
1203 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1204 {
1205 /*
1206 * On an #MC intercept the MCE handler is not called automatically in
1207 * the host. So do it by hand here.
1208 */
1209 asm volatile (
1210 "int $0x12\n");
1211 /* not sure if we ever come back to this point */
1212
1213 return 1;
1214 }
1215
1216 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1217 {
1218 /*
1219 * VMCB is undefined after a SHUTDOWN intercept
1220 * so reinitialize it.
1221 */
1222 clear_page(svm->vmcb);
1223 init_vmcb(svm);
1224
1225 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1226 return 0;
1227 }
1228
1229 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1230 {
1231 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1232 int size, in, string;
1233 unsigned port;
1234
1235 ++svm->vcpu.stat.io_exits;
1236
1237 svm->next_rip = svm->vmcb->control.exit_info_2;
1238
1239 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1240
1241 if (string) {
1242 if (emulate_instruction(&svm->vcpu,
1243 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1244 return 0;
1245 return 1;
1246 }
1247
1248 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1249 port = io_info >> 16;
1250 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1251
1252 skip_emulated_instruction(&svm->vcpu);
1253 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1254 }
1255
1256 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1257 {
1258 KVMTRACE_0D(NMI, &svm->vcpu, handler);
1259 return 1;
1260 }
1261
1262 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1263 {
1264 ++svm->vcpu.stat.irq_exits;
1265 KVMTRACE_0D(INTR, &svm->vcpu, handler);
1266 return 1;
1267 }
1268
1269 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1270 {
1271 return 1;
1272 }
1273
1274 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1275 {
1276 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1277 skip_emulated_instruction(&svm->vcpu);
1278 return kvm_emulate_halt(&svm->vcpu);
1279 }
1280
1281 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1282 {
1283 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1284 skip_emulated_instruction(&svm->vcpu);
1285 kvm_emulate_hypercall(&svm->vcpu);
1286 return 1;
1287 }
1288
1289 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1290 {
1291 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1292 || !is_paging(&svm->vcpu)) {
1293 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1294 return 1;
1295 }
1296
1297 if (svm->vmcb->save.cpl) {
1298 kvm_inject_gp(&svm->vcpu, 0);
1299 return 1;
1300 }
1301
1302 return 0;
1303 }
1304
1305 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1306 bool has_error_code, u32 error_code)
1307 {
1308 if (is_nested(svm)) {
1309 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1310 svm->vmcb->control.exit_code_hi = 0;
1311 svm->vmcb->control.exit_info_1 = error_code;
1312 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1313 if (nested_svm_exit_handled(svm, false)) {
1314 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1315
1316 nested_svm_vmexit(svm);
1317 return 1;
1318 }
1319 }
1320
1321 return 0;
1322 }
1323
1324 static inline int nested_svm_intr(struct vcpu_svm *svm)
1325 {
1326 if (is_nested(svm)) {
1327 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1328 return 0;
1329
1330 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1331 return 0;
1332
1333 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1334
1335 if (nested_svm_exit_handled(svm, false)) {
1336 nsvm_printk("VMexit -> INTR\n");
1337 nested_svm_vmexit(svm);
1338 return 1;
1339 }
1340 }
1341
1342 return 0;
1343 }
1344
1345 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1346 {
1347 struct page *page;
1348
1349 down_read(&current->mm->mmap_sem);
1350 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1351 up_read(&current->mm->mmap_sem);
1352
1353 if (is_error_page(page)) {
1354 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1355 __func__, gpa);
1356 kvm_release_page_clean(page);
1357 kvm_inject_gp(&svm->vcpu, 0);
1358 return NULL;
1359 }
1360 return page;
1361 }
1362
1363 static int nested_svm_do(struct vcpu_svm *svm,
1364 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1365 int (*handler)(struct vcpu_svm *svm,
1366 void *arg1,
1367 void *arg2,
1368 void *opaque))
1369 {
1370 struct page *arg1_page;
1371 struct page *arg2_page = NULL;
1372 void *arg1;
1373 void *arg2 = NULL;
1374 int retval;
1375
1376 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1377 if(arg1_page == NULL)
1378 return 1;
1379
1380 if (arg2_gpa) {
1381 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1382 if(arg2_page == NULL) {
1383 kvm_release_page_clean(arg1_page);
1384 return 1;
1385 }
1386 }
1387
1388 arg1 = kmap_atomic(arg1_page, KM_USER0);
1389 if (arg2_gpa)
1390 arg2 = kmap_atomic(arg2_page, KM_USER1);
1391
1392 retval = handler(svm, arg1, arg2, opaque);
1393
1394 kunmap_atomic(arg1, KM_USER0);
1395 if (arg2_gpa)
1396 kunmap_atomic(arg2, KM_USER1);
1397
1398 kvm_release_page_dirty(arg1_page);
1399 if (arg2_gpa)
1400 kvm_release_page_dirty(arg2_page);
1401
1402 return retval;
1403 }
1404
1405 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1406 void *arg1,
1407 void *arg2,
1408 void *opaque)
1409 {
1410 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1411 bool kvm_overrides = *(bool *)opaque;
1412 u32 exit_code = svm->vmcb->control.exit_code;
1413
1414 if (kvm_overrides) {
1415 switch (exit_code) {
1416 case SVM_EXIT_INTR:
1417 case SVM_EXIT_NMI:
1418 return 0;
1419 /* For now we are always handling NPFs when using them */
1420 case SVM_EXIT_NPF:
1421 if (npt_enabled)
1422 return 0;
1423 break;
1424 /* When we're shadowing, trap PFs */
1425 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1426 if (!npt_enabled)
1427 return 0;
1428 break;
1429 default:
1430 break;
1431 }
1432 }
1433
1434 switch (exit_code) {
1435 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1436 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1437 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1438 return 1;
1439 break;
1440 }
1441 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1442 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1443 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1444 return 1;
1445 break;
1446 }
1447 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1448 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1449 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1450 return 1;
1451 break;
1452 }
1453 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1454 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1455 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1456 return 1;
1457 break;
1458 }
1459 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1460 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1461 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1462 return 1;
1463 break;
1464 }
1465 default: {
1466 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1467 nsvm_printk("exit code: 0x%x\n", exit_code);
1468 if (nested_vmcb->control.intercept & exit_bits)
1469 return 1;
1470 }
1471 }
1472
1473 return 0;
1474 }
1475
1476 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1477 void *arg1, void *arg2,
1478 void *opaque)
1479 {
1480 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1481 u8 *msrpm = (u8 *)arg2;
1482 u32 t0, t1;
1483 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1484 u32 param = svm->vmcb->control.exit_info_1 & 1;
1485
1486 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1487 return 0;
1488
1489 switch(msr) {
1490 case 0 ... 0x1fff:
1491 t0 = (msr * 2) % 8;
1492 t1 = msr / 8;
1493 break;
1494 case 0xc0000000 ... 0xc0001fff:
1495 t0 = (8192 + msr - 0xc0000000) * 2;
1496 t1 = (t0 / 8);
1497 t0 %= 8;
1498 break;
1499 case 0xc0010000 ... 0xc0011fff:
1500 t0 = (16384 + msr - 0xc0010000) * 2;
1501 t1 = (t0 / 8);
1502 t0 %= 8;
1503 break;
1504 default:
1505 return 1;
1506 break;
1507 }
1508 if (msrpm[t1] & ((1 << param) << t0))
1509 return 1;
1510
1511 return 0;
1512 }
1513
1514 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1515 {
1516 bool k = kvm_override;
1517
1518 switch (svm->vmcb->control.exit_code) {
1519 case SVM_EXIT_MSR:
1520 return nested_svm_do(svm, svm->nested_vmcb,
1521 svm->nested_vmcb_msrpm, NULL,
1522 nested_svm_exit_handled_msr);
1523 default: break;
1524 }
1525
1526 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1527 nested_svm_exit_handled_real);
1528 }
1529
1530 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1531 void *arg2, void *opaque)
1532 {
1533 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1534 struct vmcb *hsave = svm->hsave;
1535 u64 nested_save[] = { nested_vmcb->save.cr0,
1536 nested_vmcb->save.cr3,
1537 nested_vmcb->save.cr4,
1538 nested_vmcb->save.efer,
1539 nested_vmcb->control.intercept_cr_read,
1540 nested_vmcb->control.intercept_cr_write,
1541 nested_vmcb->control.intercept_dr_read,
1542 nested_vmcb->control.intercept_dr_write,
1543 nested_vmcb->control.intercept_exceptions,
1544 nested_vmcb->control.intercept,
1545 nested_vmcb->control.msrpm_base_pa,
1546 nested_vmcb->control.iopm_base_pa,
1547 nested_vmcb->control.tsc_offset };
1548
1549 /* Give the current vmcb to the guest */
1550 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1551 nested_vmcb->save.cr0 = nested_save[0];
1552 if (!npt_enabled)
1553 nested_vmcb->save.cr3 = nested_save[1];
1554 nested_vmcb->save.cr4 = nested_save[2];
1555 nested_vmcb->save.efer = nested_save[3];
1556 nested_vmcb->control.intercept_cr_read = nested_save[4];
1557 nested_vmcb->control.intercept_cr_write = nested_save[5];
1558 nested_vmcb->control.intercept_dr_read = nested_save[6];
1559 nested_vmcb->control.intercept_dr_write = nested_save[7];
1560 nested_vmcb->control.intercept_exceptions = nested_save[8];
1561 nested_vmcb->control.intercept = nested_save[9];
1562 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1563 nested_vmcb->control.iopm_base_pa = nested_save[11];
1564 nested_vmcb->control.tsc_offset = nested_save[12];
1565
1566 /* We always set V_INTR_MASKING and remember the old value in hflags */
1567 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1568 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1569
1570 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1571 (nested_vmcb->control.int_vector)) {
1572 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1573 nested_vmcb->control.int_vector);
1574 }
1575
1576 /* Restore the original control entries */
1577 svm->vmcb->control = hsave->control;
1578
1579 /* Kill any pending exceptions */
1580 if (svm->vcpu.arch.exception.pending == true)
1581 nsvm_printk("WARNING: Pending Exception\n");
1582 svm->vcpu.arch.exception.pending = false;
1583
1584 /* Restore selected save entries */
1585 svm->vmcb->save.es = hsave->save.es;
1586 svm->vmcb->save.cs = hsave->save.cs;
1587 svm->vmcb->save.ss = hsave->save.ss;
1588 svm->vmcb->save.ds = hsave->save.ds;
1589 svm->vmcb->save.gdtr = hsave->save.gdtr;
1590 svm->vmcb->save.idtr = hsave->save.idtr;
1591 svm->vmcb->save.rflags = hsave->save.rflags;
1592 svm_set_efer(&svm->vcpu, hsave->save.efer);
1593 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1594 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1595 if (npt_enabled) {
1596 svm->vmcb->save.cr3 = hsave->save.cr3;
1597 svm->vcpu.arch.cr3 = hsave->save.cr3;
1598 } else {
1599 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1600 }
1601 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1602 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1603 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1604 svm->vmcb->save.dr7 = 0;
1605 svm->vmcb->save.cpl = 0;
1606 svm->vmcb->control.exit_int_info = 0;
1607
1608 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1609 /* Exit nested SVM mode */
1610 svm->nested_vmcb = 0;
1611
1612 return 0;
1613 }
1614
1615 static int nested_svm_vmexit(struct vcpu_svm *svm)
1616 {
1617 nsvm_printk("VMexit\n");
1618 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1619 NULL, nested_svm_vmexit_real))
1620 return 1;
1621
1622 kvm_mmu_reset_context(&svm->vcpu);
1623 kvm_mmu_load(&svm->vcpu);
1624
1625 return 0;
1626 }
1627
1628 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1629 void *arg2, void *opaque)
1630 {
1631 int i;
1632 u32 *nested_msrpm = (u32*)arg1;
1633 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1634 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1635 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1636
1637 return 0;
1638 }
1639
1640 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1641 void *arg2, void *opaque)
1642 {
1643 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1644 struct vmcb *hsave = svm->hsave;
1645
1646 /* nested_vmcb is our indicator if nested SVM is activated */
1647 svm->nested_vmcb = svm->vmcb->save.rax;
1648
1649 /* Clear internal status */
1650 svm->vcpu.arch.exception.pending = false;
1651
1652 /* Save the old vmcb, so we don't need to pick what we save, but
1653 can restore everything when a VMEXIT occurs */
1654 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1655 /* We need to remember the original CR3 in the SPT case */
1656 if (!npt_enabled)
1657 hsave->save.cr3 = svm->vcpu.arch.cr3;
1658 hsave->save.cr4 = svm->vcpu.arch.cr4;
1659 hsave->save.rip = svm->next_rip;
1660
1661 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1662 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1663 else
1664 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1665
1666 /* Load the nested guest state */
1667 svm->vmcb->save.es = nested_vmcb->save.es;
1668 svm->vmcb->save.cs = nested_vmcb->save.cs;
1669 svm->vmcb->save.ss = nested_vmcb->save.ss;
1670 svm->vmcb->save.ds = nested_vmcb->save.ds;
1671 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1672 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1673 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1674 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1675 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1676 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1677 if (npt_enabled) {
1678 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1679 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1680 } else {
1681 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1682 kvm_mmu_reset_context(&svm->vcpu);
1683 }
1684 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1685 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1686 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1687 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1688 /* In case we don't even reach vcpu_run, the fields are not updated */
1689 svm->vmcb->save.rax = nested_vmcb->save.rax;
1690 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1691 svm->vmcb->save.rip = nested_vmcb->save.rip;
1692 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1693 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1694 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1695
1696 /* We don't want a nested guest to be more powerful than the guest,
1697 so all intercepts are ORed */
1698 svm->vmcb->control.intercept_cr_read |=
1699 nested_vmcb->control.intercept_cr_read;
1700 svm->vmcb->control.intercept_cr_write |=
1701 nested_vmcb->control.intercept_cr_write;
1702 svm->vmcb->control.intercept_dr_read |=
1703 nested_vmcb->control.intercept_dr_read;
1704 svm->vmcb->control.intercept_dr_write |=
1705 nested_vmcb->control.intercept_dr_write;
1706 svm->vmcb->control.intercept_exceptions |=
1707 nested_vmcb->control.intercept_exceptions;
1708
1709 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1710
1711 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1712
1713 force_new_asid(&svm->vcpu);
1714 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1715 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1716 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1717 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1718 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1719 nested_vmcb->control.int_ctl);
1720 }
1721 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1722 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1723 else
1724 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1725
1726 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1727 nested_vmcb->control.exit_int_info,
1728 nested_vmcb->control.int_state);
1729
1730 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1731 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1732 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1733 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1734 nsvm_printk("Injecting Event: 0x%x\n",
1735 nested_vmcb->control.event_inj);
1736 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1737 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1738
1739 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1740
1741 return 0;
1742 }
1743
1744 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1745 {
1746 to_vmcb->save.fs = from_vmcb->save.fs;
1747 to_vmcb->save.gs = from_vmcb->save.gs;
1748 to_vmcb->save.tr = from_vmcb->save.tr;
1749 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1750 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1751 to_vmcb->save.star = from_vmcb->save.star;
1752 to_vmcb->save.lstar = from_vmcb->save.lstar;
1753 to_vmcb->save.cstar = from_vmcb->save.cstar;
1754 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1755 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1756 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1757 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1758
1759 return 1;
1760 }
1761
1762 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1763 void *arg2, void *opaque)
1764 {
1765 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1766 }
1767
1768 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1769 void *arg2, void *opaque)
1770 {
1771 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1772 }
1773
1774 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1775 {
1776 if (nested_svm_check_permissions(svm))
1777 return 1;
1778
1779 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1780 skip_emulated_instruction(&svm->vcpu);
1781
1782 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1783
1784 return 1;
1785 }
1786
1787 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1788 {
1789 if (nested_svm_check_permissions(svm))
1790 return 1;
1791
1792 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1793 skip_emulated_instruction(&svm->vcpu);
1794
1795 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1796
1797 return 1;
1798 }
1799
1800 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1801 {
1802 nsvm_printk("VMrun\n");
1803 if (nested_svm_check_permissions(svm))
1804 return 1;
1805
1806 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1807 skip_emulated_instruction(&svm->vcpu);
1808
1809 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1810 NULL, nested_svm_vmrun))
1811 return 1;
1812
1813 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1814 NULL, nested_svm_vmrun_msrpm))
1815 return 1;
1816
1817 return 1;
1818 }
1819
1820 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1821 {
1822 if (nested_svm_check_permissions(svm))
1823 return 1;
1824
1825 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1826 skip_emulated_instruction(&svm->vcpu);
1827
1828 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1829
1830 return 1;
1831 }
1832
1833 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1834 {
1835 if (nested_svm_check_permissions(svm))
1836 return 1;
1837
1838 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1839 skip_emulated_instruction(&svm->vcpu);
1840
1841 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1842
1843 /* After a CLGI no interrupts should come */
1844 svm_clear_vintr(svm);
1845 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1846
1847 return 1;
1848 }
1849
1850 static int invalid_op_interception(struct vcpu_svm *svm,
1851 struct kvm_run *kvm_run)
1852 {
1853 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1854 return 1;
1855 }
1856
1857 static int task_switch_interception(struct vcpu_svm *svm,
1858 struct kvm_run *kvm_run)
1859 {
1860 u16 tss_selector;
1861 int reason;
1862 int int_type = svm->vmcb->control.exit_int_info &
1863 SVM_EXITINTINFO_TYPE_MASK;
1864 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1865 uint32_t type =
1866 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1867 uint32_t idt_v =
1868 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1869
1870 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1871
1872 if (svm->vmcb->control.exit_info_2 &
1873 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1874 reason = TASK_SWITCH_IRET;
1875 else if (svm->vmcb->control.exit_info_2 &
1876 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1877 reason = TASK_SWITCH_JMP;
1878 else if (idt_v)
1879 reason = TASK_SWITCH_GATE;
1880 else
1881 reason = TASK_SWITCH_CALL;
1882
1883 if (reason == TASK_SWITCH_GATE) {
1884 switch (type) {
1885 case SVM_EXITINTINFO_TYPE_NMI:
1886 svm->vcpu.arch.nmi_injected = false;
1887 break;
1888 case SVM_EXITINTINFO_TYPE_EXEPT:
1889 kvm_clear_exception_queue(&svm->vcpu);
1890 break;
1891 case SVM_EXITINTINFO_TYPE_INTR:
1892 kvm_clear_interrupt_queue(&svm->vcpu);
1893 break;
1894 default:
1895 break;
1896 }
1897 }
1898
1899 if (reason != TASK_SWITCH_GATE ||
1900 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1901 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1902 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
1903 skip_emulated_instruction(&svm->vcpu);
1904
1905 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1906 }
1907
1908 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1909 {
1910 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1911 kvm_emulate_cpuid(&svm->vcpu);
1912 return 1;
1913 }
1914
1915 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1916 {
1917 ++svm->vcpu.stat.nmi_window_exits;
1918 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
1919 svm->vcpu.arch.hflags |= HF_IRET_MASK;
1920 return 1;
1921 }
1922
1923 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1924 {
1925 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1926 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1927 return 1;
1928 }
1929
1930 static int emulate_on_interception(struct vcpu_svm *svm,
1931 struct kvm_run *kvm_run)
1932 {
1933 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1934 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1935 return 1;
1936 }
1937
1938 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1939 {
1940 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1941 /* instruction emulation calls kvm_set_cr8() */
1942 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1943 if (irqchip_in_kernel(svm->vcpu.kvm)) {
1944 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1945 return 1;
1946 }
1947 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1948 return 1;
1949 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1950 return 0;
1951 }
1952
1953 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1954 {
1955 struct vcpu_svm *svm = to_svm(vcpu);
1956
1957 switch (ecx) {
1958 case MSR_IA32_TIME_STAMP_COUNTER: {
1959 u64 tsc_offset;
1960
1961 if (is_nested(svm))
1962 tsc_offset = svm->hsave->control.tsc_offset;
1963 else
1964 tsc_offset = svm->vmcb->control.tsc_offset;
1965
1966 *data = tsc_offset + native_read_tsc();
1967 break;
1968 }
1969 case MSR_K6_STAR:
1970 *data = svm->vmcb->save.star;
1971 break;
1972 #ifdef CONFIG_X86_64
1973 case MSR_LSTAR:
1974 *data = svm->vmcb->save.lstar;
1975 break;
1976 case MSR_CSTAR:
1977 *data = svm->vmcb->save.cstar;
1978 break;
1979 case MSR_KERNEL_GS_BASE:
1980 *data = svm->vmcb->save.kernel_gs_base;
1981 break;
1982 case MSR_SYSCALL_MASK:
1983 *data = svm->vmcb->save.sfmask;
1984 break;
1985 #endif
1986 case MSR_IA32_SYSENTER_CS:
1987 *data = svm->vmcb->save.sysenter_cs;
1988 break;
1989 case MSR_IA32_SYSENTER_EIP:
1990 *data = svm->vmcb->save.sysenter_eip;
1991 break;
1992 case MSR_IA32_SYSENTER_ESP:
1993 *data = svm->vmcb->save.sysenter_esp;
1994 break;
1995 /* Nobody will change the following 5 values in the VMCB so
1996 we can safely return them on rdmsr. They will always be 0
1997 until LBRV is implemented. */
1998 case MSR_IA32_DEBUGCTLMSR:
1999 *data = svm->vmcb->save.dbgctl;
2000 break;
2001 case MSR_IA32_LASTBRANCHFROMIP:
2002 *data = svm->vmcb->save.br_from;
2003 break;
2004 case MSR_IA32_LASTBRANCHTOIP:
2005 *data = svm->vmcb->save.br_to;
2006 break;
2007 case MSR_IA32_LASTINTFROMIP:
2008 *data = svm->vmcb->save.last_excp_from;
2009 break;
2010 case MSR_IA32_LASTINTTOIP:
2011 *data = svm->vmcb->save.last_excp_to;
2012 break;
2013 case MSR_VM_HSAVE_PA:
2014 *data = svm->hsave_msr;
2015 break;
2016 case MSR_VM_CR:
2017 *data = 0;
2018 break;
2019 case MSR_IA32_UCODE_REV:
2020 *data = 0x01000065;
2021 break;
2022 default:
2023 return kvm_get_msr_common(vcpu, ecx, data);
2024 }
2025 return 0;
2026 }
2027
2028 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2029 {
2030 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2031 u64 data;
2032
2033 if (svm_get_msr(&svm->vcpu, ecx, &data))
2034 kvm_inject_gp(&svm->vcpu, 0);
2035 else {
2036 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
2037 (u32)(data >> 32), handler);
2038
2039 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2040 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2041 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2042 skip_emulated_instruction(&svm->vcpu);
2043 }
2044 return 1;
2045 }
2046
2047 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2048 {
2049 struct vcpu_svm *svm = to_svm(vcpu);
2050
2051 switch (ecx) {
2052 case MSR_IA32_TIME_STAMP_COUNTER: {
2053 u64 tsc_offset = data - native_read_tsc();
2054 u64 g_tsc_offset = 0;
2055
2056 if (is_nested(svm)) {
2057 g_tsc_offset = svm->vmcb->control.tsc_offset -
2058 svm->hsave->control.tsc_offset;
2059 svm->hsave->control.tsc_offset = tsc_offset;
2060 }
2061
2062 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2063
2064 break;
2065 }
2066 case MSR_K6_STAR:
2067 svm->vmcb->save.star = data;
2068 break;
2069 #ifdef CONFIG_X86_64
2070 case MSR_LSTAR:
2071 svm->vmcb->save.lstar = data;
2072 break;
2073 case MSR_CSTAR:
2074 svm->vmcb->save.cstar = data;
2075 break;
2076 case MSR_KERNEL_GS_BASE:
2077 svm->vmcb->save.kernel_gs_base = data;
2078 break;
2079 case MSR_SYSCALL_MASK:
2080 svm->vmcb->save.sfmask = data;
2081 break;
2082 #endif
2083 case MSR_IA32_SYSENTER_CS:
2084 svm->vmcb->save.sysenter_cs = data;
2085 break;
2086 case MSR_IA32_SYSENTER_EIP:
2087 svm->vmcb->save.sysenter_eip = data;
2088 break;
2089 case MSR_IA32_SYSENTER_ESP:
2090 svm->vmcb->save.sysenter_esp = data;
2091 break;
2092 case MSR_IA32_DEBUGCTLMSR:
2093 if (!svm_has(SVM_FEATURE_LBRV)) {
2094 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2095 __func__, data);
2096 break;
2097 }
2098 if (data & DEBUGCTL_RESERVED_BITS)
2099 return 1;
2100
2101 svm->vmcb->save.dbgctl = data;
2102 if (data & (1ULL<<0))
2103 svm_enable_lbrv(svm);
2104 else
2105 svm_disable_lbrv(svm);
2106 break;
2107 case MSR_K7_EVNTSEL0:
2108 case MSR_K7_EVNTSEL1:
2109 case MSR_K7_EVNTSEL2:
2110 case MSR_K7_EVNTSEL3:
2111 case MSR_K7_PERFCTR0:
2112 case MSR_K7_PERFCTR1:
2113 case MSR_K7_PERFCTR2:
2114 case MSR_K7_PERFCTR3:
2115 /*
2116 * Just discard all writes to the performance counters; this
2117 * should keep both older linux and windows 64-bit guests
2118 * happy
2119 */
2120 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2121
2122 break;
2123 case MSR_VM_HSAVE_PA:
2124 svm->hsave_msr = data;
2125 break;
2126 default:
2127 return kvm_set_msr_common(vcpu, ecx, data);
2128 }
2129 return 0;
2130 }
2131
2132 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2133 {
2134 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2135 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2136 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2137
2138 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2139 handler);
2140
2141 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2142 if (svm_set_msr(&svm->vcpu, ecx, data))
2143 kvm_inject_gp(&svm->vcpu, 0);
2144 else
2145 skip_emulated_instruction(&svm->vcpu);
2146 return 1;
2147 }
2148
2149 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2150 {
2151 if (svm->vmcb->control.exit_info_1)
2152 return wrmsr_interception(svm, kvm_run);
2153 else
2154 return rdmsr_interception(svm, kvm_run);
2155 }
2156
2157 static int interrupt_window_interception(struct vcpu_svm *svm,
2158 struct kvm_run *kvm_run)
2159 {
2160 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2161
2162 svm_clear_vintr(svm);
2163 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2164 /*
2165 * If the user space waits to inject interrupts, exit as soon as
2166 * possible
2167 */
2168 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2169 kvm_run->request_interrupt_window &&
2170 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2171 ++svm->vcpu.stat.irq_window_exits;
2172 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2173 return 0;
2174 }
2175
2176 return 1;
2177 }
2178
2179 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2180 struct kvm_run *kvm_run) = {
2181 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2182 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2183 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2184 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2185 /* for now: */
2186 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2187 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2188 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2189 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2190 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2191 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2192 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2193 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2194 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2195 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2196 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2197 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2198 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2199 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2200 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2201 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2202 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2203 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2204 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2205 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2206 [SVM_EXIT_INTR] = intr_interception,
2207 [SVM_EXIT_NMI] = nmi_interception,
2208 [SVM_EXIT_SMI] = nop_on_interception,
2209 [SVM_EXIT_INIT] = nop_on_interception,
2210 [SVM_EXIT_VINTR] = interrupt_window_interception,
2211 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2212 [SVM_EXIT_CPUID] = cpuid_interception,
2213 [SVM_EXIT_IRET] = iret_interception,
2214 [SVM_EXIT_INVD] = emulate_on_interception,
2215 [SVM_EXIT_HLT] = halt_interception,
2216 [SVM_EXIT_INVLPG] = invlpg_interception,
2217 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2218 [SVM_EXIT_IOIO] = io_interception,
2219 [SVM_EXIT_MSR] = msr_interception,
2220 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2221 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2222 [SVM_EXIT_VMRUN] = vmrun_interception,
2223 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2224 [SVM_EXIT_VMLOAD] = vmload_interception,
2225 [SVM_EXIT_VMSAVE] = vmsave_interception,
2226 [SVM_EXIT_STGI] = stgi_interception,
2227 [SVM_EXIT_CLGI] = clgi_interception,
2228 [SVM_EXIT_SKINIT] = invalid_op_interception,
2229 [SVM_EXIT_WBINVD] = emulate_on_interception,
2230 [SVM_EXIT_MONITOR] = invalid_op_interception,
2231 [SVM_EXIT_MWAIT] = invalid_op_interception,
2232 [SVM_EXIT_NPF] = pf_interception,
2233 };
2234
2235 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2236 {
2237 struct vcpu_svm *svm = to_svm(vcpu);
2238 u32 exit_code = svm->vmcb->control.exit_code;
2239
2240 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2241 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2242
2243 if (is_nested(svm)) {
2244 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2245 exit_code, svm->vmcb->control.exit_info_1,
2246 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2247 if (nested_svm_exit_handled(svm, true)) {
2248 nested_svm_vmexit(svm);
2249 nsvm_printk("-> #VMEXIT\n");
2250 return 1;
2251 }
2252 }
2253
2254 if (npt_enabled) {
2255 int mmu_reload = 0;
2256 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2257 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2258 mmu_reload = 1;
2259 }
2260 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2261 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2262 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2263 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2264 kvm_inject_gp(vcpu, 0);
2265 return 1;
2266 }
2267 }
2268 if (mmu_reload) {
2269 kvm_mmu_reset_context(vcpu);
2270 kvm_mmu_load(vcpu);
2271 }
2272 }
2273
2274
2275 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2276 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2277 kvm_run->fail_entry.hardware_entry_failure_reason
2278 = svm->vmcb->control.exit_code;
2279 return 0;
2280 }
2281
2282 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2283 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2284 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2285 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2286 "exit_code 0x%x\n",
2287 __func__, svm->vmcb->control.exit_int_info,
2288 exit_code);
2289
2290 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2291 || !svm_exit_handlers[exit_code]) {
2292 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2293 kvm_run->hw.hardware_exit_reason = exit_code;
2294 return 0;
2295 }
2296
2297 return svm_exit_handlers[exit_code](svm, kvm_run);
2298 }
2299
2300 static void reload_tss(struct kvm_vcpu *vcpu)
2301 {
2302 int cpu = raw_smp_processor_id();
2303
2304 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2305 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2306 load_TR_desc();
2307 }
2308
2309 static void pre_svm_run(struct vcpu_svm *svm)
2310 {
2311 int cpu = raw_smp_processor_id();
2312
2313 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2314
2315 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2316 /* FIXME: handle wraparound of asid_generation */
2317 if (svm->asid_generation != svm_data->asid_generation)
2318 new_asid(svm, svm_data);
2319 }
2320
2321 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2322 {
2323 struct vcpu_svm *svm = to_svm(vcpu);
2324
2325 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2326 vcpu->arch.hflags |= HF_NMI_MASK;
2327 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2328 ++vcpu->stat.nmi_injections;
2329 }
2330
2331 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2332 {
2333 struct vmcb_control_area *control;
2334
2335 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2336
2337 ++svm->vcpu.stat.irq_injections;
2338 control = &svm->vmcb->control;
2339 control->int_vector = irq;
2340 control->int_ctl &= ~V_INTR_PRIO_MASK;
2341 control->int_ctl |= V_IRQ_MASK |
2342 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2343 }
2344
2345 static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
2346 {
2347 struct vcpu_svm *svm = to_svm(vcpu);
2348
2349 svm->vmcb->control.event_inj = nr |
2350 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2351 }
2352
2353 static void svm_set_irq(struct kvm_vcpu *vcpu)
2354 {
2355 struct vcpu_svm *svm = to_svm(vcpu);
2356
2357 nested_svm_intr(svm);
2358
2359 svm_queue_irq(vcpu, vcpu->arch.interrupt.nr);
2360 }
2361
2362 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2363 {
2364 struct vcpu_svm *svm = to_svm(vcpu);
2365
2366 if (irr == -1)
2367 return;
2368
2369 if (tpr >= irr)
2370 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2371 }
2372
2373 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2374 {
2375 struct vcpu_svm *svm = to_svm(vcpu);
2376 struct vmcb *vmcb = svm->vmcb;
2377 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2378 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2379 }
2380
2381 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2382 {
2383 struct vcpu_svm *svm = to_svm(vcpu);
2384 struct vmcb *vmcb = svm->vmcb;
2385 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2386 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2387 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2388 }
2389
2390 static void enable_irq_window(struct kvm_vcpu *vcpu)
2391 {
2392 svm_set_vintr(to_svm(vcpu));
2393 svm_inject_irq(to_svm(vcpu), 0x0);
2394 }
2395
2396 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2397 {
2398 struct vcpu_svm *svm = to_svm(vcpu);
2399
2400 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2401 == HF_NMI_MASK)
2402 return; /* IRET will cause a vm exit */
2403
2404 /* Something prevents NMI from been injected. Single step over
2405 possible problem (IRET or exception injection or interrupt
2406 shadow) */
2407 vcpu->arch.singlestep = true;
2408 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2409 update_db_intercept(vcpu);
2410 }
2411
2412 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2413 {
2414 return 0;
2415 }
2416
2417 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2418 {
2419 force_new_asid(vcpu);
2420 }
2421
2422 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2423 {
2424 }
2425
2426 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2427 {
2428 struct vcpu_svm *svm = to_svm(vcpu);
2429
2430 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2431 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2432 kvm_set_cr8(vcpu, cr8);
2433 }
2434 }
2435
2436 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2437 {
2438 struct vcpu_svm *svm = to_svm(vcpu);
2439 u64 cr8;
2440
2441 cr8 = kvm_get_cr8(vcpu);
2442 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2443 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2444 }
2445
2446 static void svm_complete_interrupts(struct vcpu_svm *svm)
2447 {
2448 u8 vector;
2449 int type;
2450 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2451
2452 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2453 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2454
2455 svm->vcpu.arch.nmi_injected = false;
2456 kvm_clear_exception_queue(&svm->vcpu);
2457 kvm_clear_interrupt_queue(&svm->vcpu);
2458
2459 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2460 return;
2461
2462 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2463 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2464
2465 switch (type) {
2466 case SVM_EXITINTINFO_TYPE_NMI:
2467 svm->vcpu.arch.nmi_injected = true;
2468 break;
2469 case SVM_EXITINTINFO_TYPE_EXEPT:
2470 /* In case of software exception do not reinject an exception
2471 vector, but re-execute and instruction instead */
2472 if (kvm_exception_is_soft(vector))
2473 break;
2474 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2475 u32 err = svm->vmcb->control.exit_int_info_err;
2476 kvm_queue_exception_e(&svm->vcpu, vector, err);
2477
2478 } else
2479 kvm_queue_exception(&svm->vcpu, vector);
2480 break;
2481 case SVM_EXITINTINFO_TYPE_INTR:
2482 kvm_queue_interrupt(&svm->vcpu, vector, false);
2483 break;
2484 default:
2485 break;
2486 }
2487 }
2488
2489 #ifdef CONFIG_X86_64
2490 #define R "r"
2491 #else
2492 #define R "e"
2493 #endif
2494
2495 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2496 {
2497 struct vcpu_svm *svm = to_svm(vcpu);
2498 u16 fs_selector;
2499 u16 gs_selector;
2500 u16 ldt_selector;
2501
2502 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2503 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2504 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2505
2506 pre_svm_run(svm);
2507
2508 sync_lapic_to_cr8(vcpu);
2509
2510 save_host_msrs(vcpu);
2511 fs_selector = kvm_read_fs();
2512 gs_selector = kvm_read_gs();
2513 ldt_selector = kvm_read_ldt();
2514 svm->host_cr2 = kvm_read_cr2();
2515 if (!is_nested(svm))
2516 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2517 /* required for live migration with NPT */
2518 if (npt_enabled)
2519 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2520
2521 clgi();
2522
2523 local_irq_enable();
2524
2525 asm volatile (
2526 "push %%"R"bp; \n\t"
2527 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2528 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2529 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2530 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2531 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2532 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2533 #ifdef CONFIG_X86_64
2534 "mov %c[r8](%[svm]), %%r8 \n\t"
2535 "mov %c[r9](%[svm]), %%r9 \n\t"
2536 "mov %c[r10](%[svm]), %%r10 \n\t"
2537 "mov %c[r11](%[svm]), %%r11 \n\t"
2538 "mov %c[r12](%[svm]), %%r12 \n\t"
2539 "mov %c[r13](%[svm]), %%r13 \n\t"
2540 "mov %c[r14](%[svm]), %%r14 \n\t"
2541 "mov %c[r15](%[svm]), %%r15 \n\t"
2542 #endif
2543
2544 /* Enter guest mode */
2545 "push %%"R"ax \n\t"
2546 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2547 __ex(SVM_VMLOAD) "\n\t"
2548 __ex(SVM_VMRUN) "\n\t"
2549 __ex(SVM_VMSAVE) "\n\t"
2550 "pop %%"R"ax \n\t"
2551
2552 /* Save guest registers, load host registers */
2553 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2554 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2555 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2556 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2557 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2558 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2559 #ifdef CONFIG_X86_64
2560 "mov %%r8, %c[r8](%[svm]) \n\t"
2561 "mov %%r9, %c[r9](%[svm]) \n\t"
2562 "mov %%r10, %c[r10](%[svm]) \n\t"
2563 "mov %%r11, %c[r11](%[svm]) \n\t"
2564 "mov %%r12, %c[r12](%[svm]) \n\t"
2565 "mov %%r13, %c[r13](%[svm]) \n\t"
2566 "mov %%r14, %c[r14](%[svm]) \n\t"
2567 "mov %%r15, %c[r15](%[svm]) \n\t"
2568 #endif
2569 "pop %%"R"bp"
2570 :
2571 : [svm]"a"(svm),
2572 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2573 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2574 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2575 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2576 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2577 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2578 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2579 #ifdef CONFIG_X86_64
2580 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2581 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2582 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2583 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2584 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2585 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2586 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2587 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2588 #endif
2589 : "cc", "memory"
2590 , R"bx", R"cx", R"dx", R"si", R"di"
2591 #ifdef CONFIG_X86_64
2592 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2593 #endif
2594 );
2595
2596 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2597 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2598 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2599 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2600
2601 kvm_write_cr2(svm->host_cr2);
2602
2603 kvm_load_fs(fs_selector);
2604 kvm_load_gs(gs_selector);
2605 kvm_load_ldt(ldt_selector);
2606 load_host_msrs(vcpu);
2607
2608 reload_tss(vcpu);
2609
2610 local_irq_disable();
2611
2612 stgi();
2613
2614 sync_cr8_to_lapic(vcpu);
2615
2616 svm->next_rip = 0;
2617
2618 svm_complete_interrupts(svm);
2619 }
2620
2621 #undef R
2622
2623 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2624 {
2625 struct vcpu_svm *svm = to_svm(vcpu);
2626
2627 if (npt_enabled) {
2628 svm->vmcb->control.nested_cr3 = root;
2629 force_new_asid(vcpu);
2630 return;
2631 }
2632
2633 svm->vmcb->save.cr3 = root;
2634 force_new_asid(vcpu);
2635
2636 if (vcpu->fpu_active) {
2637 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2638 svm->vmcb->save.cr0 |= X86_CR0_TS;
2639 vcpu->fpu_active = 0;
2640 }
2641 }
2642
2643 static int is_disabled(void)
2644 {
2645 u64 vm_cr;
2646
2647 rdmsrl(MSR_VM_CR, vm_cr);
2648 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2649 return 1;
2650
2651 return 0;
2652 }
2653
2654 static void
2655 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2656 {
2657 /*
2658 * Patch in the VMMCALL instruction:
2659 */
2660 hypercall[0] = 0x0f;
2661 hypercall[1] = 0x01;
2662 hypercall[2] = 0xd9;
2663 }
2664
2665 static void svm_check_processor_compat(void *rtn)
2666 {
2667 *(int *)rtn = 0;
2668 }
2669
2670 static bool svm_cpu_has_accelerated_tpr(void)
2671 {
2672 return false;
2673 }
2674
2675 static int get_npt_level(void)
2676 {
2677 #ifdef CONFIG_X86_64
2678 return PT64_ROOT_LEVEL;
2679 #else
2680 return PT32E_ROOT_LEVEL;
2681 #endif
2682 }
2683
2684 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2685 {
2686 return 0;
2687 }
2688
2689 static struct kvm_x86_ops svm_x86_ops = {
2690 .cpu_has_kvm_support = has_svm,
2691 .disabled_by_bios = is_disabled,
2692 .hardware_setup = svm_hardware_setup,
2693 .hardware_unsetup = svm_hardware_unsetup,
2694 .check_processor_compatibility = svm_check_processor_compat,
2695 .hardware_enable = svm_hardware_enable,
2696 .hardware_disable = svm_hardware_disable,
2697 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2698
2699 .vcpu_create = svm_create_vcpu,
2700 .vcpu_free = svm_free_vcpu,
2701 .vcpu_reset = svm_vcpu_reset,
2702
2703 .prepare_guest_switch = svm_prepare_guest_switch,
2704 .vcpu_load = svm_vcpu_load,
2705 .vcpu_put = svm_vcpu_put,
2706
2707 .set_guest_debug = svm_guest_debug,
2708 .get_msr = svm_get_msr,
2709 .set_msr = svm_set_msr,
2710 .get_segment_base = svm_get_segment_base,
2711 .get_segment = svm_get_segment,
2712 .set_segment = svm_set_segment,
2713 .get_cpl = svm_get_cpl,
2714 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2715 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2716 .set_cr0 = svm_set_cr0,
2717 .set_cr3 = svm_set_cr3,
2718 .set_cr4 = svm_set_cr4,
2719 .set_efer = svm_set_efer,
2720 .get_idt = svm_get_idt,
2721 .set_idt = svm_set_idt,
2722 .get_gdt = svm_get_gdt,
2723 .set_gdt = svm_set_gdt,
2724 .get_dr = svm_get_dr,
2725 .set_dr = svm_set_dr,
2726 .get_rflags = svm_get_rflags,
2727 .set_rflags = svm_set_rflags,
2728
2729 .tlb_flush = svm_flush_tlb,
2730
2731 .run = svm_vcpu_run,
2732 .handle_exit = handle_exit,
2733 .skip_emulated_instruction = skip_emulated_instruction,
2734 .set_interrupt_shadow = svm_set_interrupt_shadow,
2735 .get_interrupt_shadow = svm_get_interrupt_shadow,
2736 .patch_hypercall = svm_patch_hypercall,
2737 .set_irq = svm_set_irq,
2738 .set_nmi = svm_inject_nmi,
2739 .queue_exception = svm_queue_exception,
2740 .interrupt_allowed = svm_interrupt_allowed,
2741 .nmi_allowed = svm_nmi_allowed,
2742 .enable_nmi_window = enable_nmi_window,
2743 .enable_irq_window = enable_irq_window,
2744 .update_cr8_intercept = update_cr8_intercept,
2745
2746 .set_tss_addr = svm_set_tss_addr,
2747 .get_tdp_level = get_npt_level,
2748 .get_mt_mask = svm_get_mt_mask,
2749 };
2750
2751 static int __init svm_init(void)
2752 {
2753 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2754 THIS_MODULE);
2755 }
2756
2757 static void __exit svm_exit(void)
2758 {
2759 kvm_exit();
2760 }
2761
2762 module_init(svm_init)
2763 module_exit(svm_exit)
Linux with added FPC-III support