x86: Adjust section placement in AMD northbridge related code
[linux/fpc-iii.git] / arch / x86 / include / asm / agp.h
blobeec2a70d4376ec98832937471bf701ae67db3e28
1 #ifndef _ASM_X86_AGP_H
2 #define _ASM_X86_AGP_H
4 #include <asm/pgtable.h>
5 #include <asm/cacheflush.h>
7 /*
8 * Functions to keep the agpgart mappings coherent with the MMU. The
9 * GART gives the CPU a physical alias of pages in memory. The alias
10 * region is mapped uncacheable. Make sure there are no conflicting
11 * mappings with different cachability attributes for the same
12 * page. This avoids data corruption on some CPUs.
15 #define map_page_into_agp(page) set_pages_uc(page, 1)
16 #define unmap_page_from_agp(page) set_pages_wb(page, 1)
19 * Could use CLFLUSH here if the cpu supports it. But then it would
20 * need to be called for each cacheline of the whole page so it may
21 * not be worth it. Would need a page for it.
23 #define flush_agp_cache() wbinvd()
25 /* GATT allocation. Returns/accepts GATT kernel virtual address. */
26 #define alloc_gatt_pages(order) \
27 ((char *)__get_free_pages(GFP_KERNEL, (order)))
28 #define free_gatt_pages(table, order) \
29 free_pages((unsigned long)(table), (order))
31 #endif /* _ASM_X86_AGP_H */