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x86: Adjust section placement in AMD northbridge related code
[linux/fpc-iii.git] / arch / x86 / include / asm / perf_event_p4.h
blobe2f6a99f14ab3eb47b48da80a21ebc676e4eaa82
1 /*
2 * Netburst Perfomance Events (P4, old Xeon)
3 */
4
5 #ifndef PERF_EVENT_P4_H
6 #define PERF_EVENT_P4_H
7
8 #include <linux/cpu.h>
9 #include <linux/bitops.h>
10
11 /*
12 * NetBurst has perfomance MSRs shared between
13 * threads if HT is turned on, ie for both logical
14 * processors (mem: in turn in Atom with HT support
15 * perf-MSRs are not shared and every thread has its
16 * own perf-MSRs set)
17 */
18 #define ARCH_P4_TOTAL_ESCR (46)
19 #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */
20 #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
21 #define ARCH_P4_MAX_CCCR (18)
22
23 #define ARCH_P4_CNTRVAL_BITS (40)
24 #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
25
26 #define P4_ESCR_EVENT_MASK 0x7e000000U
27 #define P4_ESCR_EVENT_SHIFT 25
28 #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U
29 #define P4_ESCR_EVENTMASK_SHIFT 9
30 #define P4_ESCR_TAG_MASK 0x000001e0U
31 #define P4_ESCR_TAG_SHIFT 5
32 #define P4_ESCR_TAG_ENABLE 0x00000010U
33 #define P4_ESCR_T0_OS 0x00000008U
34 #define P4_ESCR_T0_USR 0x00000004U
35 #define P4_ESCR_T1_OS 0x00000002U
36 #define P4_ESCR_T1_USR 0x00000001U
37
38 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT)
39 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT)
40 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT)
41
42 #define P4_CCCR_OVF 0x80000000U
43 #define P4_CCCR_CASCADE 0x40000000U
44 #define P4_CCCR_OVF_PMI_T0 0x04000000U
45 #define P4_CCCR_OVF_PMI_T1 0x08000000U
46 #define P4_CCCR_FORCE_OVF 0x02000000U
47 #define P4_CCCR_EDGE 0x01000000U
48 #define P4_CCCR_THRESHOLD_MASK 0x00f00000U
49 #define P4_CCCR_THRESHOLD_SHIFT 20
50 #define P4_CCCR_COMPLEMENT 0x00080000U
51 #define P4_CCCR_COMPARE 0x00040000U
52 #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U
53 #define P4_CCCR_ESCR_SELECT_SHIFT 13
54 #define P4_CCCR_ENABLE 0x00001000U
55 #define P4_CCCR_THREAD_SINGLE 0x00010000U
56 #define P4_CCCR_THREAD_BOTH 0x00020000U
57 #define P4_CCCR_THREAD_ANY 0x00030000U
58 #define P4_CCCR_RESERVED 0x00000fffU
59
60 #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)
61 #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
62
63 #define P4_GEN_ESCR_EMASK(class, name, bit) \
64 class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
65 #define P4_ESCR_EMASK_BIT(class, name) class##__##name
66
67 /*
68 * config field is 64bit width and consists of
69 * HT << 63 | ESCR << 32 | CCCR
70 * where HT is HyperThreading bit (since ESCR
71 * has it reserved we may use it for own purpose)
72 *
73 * note that this is NOT the addresses of respective
74 * ESCR and CCCR but rather an only packed value should
75 * be unpacked and written to a proper addresses
76 *
77 * the base idea is to pack as much info as possible
78 */
79 #define p4_config_pack_escr(v) (((u64)(v)) << 32)
80 #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL)
81 #define p4_config_unpack_escr(v) (((u64)(v)) >> 32)
82 #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL)
83
84 #define p4_config_unpack_emask(v) \
85 ({ \
86 u32 t = p4_config_unpack_escr((v)); \
87 t = t & P4_ESCR_EVENTMASK_MASK; \
88 t = t >> P4_ESCR_EVENTMASK_SHIFT; \
89 t; \
90 })
91
92 #define p4_config_unpack_event(v) \
93 ({ \
94 u32 t = p4_config_unpack_escr((v)); \
95 t = t & P4_ESCR_EVENT_MASK; \
96 t = t >> P4_ESCR_EVENT_SHIFT; \
97 t; \
98 })
99
100 #define P4_CONFIG_HT_SHIFT 63
101 #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT)
102
103 /*
104 * The bits we allow to pass for RAW events
105 */
106 #define P4_CONFIG_MASK_ESCR \
107 P4_ESCR_EVENT_MASK | \
108 P4_ESCR_EVENTMASK_MASK | \
109 P4_ESCR_TAG_MASK | \
110 P4_ESCR_TAG_ENABLE
111
112 #define P4_CONFIG_MASK_CCCR \
113 P4_CCCR_EDGE | \
114 P4_CCCR_THRESHOLD_MASK | \
115 P4_CCCR_COMPLEMENT | \
116 P4_CCCR_COMPARE | \
117 P4_CCCR_THREAD_ANY | \
118 P4_CCCR_RESERVED
119
120 /* some dangerous bits are reserved for kernel internals */
121 #define P4_CONFIG_MASK \
122 (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \
123 (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR))
124
125 static inline bool p4_is_event_cascaded(u64 config)
126 {
127 u32 cccr = p4_config_unpack_cccr(config);
128 return !!(cccr & P4_CCCR_CASCADE);
129 }
130
131 static inline int p4_ht_config_thread(u64 config)
132 {
133 return !!(config & P4_CONFIG_HT);
134 }
135
136 static inline u64 p4_set_ht_bit(u64 config)
137 {
138 return config | P4_CONFIG_HT;
139 }
140
141 static inline u64 p4_clear_ht_bit(u64 config)
142 {
143 return config & ~P4_CONFIG_HT;
144 }
145
146 static inline int p4_ht_active(void)
147 {
148 #ifdef CONFIG_SMP
149 return smp_num_siblings > 1;
150 #endif
151 return 0;
152 }
153
154 static inline int p4_ht_thread(int cpu)
155 {
156 #ifdef CONFIG_SMP
157 if (smp_num_siblings == 2)
158 return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map));
159 #endif
160 return 0;
161 }
162
163 static inline int p4_should_swap_ts(u64 config, int cpu)
164 {
165 return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);
166 }
167
168 static inline u32 p4_default_cccr_conf(int cpu)
169 {
170 /*
171 * Note that P4_CCCR_THREAD_ANY is "required" on
172 * non-HT machines (on HT machines we count TS events
173 * regardless the state of second logical processor
174 */
175 u32 cccr = P4_CCCR_THREAD_ANY;
176
177 if (!p4_ht_thread(cpu))
178 cccr |= P4_CCCR_OVF_PMI_T0;
179 else
180 cccr |= P4_CCCR_OVF_PMI_T1;
181
182 return cccr;
183 }
184
185 static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
186 {
187 u32 escr = 0;
188
189 if (!p4_ht_thread(cpu)) {
190 if (!exclude_os)
191 escr |= P4_ESCR_T0_OS;
192 if (!exclude_usr)
193 escr |= P4_ESCR_T0_USR;
194 } else {
195 if (!exclude_os)
196 escr |= P4_ESCR_T1_OS;
197 if (!exclude_usr)
198 escr |= P4_ESCR_T1_USR;
199 }
200
201 return escr;
202 }
203
204 /*
205 * This are the events which should be used in "Event Select"
206 * field of ESCR register, they are like unique keys which allow
207 * the kernel to determinate which CCCR and COUNTER should be
208 * used to track an event
209 */
210 enum P4_EVENTS {
211 P4_EVENT_TC_DELIVER_MODE,
212 P4_EVENT_BPU_FETCH_REQUEST,
213 P4_EVENT_ITLB_REFERENCE,
214 P4_EVENT_MEMORY_CANCEL,
215 P4_EVENT_MEMORY_COMPLETE,
216 P4_EVENT_LOAD_PORT_REPLAY,
217 P4_EVENT_STORE_PORT_REPLAY,
218 P4_EVENT_MOB_LOAD_REPLAY,
219 P4_EVENT_PAGE_WALK_TYPE,
220 P4_EVENT_BSQ_CACHE_REFERENCE,
221 P4_EVENT_IOQ_ALLOCATION,
222 P4_EVENT_IOQ_ACTIVE_ENTRIES,
223 P4_EVENT_FSB_DATA_ACTIVITY,
224 P4_EVENT_BSQ_ALLOCATION,
225 P4_EVENT_BSQ_ACTIVE_ENTRIES,
226 P4_EVENT_SSE_INPUT_ASSIST,
227 P4_EVENT_PACKED_SP_UOP,
228 P4_EVENT_PACKED_DP_UOP,
229 P4_EVENT_SCALAR_SP_UOP,
230 P4_EVENT_SCALAR_DP_UOP,
231 P4_EVENT_64BIT_MMX_UOP,
232 P4_EVENT_128BIT_MMX_UOP,
233 P4_EVENT_X87_FP_UOP,
234 P4_EVENT_TC_MISC,
235 P4_EVENT_GLOBAL_POWER_EVENTS,
236 P4_EVENT_TC_MS_XFER,
237 P4_EVENT_UOP_QUEUE_WRITES,
238 P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
239 P4_EVENT_RETIRED_BRANCH_TYPE,
240 P4_EVENT_RESOURCE_STALL,
241 P4_EVENT_WC_BUFFER,
242 P4_EVENT_B2B_CYCLES,
243 P4_EVENT_BNR,
244 P4_EVENT_SNOOP,
245 P4_EVENT_RESPONSE,
246 P4_EVENT_FRONT_END_EVENT,
247 P4_EVENT_EXECUTION_EVENT,
248 P4_EVENT_REPLAY_EVENT,
249 P4_EVENT_INSTR_RETIRED,
250 P4_EVENT_UOPS_RETIRED,
251 P4_EVENT_UOP_TYPE,
252 P4_EVENT_BRANCH_RETIRED,
253 P4_EVENT_MISPRED_BRANCH_RETIRED,
254 P4_EVENT_X87_ASSIST,
255 P4_EVENT_MACHINE_CLEAR,
256 P4_EVENT_INSTR_COMPLETED,
257 };
258
259 #define P4_OPCODE(event) event##_OPCODE
260 #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0)
261 #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8)
262 #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel)
263
264 /*
265 * Comments below the event represent ESCR restriction
266 * for this event and counter index per ESCR
267 *
268 * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early
269 * processor builds (family 0FH, models 01H-02H). These MSRs
270 * are not available on later versions, so that we don't use
271 * them completely
272 *
273 * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly
274 * working so that we should not use this CCCR and respective
275 * counter as result
276 */
277 enum P4_EVENT_OPCODES {
278 P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),
279 /*
280 * MSR_P4_TC_ESCR0: 4, 5
281 * MSR_P4_TC_ESCR1: 6, 7
282 */
283
284 P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00),
285 /*
286 * MSR_P4_BPU_ESCR0: 0, 1
287 * MSR_P4_BPU_ESCR1: 2, 3
288 */
289
290 P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03),
291 /*
292 * MSR_P4_ITLB_ESCR0: 0, 1
293 * MSR_P4_ITLB_ESCR1: 2, 3
294 */
295
296 P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05),
297 /*
298 * MSR_P4_DAC_ESCR0: 8, 9
299 * MSR_P4_DAC_ESCR1: 10, 11
300 */
301
302 P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02),
303 /*
304 * MSR_P4_SAAT_ESCR0: 8, 9
305 * MSR_P4_SAAT_ESCR1: 10, 11
306 */
307
308 P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02),
309 /*
310 * MSR_P4_SAAT_ESCR0: 8, 9
311 * MSR_P4_SAAT_ESCR1: 10, 11
312 */
313
314 P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02),
315 /*
316 * MSR_P4_SAAT_ESCR0: 8, 9
317 * MSR_P4_SAAT_ESCR1: 10, 11
318 */
319
320 P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02),
321 /*
322 * MSR_P4_MOB_ESCR0: 0, 1
323 * MSR_P4_MOB_ESCR1: 2, 3
324 */
325
326 P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04),
327 /*
328 * MSR_P4_PMH_ESCR0: 0, 1
329 * MSR_P4_PMH_ESCR1: 2, 3
330 */
331
332 P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07),
333 /*
334 * MSR_P4_BSU_ESCR0: 0, 1
335 * MSR_P4_BSU_ESCR1: 2, 3
336 */
337
338 P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06),
339 /*
340 * MSR_P4_FSB_ESCR0: 0, 1
341 * MSR_P4_FSB_ESCR1: 2, 3
342 */
343
344 P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06),
345 /*
346 * MSR_P4_FSB_ESCR1: 2, 3
347 */
348
349 P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06),
350 /*
351 * MSR_P4_FSB_ESCR0: 0, 1
352 * MSR_P4_FSB_ESCR1: 2, 3
353 */
354
355 P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07),
356 /*
357 * MSR_P4_BSU_ESCR0: 0, 1
358 */
359
360 P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07),
361 /*
362 * NOTE: no ESCR name in docs, it's guessed
363 * MSR_P4_BSU_ESCR1: 2, 3
364 */
365
366 P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01),
367 /*
368 * MSR_P4_FIRM_ESCR0: 8, 9
369 * MSR_P4_FIRM_ESCR1: 10, 11
370 */
371
372 P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01),
373 /*
374 * MSR_P4_FIRM_ESCR0: 8, 9
375 * MSR_P4_FIRM_ESCR1: 10, 11
376 */
377
378 P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01),
379 /*
380 * MSR_P4_FIRM_ESCR0: 8, 9
381 * MSR_P4_FIRM_ESCR1: 10, 11
382 */
383
384 P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01),
385 /*
386 * MSR_P4_FIRM_ESCR0: 8, 9
387 * MSR_P4_FIRM_ESCR1: 10, 11
388 */
389
390 P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01),
391 /*
392 * MSR_P4_FIRM_ESCR0: 8, 9
393 * MSR_P4_FIRM_ESCR1: 10, 11
394 */
395
396 P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01),
397 /*
398 * MSR_P4_FIRM_ESCR0: 8, 9
399 * MSR_P4_FIRM_ESCR1: 10, 11
400 */
401
402 P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01),
403 /*
404 * MSR_P4_FIRM_ESCR0: 8, 9
405 * MSR_P4_FIRM_ESCR1: 10, 11
406 */
407
408 P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01),
409 /*
410 * MSR_P4_FIRM_ESCR0: 8, 9
411 * MSR_P4_FIRM_ESCR1: 10, 11
412 */
413
414 P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01),
415 /*
416 * MSR_P4_TC_ESCR0: 4, 5
417 * MSR_P4_TC_ESCR1: 6, 7
418 */
419
420 P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06),
421 /*
422 * MSR_P4_FSB_ESCR0: 0, 1
423 * MSR_P4_FSB_ESCR1: 2, 3
424 */
425
426 P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00),
427 /*
428 * MSR_P4_MS_ESCR0: 4, 5
429 * MSR_P4_MS_ESCR1: 6, 7
430 */
431
432 P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00),
433 /*
434 * MSR_P4_MS_ESCR0: 4, 5
435 * MSR_P4_MS_ESCR1: 6, 7
436 */
437
438 P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02),
439 /*
440 * MSR_P4_TBPU_ESCR0: 4, 5
441 * MSR_P4_TBPU_ESCR1: 6, 7
442 */
443
444 P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02),
445 /*
446 * MSR_P4_TBPU_ESCR0: 4, 5
447 * MSR_P4_TBPU_ESCR1: 6, 7
448 */
449
450 P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01),
451 /*
452 * MSR_P4_ALF_ESCR0: 12, 13, 16
453 * MSR_P4_ALF_ESCR1: 14, 15, 17
454 */
455
456 P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05),
457 /*
458 * MSR_P4_DAC_ESCR0: 8, 9
459 * MSR_P4_DAC_ESCR1: 10, 11
460 */
461
462 P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03),
463 /*
464 * MSR_P4_FSB_ESCR0: 0, 1
465 * MSR_P4_FSB_ESCR1: 2, 3
466 */
467
468 P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03),
469 /*
470 * MSR_P4_FSB_ESCR0: 0, 1
471 * MSR_P4_FSB_ESCR1: 2, 3
472 */
473
474 P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03),
475 /*
476 * MSR_P4_FSB_ESCR0: 0, 1
477 * MSR_P4_FSB_ESCR1: 2, 3
478 */
479
480 P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03),
481 /*
482 * MSR_P4_FSB_ESCR0: 0, 1
483 * MSR_P4_FSB_ESCR1: 2, 3
484 */
485
486 P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05),
487 /*
488 * MSR_P4_CRU_ESCR2: 12, 13, 16
489 * MSR_P4_CRU_ESCR3: 14, 15, 17
490 */
491
492 P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05),
493 /*
494 * MSR_P4_CRU_ESCR2: 12, 13, 16
495 * MSR_P4_CRU_ESCR3: 14, 15, 17
496 */
497
498 P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05),
499 /*
500 * MSR_P4_CRU_ESCR2: 12, 13, 16
501 * MSR_P4_CRU_ESCR3: 14, 15, 17
502 */
503
504 P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04),
505 /*
506 * MSR_P4_CRU_ESCR0: 12, 13, 16
507 * MSR_P4_CRU_ESCR1: 14, 15, 17
508 */
509
510 P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04),
511 /*
512 * MSR_P4_CRU_ESCR0: 12, 13, 16
513 * MSR_P4_CRU_ESCR1: 14, 15, 17
514 */
515
516 P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02),
517 /*
518 * MSR_P4_RAT_ESCR0: 12, 13, 16
519 * MSR_P4_RAT_ESCR1: 14, 15, 17
520 */
521
522 P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05),
523 /*
524 * MSR_P4_CRU_ESCR2: 12, 13, 16
525 * MSR_P4_CRU_ESCR3: 14, 15, 17
526 */
527
528 P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04),
529 /*
530 * MSR_P4_CRU_ESCR0: 12, 13, 16
531 * MSR_P4_CRU_ESCR1: 14, 15, 17
532 */
533
534 P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05),
535 /*
536 * MSR_P4_CRU_ESCR2: 12, 13, 16
537 * MSR_P4_CRU_ESCR3: 14, 15, 17
538 */
539
540 P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05),
541 /*
542 * MSR_P4_CRU_ESCR2: 12, 13, 16
543 * MSR_P4_CRU_ESCR3: 14, 15, 17
544 */
545
546 P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04),
547 /*
548 * MSR_P4_CRU_ESCR0: 12, 13, 16
549 * MSR_P4_CRU_ESCR1: 14, 15, 17
550 */
551 };
552
553 /*
554 * a caller should use P4_ESCR_EMASK_NAME helper to
555 * pick the EventMask needed, for example
556 *
557 * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD)
558 */
559 enum P4_ESCR_EMASKS {
560 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0),
561 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1),
562 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2),
563 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3),
564 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4),
565 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5),
566 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6),
567
568 P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0),
569
570 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0),
571 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1),
572 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2),
573
574 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2),
575 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3),
576
577 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0),
578 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
579
580 P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1),
581
582 P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1),
583
584 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1),
585 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3),
586 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
587 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
588
589 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0),
590 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1),
591
592 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
593 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
594 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
595 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
596 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
597 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
598 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
599 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
600 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
601
602 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0),
603 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5),
604 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6),
605 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7),
606 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8),
607 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9),
608 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10),
609 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11),
610 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13),
611 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14),
612 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15),
613
614 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
615 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
616 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
617 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
618 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
619 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
620 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
621 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
622 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13),
623 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14),
624 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
625
626 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
627 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
628 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
629 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
630 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
631 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
632
633 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0),
634 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1),
635 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2),
636 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3),
637 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
638 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
639 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
640 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
641 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
642 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
643 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11),
644 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12),
645 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13),
646
647 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
648 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
649 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
650 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
651 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
652 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
653 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
654 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
655 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
656 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
657 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
658 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
659 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
660
661 P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15),
662
663 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15),
664
665 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15),
666
667 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15),
668
669 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15),
670
671 P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15),
672
673 P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15),
674
675 P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15),
676
677 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4),
678
679 P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0),
680
681 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0),
682
683 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
684 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
685 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2),
686
687 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
688 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
689 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
690 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
691
692 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
693 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2),
694 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3),
695 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4),
696
697 P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5),
698
699 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0),
700 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1),
701
702 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0),
703 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1),
704
705 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0),
706 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1),
707 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2),
708 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3),
709 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4),
710 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5),
711 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6),
712 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7),
713
714 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0),
715 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1),
716
717 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0),
718 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1),
719 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2),
720 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3),
721
722 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0),
723 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1),
724
725 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1),
726 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2),
727
728 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0),
729 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1),
730 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2),
731 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3),
732
733 P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
734
735 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0),
736 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1),
737 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2),
738 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3),
739 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4),
740
741 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0),
742 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1),
743 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2),
744
745 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0),
746 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1),
747 };
748
749 /*
750 * Note we have UOP and PEBS bits reserved for now
751 * just in case if we will need them once
752 */
753 #define P4_PEBS_CONFIG_ENABLE (1 << 7)
754 #define P4_PEBS_CONFIG_UOP_TAG (1 << 8)
755 #define P4_PEBS_CONFIG_METRIC_MASK 0x3f
756 #define P4_PEBS_CONFIG_MASK 0xff
757
758 /*
759 * mem: Only counters MSR_IQ_COUNTER4 (16) and
760 * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
761 */
762 #define P4_PEBS_ENABLE 0x02000000U
763 #define P4_PEBS_ENABLE_UOP_TAG 0x01000000U
764
765 #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
766 #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK)
767
768 #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask))
769
770 enum P4_PEBS_METRIC {
771 P4_PEBS_METRIC__none,
772
773 P4_PEBS_METRIC__1stl_cache_load_miss_retired,
774 P4_PEBS_METRIC__2ndl_cache_load_miss_retired,
775 P4_PEBS_METRIC__dtlb_load_miss_retired,
776 P4_PEBS_METRIC__dtlb_store_miss_retired,
777 P4_PEBS_METRIC__dtlb_all_miss_retired,
778 P4_PEBS_METRIC__tagged_mispred_branch,
779 P4_PEBS_METRIC__mob_load_replay_retired,
780 P4_PEBS_METRIC__split_load_retired,
781 P4_PEBS_METRIC__split_store_retired,
782
783 P4_PEBS_METRIC__max
784 };
785
786 /*
787 * Notes on internal configuration of ESCR+CCCR tuples
788 *
789 * Since P4 has quite the different architecture of
790 * performance registers in compare with "architectural"
791 * once and we have on 64 bits to keep configuration
792 * of performance event, the following trick is used.
793 *
794 * 1) Since both ESCR and CCCR registers have only low
795 * 32 bits valuable, we pack them into a single 64 bit
796 * configuration. Low 32 bits of such config correspond
797 * to low 32 bits of CCCR register and high 32 bits
798 * correspond to low 32 bits of ESCR register.
799 *
800 * 2) The meaning of every bit of such config field can
801 * be found in Intel SDM but it should be noted that
802 * we "borrow" some reserved bits for own usage and
803 * clean them or set to a proper value when we do
804 * a real write to hardware registers.
805 *
806 * 3) The format of bits of config is the following
807 * and should be either 0 or set to some predefined
808 * values:
809 *
810 * Low 32 bits
811 * -----------
812 * 0-6: P4_PEBS_METRIC enum
813 * 7-11: reserved
814 * 12: reserved (Enable)
815 * 13-15: reserved (ESCR select)
816 * 16-17: Active Thread
817 * 18: Compare
818 * 19: Complement
819 * 20-23: Threshold
820 * 24: Edge
821 * 25: reserved (FORCE_OVF)
822 * 26: reserved (OVF_PMI_T0)
823 * 27: reserved (OVF_PMI_T1)
824 * 28-29: reserved
825 * 30: reserved (Cascade)
826 * 31: reserved (OVF)
827 *
828 * High 32 bits
829 * ------------
830 * 0: reserved (T1_USR)
831 * 1: reserved (T1_OS)
832 * 2: reserved (T0_USR)
833 * 3: reserved (T0_OS)
834 * 4: Tag Enable
835 * 5-8: Tag Value
836 * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
837 * 25-30: enum P4_EVENTS
838 * 31: reserved (HT thread)
839 */
840
841 #endif /* PERF_EVENT_P4_H */
842
Linux with added FPC-III support