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x86: Adjust section placement in AMD northbridge related code
[linux/fpc-iii.git] / arch / x86 / include / asm / processor.h
blob45636cefa186b427f558d98b7257a0f00dd405ec
1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
18 #include <asm/page.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
21 #include <asm/msr.h>
22 #include <asm/desc_defs.h>
23 #include <asm/nops.h>
24
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32
33 #define HBP_NUM 4
34 /*
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
37 */
38 static inline void *current_text_addr(void)
39 {
40 void *pc;
41
42 asm volatile("mov $1f, %0; 1:":"=r" (pc));
43
44 return pc;
45 }
46
47 #ifdef CONFIG_X86_VSMP
48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
50 #else
51 # define ARCH_MIN_TASKALIGN 16
52 # define ARCH_MIN_MMSTRUCT_ALIGN 0
53 #endif
54
55 /*
56 * CPU type and hardware bug flags. Kept separately for each CPU.
57 * Members of this structure are referenced in head.S, so think twice
58 * before touching them. [mj]
59 */
60
61 struct cpuinfo_x86 {
62 __u8 x86; /* CPU family */
63 __u8 x86_vendor; /* CPU vendor */
64 __u8 x86_model;
65 __u8 x86_mask;
66 #ifdef CONFIG_X86_32
67 char wp_works_ok; /* It doesn't on 386's */
68
69 /* Problems on some 486Dx4's and old 386's: */
70 char hlt_works_ok;
71 char hard_math;
72 char rfu;
73 char fdiv_bug;
74 char f00f_bug;
75 char coma_bug;
76 char pad0;
77 #else
78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
79 int x86_tlbsize;
80 #endif
81 __u8 x86_virt_bits;
82 __u8 x86_phys_bits;
83 /* CPUID returned core id bits: */
84 __u8 x86_coreid_bits;
85 /* Max extended CPUID function supported: */
86 __u32 extended_cpuid_level;
87 /* Maximum supported CPUID level, -1=no CPUID: */
88 int cpuid_level;
89 __u32 x86_capability[NCAPINTS];
90 char x86_vendor_id[16];
91 char x86_model_id[64];
92 /* in KB - valid for CPUS which support this call: */
93 int x86_cache_size;
94 int x86_cache_alignment; /* In bytes */
95 int x86_power;
96 unsigned long loops_per_jiffy;
97 #ifdef CONFIG_SMP
98 /* cpus sharing the last level cache: */
99 cpumask_var_t llc_shared_map;
100 #endif
101 /* cpuid returned max cores value: */
102 u16 x86_max_cores;
103 u16 apicid;
104 u16 initial_apicid;
105 u16 x86_clflush_size;
106 #ifdef CONFIG_SMP
107 /* number of cores as seen by the OS: */
108 u16 booted_cores;
109 /* Physical processor id: */
110 u16 phys_proc_id;
111 /* Core id: */
112 u16 cpu_core_id;
113 /* Compute unit id */
114 u8 compute_unit_id;
115 /* Index into per_cpu list: */
116 u16 cpu_index;
117 #endif
118 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
119
120 #define X86_VENDOR_INTEL 0
121 #define X86_VENDOR_CYRIX 1
122 #define X86_VENDOR_AMD 2
123 #define X86_VENDOR_UMC 3
124 #define X86_VENDOR_CENTAUR 5
125 #define X86_VENDOR_TRANSMETA 7
126 #define X86_VENDOR_NSC 8
127 #define X86_VENDOR_NUM 9
128
129 #define X86_VENDOR_UNKNOWN 0xff
130
131 /*
132 * capabilities of CPUs
133 */
134 extern struct cpuinfo_x86 boot_cpu_data;
135 extern struct cpuinfo_x86 new_cpu_data;
136
137 extern struct tss_struct doublefault_tss;
138 extern __u32 cpu_caps_cleared[NCAPINTS];
139 extern __u32 cpu_caps_set[NCAPINTS];
140
141 #ifdef CONFIG_SMP
142 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
143 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
144 #else
145 #define cpu_info boot_cpu_data
146 #define cpu_data(cpu) boot_cpu_data
147 #endif
148
149 extern const struct seq_operations cpuinfo_op;
150
151 static inline int hlt_works(int cpu)
152 {
153 #ifdef CONFIG_X86_32
154 return cpu_data(cpu).hlt_works_ok;
155 #else
156 return 1;
157 #endif
158 }
159
160 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
161
162 extern void cpu_detect(struct cpuinfo_x86 *c);
163
164 extern struct pt_regs *idle_regs(struct pt_regs *);
165
166 extern void early_cpu_init(void);
167 extern void identify_boot_cpu(void);
168 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
169 extern void print_cpu_info(struct cpuinfo_x86 *);
170 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
171 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
172 extern unsigned short num_cache_leaves;
173
174 extern void detect_extended_topology(struct cpuinfo_x86 *c);
175 extern void detect_ht(struct cpuinfo_x86 *c);
176
177 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
178 unsigned int *ecx, unsigned int *edx)
179 {
180 /* ecx is often an input as well as an output. */
181 asm volatile("cpuid"
182 : "=a" (*eax),
183 "=b" (*ebx),
184 "=c" (*ecx),
185 "=d" (*edx)
186 : "0" (*eax), "2" (*ecx));
187 }
188
189 static inline void load_cr3(pgd_t *pgdir)
190 {
191 write_cr3(__pa(pgdir));
192 }
193
194 #ifdef CONFIG_X86_32
195 /* This is the TSS defined by the hardware. */
196 struct x86_hw_tss {
197 unsigned short back_link, __blh;
198 unsigned long sp0;
199 unsigned short ss0, __ss0h;
200 unsigned long sp1;
201 /* ss1 caches MSR_IA32_SYSENTER_CS: */
202 unsigned short ss1, __ss1h;
203 unsigned long sp2;
204 unsigned short ss2, __ss2h;
205 unsigned long __cr3;
206 unsigned long ip;
207 unsigned long flags;
208 unsigned long ax;
209 unsigned long cx;
210 unsigned long dx;
211 unsigned long bx;
212 unsigned long sp;
213 unsigned long bp;
214 unsigned long si;
215 unsigned long di;
216 unsigned short es, __esh;
217 unsigned short cs, __csh;
218 unsigned short ss, __ssh;
219 unsigned short ds, __dsh;
220 unsigned short fs, __fsh;
221 unsigned short gs, __gsh;
222 unsigned short ldt, __ldth;
223 unsigned short trace;
224 unsigned short io_bitmap_base;
225
226 } __attribute__((packed));
227 #else
228 struct x86_hw_tss {
229 u32 reserved1;
230 u64 sp0;
231 u64 sp1;
232 u64 sp2;
233 u64 reserved2;
234 u64 ist[7];
235 u32 reserved3;
236 u32 reserved4;
237 u16 reserved5;
238 u16 io_bitmap_base;
239
240 } __attribute__((packed)) ____cacheline_aligned;
241 #endif
242
243 /*
244 * IO-bitmap sizes:
245 */
246 #define IO_BITMAP_BITS 65536
247 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
248 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
249 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
250 #define INVALID_IO_BITMAP_OFFSET 0x8000
251
252 struct tss_struct {
253 /*
254 * The hardware state:
255 */
256 struct x86_hw_tss x86_tss;
257
258 /*
259 * The extra 1 is there because the CPU will access an
260 * additional byte beyond the end of the IO permission
261 * bitmap. The extra byte must be all 1 bits, and must
262 * be within the limit.
263 */
264 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
265
266 /*
267 * .. and then another 0x100 bytes for the emergency kernel stack:
268 */
269 unsigned long stack[64];
270
271 } ____cacheline_aligned;
272
273 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
274
275 /*
276 * Save the original ist values for checking stack pointers during debugging
277 */
278 struct orig_ist {
279 unsigned long ist[7];
280 };
281
282 #define MXCSR_DEFAULT 0x1f80
283
284 struct i387_fsave_struct {
285 u32 cwd; /* FPU Control Word */
286 u32 swd; /* FPU Status Word */
287 u32 twd; /* FPU Tag Word */
288 u32 fip; /* FPU IP Offset */
289 u32 fcs; /* FPU IP Selector */
290 u32 foo; /* FPU Operand Pointer Offset */
291 u32 fos; /* FPU Operand Pointer Selector */
292
293 /* 8*10 bytes for each FP-reg = 80 bytes: */
294 u32 st_space[20];
295
296 /* Software status information [not touched by FSAVE ]: */
297 u32 status;
298 };
299
300 struct i387_fxsave_struct {
301 u16 cwd; /* Control Word */
302 u16 swd; /* Status Word */
303 u16 twd; /* Tag Word */
304 u16 fop; /* Last Instruction Opcode */
305 union {
306 struct {
307 u64 rip; /* Instruction Pointer */
308 u64 rdp; /* Data Pointer */
309 };
310 struct {
311 u32 fip; /* FPU IP Offset */
312 u32 fcs; /* FPU IP Selector */
313 u32 foo; /* FPU Operand Offset */
314 u32 fos; /* FPU Operand Selector */
315 };
316 };
317 u32 mxcsr; /* MXCSR Register State */
318 u32 mxcsr_mask; /* MXCSR Mask */
319
320 /* 8*16 bytes for each FP-reg = 128 bytes: */
321 u32 st_space[32];
322
323 /* 16*16 bytes for each XMM-reg = 256 bytes: */
324 u32 xmm_space[64];
325
326 u32 padding[12];
327
328 union {
329 u32 padding1[12];
330 u32 sw_reserved[12];
331 };
332
333 } __attribute__((aligned(16)));
334
335 struct i387_soft_struct {
336 u32 cwd;
337 u32 swd;
338 u32 twd;
339 u32 fip;
340 u32 fcs;
341 u32 foo;
342 u32 fos;
343 /* 8*10 bytes for each FP-reg = 80 bytes: */
344 u32 st_space[20];
345 u8 ftop;
346 u8 changed;
347 u8 lookahead;
348 u8 no_update;
349 u8 rm;
350 u8 alimit;
351 struct math_emu_info *info;
352 u32 entry_eip;
353 };
354
355 struct ymmh_struct {
356 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
357 u32 ymmh_space[64];
358 };
359
360 struct xsave_hdr_struct {
361 u64 xstate_bv;
362 u64 reserved1[2];
363 u64 reserved2[5];
364 } __attribute__((packed));
365
366 struct xsave_struct {
367 struct i387_fxsave_struct i387;
368 struct xsave_hdr_struct xsave_hdr;
369 struct ymmh_struct ymmh;
370 /* new processor state extensions will go here */
371 } __attribute__ ((packed, aligned (64)));
372
373 union thread_xstate {
374 struct i387_fsave_struct fsave;
375 struct i387_fxsave_struct fxsave;
376 struct i387_soft_struct soft;
377 struct xsave_struct xsave;
378 };
379
380 struct fpu {
381 union thread_xstate *state;
382 };
383
384 #ifdef CONFIG_X86_64
385 DECLARE_PER_CPU(struct orig_ist, orig_ist);
386
387 union irq_stack_union {
388 char irq_stack[IRQ_STACK_SIZE];
389 /*
390 * GCC hardcodes the stack canary as %gs:40. Since the
391 * irq_stack is the object at %gs:0, we reserve the bottom
392 * 48 bytes of the irq stack for the canary.
393 */
394 struct {
395 char gs_base[40];
396 unsigned long stack_canary;
397 };
398 };
399
400 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
401 DECLARE_INIT_PER_CPU(irq_stack_union);
402
403 DECLARE_PER_CPU(char *, irq_stack_ptr);
404 DECLARE_PER_CPU(unsigned int, irq_count);
405 extern unsigned long kernel_eflags;
406 extern asmlinkage void ignore_sysret(void);
407 #else /* X86_64 */
408 #ifdef CONFIG_CC_STACKPROTECTOR
409 /*
410 * Make sure stack canary segment base is cached-aligned:
411 * "For Intel Atom processors, avoid non zero segment base address
412 * that is not aligned to cache line boundary at all cost."
413 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
414 */
415 struct stack_canary {
416 char __pad[20]; /* canary at %gs:20 */
417 unsigned long canary;
418 };
419 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
420 #endif
421 #endif /* X86_64 */
422
423 extern unsigned int xstate_size;
424 extern void free_thread_xstate(struct task_struct *);
425 extern struct kmem_cache *task_xstate_cachep;
426
427 struct perf_event;
428
429 struct thread_struct {
430 /* Cached TLS descriptors: */
431 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
432 unsigned long sp0;
433 unsigned long sp;
434 #ifdef CONFIG_X86_32
435 unsigned long sysenter_cs;
436 #else
437 unsigned long usersp; /* Copy from PDA */
438 unsigned short es;
439 unsigned short ds;
440 unsigned short fsindex;
441 unsigned short gsindex;
442 #endif
443 #ifdef CONFIG_X86_32
444 unsigned long ip;
445 #endif
446 #ifdef CONFIG_X86_64
447 unsigned long fs;
448 #endif
449 unsigned long gs;
450 /* Save middle states of ptrace breakpoints */
451 struct perf_event *ptrace_bps[HBP_NUM];
452 /* Debug status used for traps, single steps, etc... */
453 unsigned long debugreg6;
454 /* Keep track of the exact dr7 value set by the user */
455 unsigned long ptrace_dr7;
456 /* Fault info: */
457 unsigned long cr2;
458 unsigned long trap_no;
459 unsigned long error_code;
460 /* floating point and extended processor state */
461 struct fpu fpu;
462 #ifdef CONFIG_X86_32
463 /* Virtual 86 mode info */
464 struct vm86_struct __user *vm86_info;
465 unsigned long screen_bitmap;
466 unsigned long v86flags;
467 unsigned long v86mask;
468 unsigned long saved_sp0;
469 unsigned int saved_fs;
470 unsigned int saved_gs;
471 #endif
472 /* IO permissions: */
473 unsigned long *io_bitmap_ptr;
474 unsigned long iopl;
475 /* Max allowed port in the bitmap, in bytes: */
476 unsigned io_bitmap_max;
477 };
478
479 static inline unsigned long native_get_debugreg(int regno)
480 {
481 unsigned long val = 0; /* Damn you, gcc! */
482
483 switch (regno) {
484 case 0:
485 asm("mov %%db0, %0" :"=r" (val));
486 break;
487 case 1:
488 asm("mov %%db1, %0" :"=r" (val));
489 break;
490 case 2:
491 asm("mov %%db2, %0" :"=r" (val));
492 break;
493 case 3:
494 asm("mov %%db3, %0" :"=r" (val));
495 break;
496 case 6:
497 asm("mov %%db6, %0" :"=r" (val));
498 break;
499 case 7:
500 asm("mov %%db7, %0" :"=r" (val));
501 break;
502 default:
503 BUG();
504 }
505 return val;
506 }
507
508 static inline void native_set_debugreg(int regno, unsigned long value)
509 {
510 switch (regno) {
511 case 0:
512 asm("mov %0, %%db0" ::"r" (value));
513 break;
514 case 1:
515 asm("mov %0, %%db1" ::"r" (value));
516 break;
517 case 2:
518 asm("mov %0, %%db2" ::"r" (value));
519 break;
520 case 3:
521 asm("mov %0, %%db3" ::"r" (value));
522 break;
523 case 6:
524 asm("mov %0, %%db6" ::"r" (value));
525 break;
526 case 7:
527 asm("mov %0, %%db7" ::"r" (value));
528 break;
529 default:
530 BUG();
531 }
532 }
533
534 /*
535 * Set IOPL bits in EFLAGS from given mask
536 */
537 static inline void native_set_iopl_mask(unsigned mask)
538 {
539 #ifdef CONFIG_X86_32
540 unsigned int reg;
541
542 asm volatile ("pushfl;"
543 "popl %0;"
544 "andl %1, %0;"
545 "orl %2, %0;"
546 "pushl %0;"
547 "popfl"
548 : "=&r" (reg)
549 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
550 #endif
551 }
552
553 static inline void
554 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
555 {
556 tss->x86_tss.sp0 = thread->sp0;
557 #ifdef CONFIG_X86_32
558 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
559 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
560 tss->x86_tss.ss1 = thread->sysenter_cs;
561 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
562 }
563 #endif
564 }
565
566 static inline void native_swapgs(void)
567 {
568 #ifdef CONFIG_X86_64
569 asm volatile("swapgs" ::: "memory");
570 #endif
571 }
572
573 #ifdef CONFIG_PARAVIRT
574 #include <asm/paravirt.h>
575 #else
576 #define __cpuid native_cpuid
577 #define paravirt_enabled() 0
578
579 /*
580 * These special macros can be used to get or set a debugging register
581 */
582 #define get_debugreg(var, register) \
583 (var) = native_get_debugreg(register)
584 #define set_debugreg(value, register) \
585 native_set_debugreg(register, value)
586
587 static inline void load_sp0(struct tss_struct *tss,
588 struct thread_struct *thread)
589 {
590 native_load_sp0(tss, thread);
591 }
592
593 #define set_iopl_mask native_set_iopl_mask
594 #endif /* CONFIG_PARAVIRT */
595
596 /*
597 * Save the cr4 feature set we're using (ie
598 * Pentium 4MB enable and PPro Global page
599 * enable), so that any CPU's that boot up
600 * after us can get the correct flags.
601 */
602 extern unsigned long mmu_cr4_features;
603
604 static inline void set_in_cr4(unsigned long mask)
605 {
606 unsigned long cr4;
607
608 mmu_cr4_features |= mask;
609 cr4 = read_cr4();
610 cr4 |= mask;
611 write_cr4(cr4);
612 }
613
614 static inline void clear_in_cr4(unsigned long mask)
615 {
616 unsigned long cr4;
617
618 mmu_cr4_features &= ~mask;
619 cr4 = read_cr4();
620 cr4 &= ~mask;
621 write_cr4(cr4);
622 }
623
624 typedef struct {
625 unsigned long seg;
626 } mm_segment_t;
627
628
629 /*
630 * create a kernel thread without removing it from tasklists
631 */
632 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
633
634 /* Free all resources held by a thread. */
635 extern void release_thread(struct task_struct *);
636
637 /* Prepare to copy thread state - unlazy all lazy state */
638 extern void prepare_to_copy(struct task_struct *tsk);
639
640 unsigned long get_wchan(struct task_struct *p);
641
642 /*
643 * Generic CPUID function
644 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
645 * resulting in stale register contents being returned.
646 */
647 static inline void cpuid(unsigned int op,
648 unsigned int *eax, unsigned int *ebx,
649 unsigned int *ecx, unsigned int *edx)
650 {
651 *eax = op;
652 *ecx = 0;
653 __cpuid(eax, ebx, ecx, edx);
654 }
655
656 /* Some CPUID calls want 'count' to be placed in ecx */
657 static inline void cpuid_count(unsigned int op, int count,
658 unsigned int *eax, unsigned int *ebx,
659 unsigned int *ecx, unsigned int *edx)
660 {
661 *eax = op;
662 *ecx = count;
663 __cpuid(eax, ebx, ecx, edx);
664 }
665
666 /*
667 * CPUID functions returning a single datum
668 */
669 static inline unsigned int cpuid_eax(unsigned int op)
670 {
671 unsigned int eax, ebx, ecx, edx;
672
673 cpuid(op, &eax, &ebx, &ecx, &edx);
674
675 return eax;
676 }
677
678 static inline unsigned int cpuid_ebx(unsigned int op)
679 {
680 unsigned int eax, ebx, ecx, edx;
681
682 cpuid(op, &eax, &ebx, &ecx, &edx);
683
684 return ebx;
685 }
686
687 static inline unsigned int cpuid_ecx(unsigned int op)
688 {
689 unsigned int eax, ebx, ecx, edx;
690
691 cpuid(op, &eax, &ebx, &ecx, &edx);
692
693 return ecx;
694 }
695
696 static inline unsigned int cpuid_edx(unsigned int op)
697 {
698 unsigned int eax, ebx, ecx, edx;
699
700 cpuid(op, &eax, &ebx, &ecx, &edx);
701
702 return edx;
703 }
704
705 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
706 static inline void rep_nop(void)
707 {
708 asm volatile("rep; nop" ::: "memory");
709 }
710
711 static inline void cpu_relax(void)
712 {
713 rep_nop();
714 }
715
716 /* Stop speculative execution and prefetching of modified code. */
717 static inline void sync_core(void)
718 {
719 int tmp;
720
721 #if defined(CONFIG_M386) || defined(CONFIG_M486)
722 if (boot_cpu_data.x86 < 5)
723 /* There is no speculative execution.
724 * jmp is a barrier to prefetching. */
725 asm volatile("jmp 1f\n1:\n" ::: "memory");
726 else
727 #endif
728 /* cpuid is a barrier to speculative execution.
729 * Prefetched instructions are automatically
730 * invalidated when modified. */
731 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
732 : "ebx", "ecx", "edx", "memory");
733 }
734
735 static inline void __monitor(const void *eax, unsigned long ecx,
736 unsigned long edx)
737 {
738 /* "monitor %eax, %ecx, %edx;" */
739 asm volatile(".byte 0x0f, 0x01, 0xc8;"
740 :: "a" (eax), "c" (ecx), "d"(edx));
741 }
742
743 static inline void __mwait(unsigned long eax, unsigned long ecx)
744 {
745 /* "mwait %eax, %ecx;" */
746 asm volatile(".byte 0x0f, 0x01, 0xc9;"
747 :: "a" (eax), "c" (ecx));
748 }
749
750 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
751 {
752 trace_hardirqs_on();
753 /* "mwait %eax, %ecx;" */
754 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
755 :: "a" (eax), "c" (ecx));
756 }
757
758 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
759
760 extern void select_idle_routine(const struct cpuinfo_x86 *c);
761 extern void init_c1e_mask(void);
762
763 extern unsigned long boot_option_idle_override;
764 extern bool c1e_detected;
765
766 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
767 IDLE_POLL, IDLE_FORCE_MWAIT};
768
769 extern void enable_sep_cpu(void);
770 extern int sysenter_setup(void);
771
772 extern void early_trap_init(void);
773
774 /* Defined in head.S */
775 extern struct desc_ptr early_gdt_descr;
776
777 extern void cpu_set_gdt(int);
778 extern void switch_to_new_gdt(int);
779 extern void load_percpu_segment(int);
780 extern void cpu_init(void);
781
782 static inline unsigned long get_debugctlmsr(void)
783 {
784 unsigned long debugctlmsr = 0;
785
786 #ifndef CONFIG_X86_DEBUGCTLMSR
787 if (boot_cpu_data.x86 < 6)
788 return 0;
789 #endif
790 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
791
792 return debugctlmsr;
793 }
794
795 static inline void update_debugctlmsr(unsigned long debugctlmsr)
796 {
797 #ifndef CONFIG_X86_DEBUGCTLMSR
798 if (boot_cpu_data.x86 < 6)
799 return;
800 #endif
801 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
802 }
803
804 /*
805 * from system description table in BIOS. Mostly for MCA use, but
806 * others may find it useful:
807 */
808 extern unsigned int machine_id;
809 extern unsigned int machine_submodel_id;
810 extern unsigned int BIOS_revision;
811
812 /* Boot loader type from the setup header: */
813 extern int bootloader_type;
814 extern int bootloader_version;
815
816 extern char ignore_fpu_irq;
817
818 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
819 #define ARCH_HAS_PREFETCHW
820 #define ARCH_HAS_SPINLOCK_PREFETCH
821
822 #ifdef CONFIG_X86_32
823 # define BASE_PREFETCH ASM_NOP4
824 # define ARCH_HAS_PREFETCH
825 #else
826 # define BASE_PREFETCH "prefetcht0 (%1)"
827 #endif
828
829 /*
830 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
831 *
832 * It's not worth to care about 3dnow prefetches for the K6
833 * because they are microcoded there and very slow.
834 */
835 static inline void prefetch(const void *x)
836 {
837 alternative_input(BASE_PREFETCH,
838 "prefetchnta (%1)",
839 X86_FEATURE_XMM,
840 "r" (x));
841 }
842
843 /*
844 * 3dnow prefetch to get an exclusive cache line.
845 * Useful for spinlocks to avoid one state transition in the
846 * cache coherency protocol:
847 */
848 static inline void prefetchw(const void *x)
849 {
850 alternative_input(BASE_PREFETCH,
851 "prefetchw (%1)",
852 X86_FEATURE_3DNOW,
853 "r" (x));
854 }
855
856 static inline void spin_lock_prefetch(const void *x)
857 {
858 prefetchw(x);
859 }
860
861 #ifdef CONFIG_X86_32
862 /*
863 * User space process size: 3GB (default).
864 */
865 #define TASK_SIZE PAGE_OFFSET
866 #define TASK_SIZE_MAX TASK_SIZE
867 #define STACK_TOP TASK_SIZE
868 #define STACK_TOP_MAX STACK_TOP
869
870 #define INIT_THREAD { \
871 .sp0 = sizeof(init_stack) + (long)&init_stack, \
872 .vm86_info = NULL, \
873 .sysenter_cs = __KERNEL_CS, \
874 .io_bitmap_ptr = NULL, \
875 }
876
877 /*
878 * Note that the .io_bitmap member must be extra-big. This is because
879 * the CPU will access an additional byte beyond the end of the IO
880 * permission bitmap. The extra byte must be all 1 bits, and must
881 * be within the limit.
882 */
883 #define INIT_TSS { \
884 .x86_tss = { \
885 .sp0 = sizeof(init_stack) + (long)&init_stack, \
886 .ss0 = __KERNEL_DS, \
887 .ss1 = __KERNEL_CS, \
888 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
889 }, \
890 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
891 }
892
893 extern unsigned long thread_saved_pc(struct task_struct *tsk);
894
895 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
896 #define KSTK_TOP(info) \
897 ({ \
898 unsigned long *__ptr = (unsigned long *)(info); \
899 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
900 })
901
902 /*
903 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
904 * This is necessary to guarantee that the entire "struct pt_regs"
905 * is accessible even if the CPU haven't stored the SS/ESP registers
906 * on the stack (interrupt gate does not save these registers
907 * when switching to the same priv ring).
908 * Therefore beware: accessing the ss/esp fields of the
909 * "struct pt_regs" is possible, but they may contain the
910 * completely wrong values.
911 */
912 #define task_pt_regs(task) \
913 ({ \
914 struct pt_regs *__regs__; \
915 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
916 __regs__ - 1; \
917 })
918
919 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
920
921 #else
922 /*
923 * User space process size. 47bits minus one guard page.
924 */
925 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
926
927 /* This decides where the kernel will search for a free chunk of vm
928 * space during mmap's.
929 */
930 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
931 0xc0000000 : 0xFFFFe000)
932
933 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
934 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
935 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
936 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
937
938 #define STACK_TOP TASK_SIZE
939 #define STACK_TOP_MAX TASK_SIZE_MAX
940
941 #define INIT_THREAD { \
942 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
943 }
944
945 #define INIT_TSS { \
946 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
947 }
948
949 /*
950 * Return saved PC of a blocked thread.
951 * What is this good for? it will be always the scheduler or ret_from_fork.
952 */
953 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
954
955 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
956 extern unsigned long KSTK_ESP(struct task_struct *task);
957 #endif /* CONFIG_X86_64 */
958
959 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
960 unsigned long new_sp);
961
962 /*
963 * This decides where the kernel will search for a free chunk of vm
964 * space during mmap's.
965 */
966 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
967
968 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
969
970 /* Get/set a process' ability to use the timestamp counter instruction */
971 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
972 #define SET_TSC_CTL(val) set_tsc_mode((val))
973
974 extern int get_tsc_mode(unsigned long adr);
975 extern int set_tsc_mode(unsigned int val);
976
977 extern int amd_get_nb_id(int cpu);
978
979 struct aperfmperf {
980 u64 aperf, mperf;
981 };
982
983 static inline void get_aperfmperf(struct aperfmperf *am)
984 {
985 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
986
987 rdmsrl(MSR_IA32_APERF, am->aperf);
988 rdmsrl(MSR_IA32_MPERF, am->mperf);
989 }
990
991 #define APERFMPERF_SHIFT 10
992
993 static inline
994 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
995 struct aperfmperf *new)
996 {
997 u64 aperf = new->aperf - old->aperf;
998 u64 mperf = new->mperf - old->mperf;
999 unsigned long ratio = aperf;
1000
1001 mperf >>= APERFMPERF_SHIFT;
1002 if (mperf)
1003 ratio = div64_u64(aperf, mperf);
1004
1005 return ratio;
1006 }
1007
1008 /*
1009 * AMD errata checking
1010 */
1011 #ifdef CONFIG_CPU_SUP_AMD
1012 extern const int amd_erratum_383[];
1013 extern const int amd_erratum_400[];
1014 extern bool cpu_has_amd_erratum(const int *);
1015
1016 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1017 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1018 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1019 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1020 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1021 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1022 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1023
1024 #else
1025 #define cpu_has_amd_erratum(x) (false)
1026 #endif /* CONFIG_CPU_SUP_AMD */
1027
1028 #endif /* _ASM_X86_PROCESSOR_H */
Linux with added FPC-III support