x86: Adjust section placement in AMD northbridge related code
[linux/fpc-iii.git] / arch / x86 / include / asm / smpboot_hooks.h
blob6c22bf353f26495b1fa71dc5a92cdaa05e5b1d8e
1 /* two abstractions specific to kernel/smpboot.c, mainly to cater to visws
2 * which needs to alter them. */
4 static inline void smpboot_clear_io_apic_irqs(void)
6 #ifdef CONFIG_X86_IO_APIC
7 io_apic_irqs = 0;
8 #endif
11 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
13 CMOS_WRITE(0xa, 0xf);
14 local_flush_tlb();
15 pr_debug("1.\n");
16 *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_high)) =
17 start_eip >> 4;
18 pr_debug("2.\n");
19 *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_low)) =
20 start_eip & 0xf;
21 pr_debug("3.\n");
24 static inline void smpboot_restore_warm_reset_vector(void)
27 * Install writable page 0 entry to set BIOS data area.
29 local_flush_tlb();
32 * Paranoid: Set warm reset code and vector here back
33 * to default values.
35 CMOS_WRITE(0, 0xf);
37 *((volatile long *)phys_to_virt(apic->trampoline_phys_low)) = 0;
40 static inline void __init smpboot_setup_io_apic(void)
42 #ifdef CONFIG_X86_IO_APIC
44 * Here we can be sure that there is an IO-APIC in the system. Let's
45 * go and set it up:
47 if (!skip_ioapic_setup && nr_ioapics)
48 setup_IO_APIC();
49 else {
50 nr_ioapics = 0;
52 #endif
55 static inline void smpboot_clear_io_apic(void)
57 #ifdef CONFIG_X86_IO_APIC
58 nr_ioapics = 0;
59 #endif