arm: dts: armada-*.dtsi: use SPDX-License-Identifier for most of the Armada SoCs
[linux/fpc-iii.git] / arch / arm / mach-imx / mach-kzm_arm11_01.c
blobab847e2c822a59b78a2db549dd6e257698884f33
1 /*
2 * KZM-ARM11-01 support
3 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
5 * based on code for MX31ADS,
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/gpio.h>
22 #include <linux/init.h>
23 #include <linux/platform_device.h>
24 #include <linux/serial_8250.h>
25 #include <linux/smsc911x.h>
26 #include <linux/types.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/fixed.h>
30 #include <asm/irq.h>
31 #include <asm/mach-types.h>
32 #include <asm/memory.h>
33 #include <asm/setup.h>
34 #include <asm/mach/arch.h>
35 #include <asm/mach/irq.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/time.h>
39 #include "common.h"
40 #include "devices-imx31.h"
41 #include "hardware.h"
42 #include "iomux-mx3.h"
44 #define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
45 IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
46 IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
47 MX31_IO_ADDRESS(x))
50 * KZM-ARM11-01 Board Control Registers on FPGA
52 #define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
53 #define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
54 #define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
55 #define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
56 #define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
57 #define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
58 #define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
59 #define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
62 * External UART for touch panel on FPGA
64 #define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
66 #if IS_ENABLED(CONFIG_SERIAL_8250)
68 * KZM-ARM11-01 has an external UART on FPGA
70 static struct plat_serial8250_port serial_platform_data[] = {
72 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
73 .mapbase = KZM_ARM11_16550,
74 /* irq number is run-time assigned */
75 .irqflags = IRQ_TYPE_EDGE_RISING,
76 .uartclk = 14745600,
77 .regshift = 0,
78 .iotype = UPIO_MEM,
79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
80 UPF_BUGGY_UART,
82 {},
85 static struct resource serial8250_resources[] = {
87 .start = KZM_ARM11_16550,
88 .end = KZM_ARM11_16550 + 0x10,
89 .flags = IORESOURCE_MEM,
92 /* irq number is run-time assigned */
93 .flags = IORESOURCE_IRQ,
97 static struct platform_device serial_device = {
98 .name = "serial8250",
99 .id = PLAT8250_DEV_PLATFORM,
100 .dev = {
101 .platform_data = serial_platform_data,
103 .num_resources = ARRAY_SIZE(serial8250_resources),
104 .resource = serial8250_resources,
107 static int __init kzm_init_ext_uart(void)
109 u8 tmp;
112 * GPIO 1-1: external UART interrupt line
114 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
115 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
116 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
119 * Unmask UART interrupt
121 tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
122 tmp |= 0x2;
123 __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
125 serial_platform_data[0].irq =
126 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
127 serial8250_resources[1].start =
128 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
129 serial8250_resources[1].end =
130 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
132 return platform_device_register(&serial_device);
134 #else
135 static inline int kzm_init_ext_uart(void)
137 return 0;
139 #endif
142 * SMSC LAN9118
144 #if IS_ENABLED(CONFIG_SMSC911X)
145 static struct smsc911x_platform_config kzm_smsc9118_config = {
146 .phy_interface = PHY_INTERFACE_MODE_MII,
147 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
148 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
149 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
152 static struct resource kzm_smsc9118_resources[] = {
154 .start = MX31_CS5_BASE_ADDR,
155 .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
156 .flags = IORESOURCE_MEM,
159 /* irq number is run-time assigned */
160 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
164 static struct platform_device kzm_smsc9118_device = {
165 .name = "smsc911x",
166 .id = -1,
167 .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
168 .resource = kzm_smsc9118_resources,
169 .dev = {
170 .platform_data = &kzm_smsc9118_config,
174 static struct regulator_consumer_supply dummy_supplies[] = {
175 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
176 REGULATOR_SUPPLY("vddvario", "smsc911x"),
179 static int __init kzm_init_smsc9118(void)
182 * GPIO 1-2: SMSC9118 interrupt line
184 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
185 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
186 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
188 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
190 kzm_smsc9118_resources[1].start =
191 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
192 kzm_smsc9118_resources[1].end =
193 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
195 return platform_device_register(&kzm_smsc9118_device);
197 #else
198 static inline int kzm_init_smsc9118(void)
200 return 0;
202 #endif
204 #if IS_ENABLED(CONFIG_SERIAL_IMX)
205 static const struct imxuart_platform_data uart_pdata __initconst = {
206 .flags = IMXUART_HAVE_RTSCTS,
209 static void __init kzm_init_imx_uart(void)
211 imx31_add_imx_uart0(&uart_pdata);
212 imx31_add_imx_uart1(&uart_pdata);
214 #else
215 static inline void kzm_init_imx_uart(void)
218 #endif
220 static int kzm_pins[] __initdata = {
221 MX31_PIN_CTS1__CTS1,
222 MX31_PIN_RTS1__RTS1,
223 MX31_PIN_TXD1__TXD1,
224 MX31_PIN_RXD1__RXD1,
225 MX31_PIN_DCD_DCE1__DCD_DCE1,
226 MX31_PIN_RI_DCE1__RI_DCE1,
227 MX31_PIN_DSR_DCE1__DSR_DCE1,
228 MX31_PIN_DTR_DCE1__DTR_DCE1,
229 MX31_PIN_CTS2__CTS2,
230 MX31_PIN_RTS2__RTS2,
231 MX31_PIN_TXD2__TXD2,
232 MX31_PIN_RXD2__RXD2,
233 MX31_PIN_DCD_DTE1__DCD_DTE2,
234 MX31_PIN_RI_DTE1__RI_DTE2,
235 MX31_PIN_DSR_DTE1__DSR_DTE2,
236 MX31_PIN_DTR_DTE1__DTR_DTE2,
240 * Board specific initialization.
242 static void __init kzm_board_init(void)
244 imx31_soc_init();
246 mxc_iomux_setup_multiple_pins(kzm_pins,
247 ARRAY_SIZE(kzm_pins), "kzm");
248 kzm_init_imx_uart();
250 pr_info("Clock input source is 26MHz\n");
253 static void __init kzm_late_init(void)
255 kzm_init_ext_uart();
256 kzm_init_smsc9118();
260 * This structure defines static mappings for the kzm-arm11-01 board.
262 static struct map_desc kzm_io_desc[] __initdata = {
264 .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
265 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
266 .length = MX31_CS4_SIZE,
267 .type = MT_DEVICE
270 .virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
271 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
272 .length = MX31_CS5_SIZE,
273 .type = MT_DEVICE
278 * Set up static virtual mappings.
280 static void __init kzm_map_io(void)
282 mx31_map_io();
283 iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
286 static void __init kzm_timer_init(void)
288 mx31_clocks_init(26000000);
291 MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
292 .atag_offset = 0x100,
293 .map_io = kzm_map_io,
294 .init_early = imx31_init_early,
295 .init_irq = mx31_init_irq,
296 .init_time = kzm_timer_init,
297 .init_machine = kzm_board_init,
298 .init_late = kzm_late_init,
299 .restart = mxc_restart,
300 MACHINE_END