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mtd: rawnand: Get rid of chip->ecc_{strength,step}_ds
[linux/fpc-iii.git] / drivers / mtd / nand / raw / atmel / nand-controller.c
blob80d14ba0624582999dc2aaf36a64489c63c04abc
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2017 ATMEL
4 * Copyright 2017 Free Electrons
5 *
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
7 *
8 * Derived from the atmel_nand.c driver which contained the following
9 * copyrights:
10 *
11 * Copyright 2003 Rick Bronson
12 *
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
14 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
15 *
16 * Derived from drivers/mtd/spia.c (removed in v3.8)
17 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)
18 *
19 *
20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
21 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
22 *
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
25 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
26 *
27 * Add Programmable Multibit ECC support for various AT91 SoC
28 * Copyright 2012 ATMEL, Hong Xu
29 *
30 * Add Nand Flash Controller support for SAMA5 SoC
31 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
32 *
33 * A few words about the naming convention in this file. This convention
34 * applies to structure and function names.
35 *
36 * Prefixes:
37 *
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
40 * (at91sam9 and avr32 SoCs)
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
42 * (sama5 SoCs and later)
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
44 * that is available in the HSMC block
45 * - <soc>_nand_: all SoC specific structures/functions
46 */
47
48 #include <linux/clk.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/dmaengine.h>
51 #include <linux/genalloc.h>
52 #include <linux/gpio/consumer.h>
53 #include <linux/interrupt.h>
54 #include <linux/mfd/syscon.h>
55 #include <linux/mfd/syscon/atmel-matrix.h>
56 #include <linux/mfd/syscon/atmel-smc.h>
57 #include <linux/module.h>
58 #include <linux/mtd/rawnand.h>
59 #include <linux/of_address.h>
60 #include <linux/of_irq.h>
61 #include <linux/of_platform.h>
62 #include <linux/iopoll.h>
63 #include <linux/platform_device.h>
64 #include <linux/regmap.h>
65 #include <soc/at91/atmel-sfr.h>
66
67 #include "pmecc.h"
68
69 #define ATMEL_HSMC_NFC_CFG 0x0
70 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
71 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
72 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
73 #define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
74 #define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
75 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
76 #define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
77 #define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
78 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
80
81 #define ATMEL_HSMC_NFC_CTRL 0x4
82 #define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
83 #define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
84
85 #define ATMEL_HSMC_NFC_SR 0x8
86 #define ATMEL_HSMC_NFC_IER 0xc
87 #define ATMEL_HSMC_NFC_IDR 0x10
88 #define ATMEL_HSMC_NFC_IMR 0x14
89 #define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
90 #define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
91 #define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
92 #define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
93 #define ATMEL_HSMC_NFC_SR_WR BIT(11)
94 #define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
95 #define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
96 #define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
97 #define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
98 #define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
99 #define ATMEL_HSMC_NFC_SR_AWB BIT(22)
100 #define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
101 #define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
102 ATMEL_HSMC_NFC_SR_UNDEF | \
103 ATMEL_HSMC_NFC_SR_AWB | \
104 ATMEL_HSMC_NFC_SR_NFCASE)
105 #define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
106
107 #define ATMEL_HSMC_NFC_ADDR 0x18
108 #define ATMEL_HSMC_NFC_BANK 0x1c
109
110 #define ATMEL_NFC_MAX_RB_ID 7
111
112 #define ATMEL_NFC_SRAM_SIZE 0x2400
113
114 #define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
115 #define ATMEL_NFC_VCMD2 BIT(18)
116 #define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
117 #define ATMEL_NFC_CSID(cs) ((cs) << 22)
118 #define ATMEL_NFC_DATAEN BIT(25)
119 #define ATMEL_NFC_NFCWR BIT(26)
120
121 #define ATMEL_NFC_MAX_ADDR_CYCLES 5
122
123 #define ATMEL_NAND_ALE_OFFSET BIT(21)
124 #define ATMEL_NAND_CLE_OFFSET BIT(22)
125
126 #define DEFAULT_TIMEOUT_MS 1000
127 #define MIN_DMA_LEN 128
128
129 static bool atmel_nand_avoid_dma __read_mostly;
130
131 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
132 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
133
134 enum atmel_nand_rb_type {
135 ATMEL_NAND_NO_RB,
136 ATMEL_NAND_NATIVE_RB,
137 ATMEL_NAND_GPIO_RB,
138 };
139
140 struct atmel_nand_rb {
141 enum atmel_nand_rb_type type;
142 union {
143 struct gpio_desc *gpio;
144 int id;
145 };
146 };
147
148 struct atmel_nand_cs {
149 int id;
150 struct atmel_nand_rb rb;
151 struct gpio_desc *csgpio;
152 struct {
153 void __iomem *virt;
154 dma_addr_t dma;
155 } io;
156
157 struct atmel_smc_cs_conf smcconf;
158 };
159
160 struct atmel_nand {
161 struct list_head node;
162 struct device *dev;
163 struct nand_chip base;
164 struct atmel_nand_cs *activecs;
165 struct atmel_pmecc_user *pmecc;
166 struct gpio_desc *cdgpio;
167 int numcs;
168 struct atmel_nand_cs cs[];
169 };
170
171 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
172 {
173 return container_of(chip, struct atmel_nand, base);
174 }
175
176 enum atmel_nfc_data_xfer {
177 ATMEL_NFC_NO_DATA,
178 ATMEL_NFC_READ_DATA,
179 ATMEL_NFC_WRITE_DATA,
180 };
181
182 struct atmel_nfc_op {
183 u8 cs;
184 u8 ncmds;
185 u8 cmds[2];
186 u8 naddrs;
187 u8 addrs[5];
188 enum atmel_nfc_data_xfer data;
189 u32 wait;
190 u32 errors;
191 };
192
193 struct atmel_nand_controller;
194 struct atmel_nand_controller_caps;
195
196 struct atmel_nand_controller_ops {
197 int (*probe)(struct platform_device *pdev,
198 const struct atmel_nand_controller_caps *caps);
199 int (*remove)(struct atmel_nand_controller *nc);
200 void (*nand_init)(struct atmel_nand_controller *nc,
201 struct atmel_nand *nand);
202 int (*ecc_init)(struct nand_chip *chip);
203 int (*setup_data_interface)(struct atmel_nand *nand, int csline,
204 const struct nand_data_interface *conf);
205 };
206
207 struct atmel_nand_controller_caps {
208 bool has_dma;
209 bool legacy_of_bindings;
210 u32 ale_offs;
211 u32 cle_offs;
212 const char *ebi_csa_regmap_name;
213 const struct atmel_nand_controller_ops *ops;
214 };
215
216 struct atmel_nand_controller {
217 struct nand_controller base;
218 const struct atmel_nand_controller_caps *caps;
219 struct device *dev;
220 struct regmap *smc;
221 struct dma_chan *dmac;
222 struct atmel_pmecc *pmecc;
223 struct list_head chips;
224 struct clk *mck;
225 };
226
227 static inline struct atmel_nand_controller *
228 to_nand_controller(struct nand_controller *ctl)
229 {
230 return container_of(ctl, struct atmel_nand_controller, base);
231 }
232
233 struct atmel_smc_nand_ebi_csa_cfg {
234 u32 offs;
235 u32 nfd0_on_d16;
236 };
237
238 struct atmel_smc_nand_controller {
239 struct atmel_nand_controller base;
240 struct regmap *ebi_csa_regmap;
241 struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
242 };
243
244 static inline struct atmel_smc_nand_controller *
245 to_smc_nand_controller(struct nand_controller *ctl)
246 {
247 return container_of(to_nand_controller(ctl),
248 struct atmel_smc_nand_controller, base);
249 }
250
251 struct atmel_hsmc_nand_controller {
252 struct atmel_nand_controller base;
253 struct {
254 struct gen_pool *pool;
255 void __iomem *virt;
256 dma_addr_t dma;
257 } sram;
258 const struct atmel_hsmc_reg_layout *hsmc_layout;
259 struct regmap *io;
260 struct atmel_nfc_op op;
261 struct completion complete;
262 int irq;
263
264 /* Only used when instantiating from legacy DT bindings. */
265 struct clk *clk;
266 };
267
268 static inline struct atmel_hsmc_nand_controller *
269 to_hsmc_nand_controller(struct nand_controller *ctl)
270 {
271 return container_of(to_nand_controller(ctl),
272 struct atmel_hsmc_nand_controller, base);
273 }
274
275 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
276 {
277 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
278 op->wait ^= status & op->wait;
279
280 return !op->wait || op->errors;
281 }
282
283 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
284 {
285 struct atmel_hsmc_nand_controller *nc = data;
286 u32 sr, rcvd;
287 bool done;
288
289 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
290
291 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
292 done = atmel_nfc_op_done(&nc->op, sr);
293
294 if (rcvd)
295 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
296
297 if (done)
298 complete(&nc->complete);
299
300 return rcvd ? IRQ_HANDLED : IRQ_NONE;
301 }
302
303 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
304 unsigned int timeout_ms)
305 {
306 int ret;
307
308 if (!timeout_ms)
309 timeout_ms = DEFAULT_TIMEOUT_MS;
310
311 if (poll) {
312 u32 status;
313
314 ret = regmap_read_poll_timeout(nc->base.smc,
315 ATMEL_HSMC_NFC_SR, status,
316 atmel_nfc_op_done(&nc->op,
317 status),
318 0, timeout_ms * 1000);
319 } else {
320 init_completion(&nc->complete);
321 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
322 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
323 ret = wait_for_completion_timeout(&nc->complete,
324 msecs_to_jiffies(timeout_ms));
325 if (!ret)
326 ret = -ETIMEDOUT;
327 else
328 ret = 0;
329
330 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
331 }
332
333 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
334 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
335 ret = -ETIMEDOUT;
336 }
337
338 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
339 dev_err(nc->base.dev, "Access to an undefined area\n");
340 ret = -EIO;
341 }
342
343 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
344 dev_err(nc->base.dev, "Access while busy\n");
345 ret = -EIO;
346 }
347
348 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
349 dev_err(nc->base.dev, "Wrong access size\n");
350 ret = -EIO;
351 }
352
353 return ret;
354 }
355
356 static void atmel_nand_dma_transfer_finished(void *data)
357 {
358 struct completion *finished = data;
359
360 complete(finished);
361 }
362
363 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
364 void *buf, dma_addr_t dev_dma, size_t len,
365 enum dma_data_direction dir)
366 {
367 DECLARE_COMPLETION_ONSTACK(finished);
368 dma_addr_t src_dma, dst_dma, buf_dma;
369 struct dma_async_tx_descriptor *tx;
370 dma_cookie_t cookie;
371
372 buf_dma = dma_map_single(nc->dev, buf, len, dir);
373 if (dma_mapping_error(nc->dev, dev_dma)) {
374 dev_err(nc->dev,
375 "Failed to prepare a buffer for DMA access\n");
376 goto err;
377 }
378
379 if (dir == DMA_FROM_DEVICE) {
380 src_dma = dev_dma;
381 dst_dma = buf_dma;
382 } else {
383 src_dma = buf_dma;
384 dst_dma = dev_dma;
385 }
386
387 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
388 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
389 if (!tx) {
390 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
391 goto err_unmap;
392 }
393
394 tx->callback = atmel_nand_dma_transfer_finished;
395 tx->callback_param = &finished;
396
397 cookie = dmaengine_submit(tx);
398 if (dma_submit_error(cookie)) {
399 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
400 goto err_unmap;
401 }
402
403 dma_async_issue_pending(nc->dmac);
404 wait_for_completion(&finished);
405
406 return 0;
407
408 err_unmap:
409 dma_unmap_single(nc->dev, buf_dma, len, dir);
410
411 err:
412 dev_dbg(nc->dev, "Fall back to CPU I/O\n");
413
414 return -EIO;
415 }
416
417 static u8 atmel_nand_read_byte(struct nand_chip *chip)
418 {
419 struct atmel_nand *nand = to_atmel_nand(chip);
420
421 return ioread8(nand->activecs->io.virt);
422 }
423
424 static void atmel_nand_write_byte(struct nand_chip *chip, u8 byte)
425 {
426 struct atmel_nand *nand = to_atmel_nand(chip);
427
428 if (chip->options & NAND_BUSWIDTH_16)
429 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
430 else
431 iowrite8(byte, nand->activecs->io.virt);
432 }
433
434 static void atmel_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
435 {
436 struct atmel_nand *nand = to_atmel_nand(chip);
437 struct atmel_nand_controller *nc;
438
439 nc = to_nand_controller(chip->controller);
440
441 /*
442 * If the controller supports DMA, the buffer address is DMA-able and
443 * len is long enough to make DMA transfers profitable, let's trigger
444 * a DMA transfer. If it fails, fallback to PIO mode.
445 */
446 if (nc->dmac && virt_addr_valid(buf) &&
447 len >= MIN_DMA_LEN &&
448 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
449 DMA_FROM_DEVICE))
450 return;
451
452 if (chip->options & NAND_BUSWIDTH_16)
453 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
454 else
455 ioread8_rep(nand->activecs->io.virt, buf, len);
456 }
457
458 static void atmel_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
459 {
460 struct atmel_nand *nand = to_atmel_nand(chip);
461 struct atmel_nand_controller *nc;
462
463 nc = to_nand_controller(chip->controller);
464
465 /*
466 * If the controller supports DMA, the buffer address is DMA-able and
467 * len is long enough to make DMA transfers profitable, let's trigger
468 * a DMA transfer. If it fails, fallback to PIO mode.
469 */
470 if (nc->dmac && virt_addr_valid(buf) &&
471 len >= MIN_DMA_LEN &&
472 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
473 len, DMA_TO_DEVICE))
474 return;
475
476 if (chip->options & NAND_BUSWIDTH_16)
477 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
478 else
479 iowrite8_rep(nand->activecs->io.virt, buf, len);
480 }
481
482 static int atmel_nand_dev_ready(struct nand_chip *chip)
483 {
484 struct atmel_nand *nand = to_atmel_nand(chip);
485
486 return gpiod_get_value(nand->activecs->rb.gpio);
487 }
488
489 static void atmel_nand_select_chip(struct nand_chip *chip, int cs)
490 {
491 struct atmel_nand *nand = to_atmel_nand(chip);
492
493 if (cs < 0 || cs >= nand->numcs) {
494 nand->activecs = NULL;
495 chip->legacy.dev_ready = NULL;
496 return;
497 }
498
499 nand->activecs = &nand->cs[cs];
500
501 if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
502 chip->legacy.dev_ready = atmel_nand_dev_ready;
503 }
504
505 static int atmel_hsmc_nand_dev_ready(struct nand_chip *chip)
506 {
507 struct atmel_nand *nand = to_atmel_nand(chip);
508 struct atmel_hsmc_nand_controller *nc;
509 u32 status;
510
511 nc = to_hsmc_nand_controller(chip->controller);
512
513 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
514
515 return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
516 }
517
518 static void atmel_hsmc_nand_select_chip(struct nand_chip *chip, int cs)
519 {
520 struct mtd_info *mtd = nand_to_mtd(chip);
521 struct atmel_nand *nand = to_atmel_nand(chip);
522 struct atmel_hsmc_nand_controller *nc;
523
524 nc = to_hsmc_nand_controller(chip->controller);
525
526 atmel_nand_select_chip(chip, cs);
527
528 if (!nand->activecs) {
529 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
530 ATMEL_HSMC_NFC_CTRL_DIS);
531 return;
532 }
533
534 if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
535 chip->legacy.dev_ready = atmel_hsmc_nand_dev_ready;
536
537 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
538 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
539 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
540 ATMEL_HSMC_NFC_CFG_RSPARE |
541 ATMEL_HSMC_NFC_CFG_WSPARE,
542 ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
543 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
544 ATMEL_HSMC_NFC_CFG_RSPARE);
545 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
546 ATMEL_HSMC_NFC_CTRL_EN);
547 }
548
549 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
550 {
551 u8 *addrs = nc->op.addrs;
552 unsigned int op = 0;
553 u32 addr, val;
554 int i, ret;
555
556 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
557
558 for (i = 0; i < nc->op.ncmds; i++)
559 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
560
561 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
562 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
563
564 op |= ATMEL_NFC_CSID(nc->op.cs) |
565 ATMEL_NFC_ACYCLE(nc->op.naddrs);
566
567 if (nc->op.ncmds > 1)
568 op |= ATMEL_NFC_VCMD2;
569
570 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
571 (addrs[3] << 24);
572
573 if (nc->op.data != ATMEL_NFC_NO_DATA) {
574 op |= ATMEL_NFC_DATAEN;
575 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
576
577 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
578 op |= ATMEL_NFC_NFCWR;
579 }
580
581 /* Clear all flags. */
582 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
583
584 /* Send the command. */
585 regmap_write(nc->io, op, addr);
586
587 ret = atmel_nfc_wait(nc, poll, 0);
588 if (ret)
589 dev_err(nc->base.dev,
590 "Failed to send NAND command (err = %d)!",
591 ret);
592
593 /* Reset the op state. */
594 memset(&nc->op, 0, sizeof(nc->op));
595
596 return ret;
597 }
598
599 static void atmel_hsmc_nand_cmd_ctrl(struct nand_chip *chip, int dat,
600 unsigned int ctrl)
601 {
602 struct atmel_nand *nand = to_atmel_nand(chip);
603 struct atmel_hsmc_nand_controller *nc;
604
605 nc = to_hsmc_nand_controller(chip->controller);
606
607 if (ctrl & NAND_ALE) {
608 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
609 return;
610
611 nc->op.addrs[nc->op.naddrs++] = dat;
612 } else if (ctrl & NAND_CLE) {
613 if (nc->op.ncmds > 1)
614 return;
615
616 nc->op.cmds[nc->op.ncmds++] = dat;
617 }
618
619 if (dat == NAND_CMD_NONE) {
620 nc->op.cs = nand->activecs->id;
621 atmel_nfc_exec_op(nc, true);
622 }
623 }
624
625 static void atmel_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
626 unsigned int ctrl)
627 {
628 struct atmel_nand *nand = to_atmel_nand(chip);
629 struct atmel_nand_controller *nc;
630
631 nc = to_nand_controller(chip->controller);
632
633 if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
634 if (ctrl & NAND_NCE)
635 gpiod_set_value(nand->activecs->csgpio, 0);
636 else
637 gpiod_set_value(nand->activecs->csgpio, 1);
638 }
639
640 if (ctrl & NAND_ALE)
641 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
642 else if (ctrl & NAND_CLE)
643 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
644 }
645
646 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
647 bool oob_required)
648 {
649 struct mtd_info *mtd = nand_to_mtd(chip);
650 struct atmel_hsmc_nand_controller *nc;
651 int ret = -EIO;
652
653 nc = to_hsmc_nand_controller(chip->controller);
654
655 if (nc->base.dmac)
656 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
657 nc->sram.dma, mtd->writesize,
658 DMA_TO_DEVICE);
659
660 /* Falling back to CPU copy. */
661 if (ret)
662 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
663
664 if (oob_required)
665 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
666 mtd->oobsize);
667 }
668
669 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
670 bool oob_required)
671 {
672 struct mtd_info *mtd = nand_to_mtd(chip);
673 struct atmel_hsmc_nand_controller *nc;
674 int ret = -EIO;
675
676 nc = to_hsmc_nand_controller(chip->controller);
677
678 if (nc->base.dmac)
679 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
680 mtd->writesize, DMA_FROM_DEVICE);
681
682 /* Falling back to CPU copy. */
683 if (ret)
684 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
685
686 if (oob_required)
687 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
688 mtd->oobsize);
689 }
690
691 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
692 {
693 struct mtd_info *mtd = nand_to_mtd(chip);
694 struct atmel_hsmc_nand_controller *nc;
695
696 nc = to_hsmc_nand_controller(chip->controller);
697
698 if (column >= 0) {
699 nc->op.addrs[nc->op.naddrs++] = column;
700
701 /*
702 * 2 address cycles for the column offset on large page NANDs.
703 */
704 if (mtd->writesize > 512)
705 nc->op.addrs[nc->op.naddrs++] = column >> 8;
706 }
707
708 if (page >= 0) {
709 nc->op.addrs[nc->op.naddrs++] = page;
710 nc->op.addrs[nc->op.naddrs++] = page >> 8;
711
712 if (chip->options & NAND_ROW_ADDR_3)
713 nc->op.addrs[nc->op.naddrs++] = page >> 16;
714 }
715 }
716
717 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
718 {
719 struct atmel_nand *nand = to_atmel_nand(chip);
720 struct atmel_nand_controller *nc;
721 int ret;
722
723 nc = to_nand_controller(chip->controller);
724
725 if (raw)
726 return 0;
727
728 ret = atmel_pmecc_enable(nand->pmecc, op);
729 if (ret)
730 dev_err(nc->dev,
731 "Failed to enable ECC engine (err = %d)\n", ret);
732
733 return ret;
734 }
735
736 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
737 {
738 struct atmel_nand *nand = to_atmel_nand(chip);
739
740 if (!raw)
741 atmel_pmecc_disable(nand->pmecc);
742 }
743
744 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
745 {
746 struct atmel_nand *nand = to_atmel_nand(chip);
747 struct mtd_info *mtd = nand_to_mtd(chip);
748 struct atmel_nand_controller *nc;
749 struct mtd_oob_region oobregion;
750 void *eccbuf;
751 int ret, i;
752
753 nc = to_nand_controller(chip->controller);
754
755 if (raw)
756 return 0;
757
758 ret = atmel_pmecc_wait_rdy(nand->pmecc);
759 if (ret) {
760 dev_err(nc->dev,
761 "Failed to transfer NAND page data (err = %d)\n",
762 ret);
763 return ret;
764 }
765
766 mtd_ooblayout_ecc(mtd, 0, &oobregion);
767 eccbuf = chip->oob_poi + oobregion.offset;
768
769 for (i = 0; i < chip->ecc.steps; i++) {
770 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
771 eccbuf);
772 eccbuf += chip->ecc.bytes;
773 }
774
775 return 0;
776 }
777
778 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
779 bool raw)
780 {
781 struct atmel_nand *nand = to_atmel_nand(chip);
782 struct mtd_info *mtd = nand_to_mtd(chip);
783 struct atmel_nand_controller *nc;
784 struct mtd_oob_region oobregion;
785 int ret, i, max_bitflips = 0;
786 void *databuf, *eccbuf;
787
788 nc = to_nand_controller(chip->controller);
789
790 if (raw)
791 return 0;
792
793 ret = atmel_pmecc_wait_rdy(nand->pmecc);
794 if (ret) {
795 dev_err(nc->dev,
796 "Failed to read NAND page data (err = %d)\n",
797 ret);
798 return ret;
799 }
800
801 mtd_ooblayout_ecc(mtd, 0, &oobregion);
802 eccbuf = chip->oob_poi + oobregion.offset;
803 databuf = buf;
804
805 for (i = 0; i < chip->ecc.steps; i++) {
806 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
807 eccbuf);
808 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
809 ret = nand_check_erased_ecc_chunk(databuf,
810 chip->ecc.size,
811 eccbuf,
812 chip->ecc.bytes,
813 NULL, 0,
814 chip->ecc.strength);
815
816 if (ret >= 0)
817 max_bitflips = max(ret, max_bitflips);
818 else
819 mtd->ecc_stats.failed++;
820
821 databuf += chip->ecc.size;
822 eccbuf += chip->ecc.bytes;
823 }
824
825 return max_bitflips;
826 }
827
828 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
829 bool oob_required, int page, bool raw)
830 {
831 struct mtd_info *mtd = nand_to_mtd(chip);
832 struct atmel_nand *nand = to_atmel_nand(chip);
833 int ret;
834
835 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
836
837 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
838 if (ret)
839 return ret;
840
841 atmel_nand_write_buf(chip, buf, mtd->writesize);
842
843 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
844 if (ret) {
845 atmel_pmecc_disable(nand->pmecc);
846 return ret;
847 }
848
849 atmel_nand_pmecc_disable(chip, raw);
850
851 atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
852
853 return nand_prog_page_end_op(chip);
854 }
855
856 static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
857 int oob_required, int page)
858 {
859 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
860 }
861
862 static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
863 const u8 *buf, int oob_required,
864 int page)
865 {
866 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
867 }
868
869 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
870 bool oob_required, int page, bool raw)
871 {
872 struct mtd_info *mtd = nand_to_mtd(chip);
873 int ret;
874
875 nand_read_page_op(chip, page, 0, NULL, 0);
876
877 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
878 if (ret)
879 return ret;
880
881 atmel_nand_read_buf(chip, buf, mtd->writesize);
882 atmel_nand_read_buf(chip, chip->oob_poi, mtd->oobsize);
883
884 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
885
886 atmel_nand_pmecc_disable(chip, raw);
887
888 return ret;
889 }
890
891 static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
892 int oob_required, int page)
893 {
894 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
895 }
896
897 static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
898 int oob_required, int page)
899 {
900 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
901 }
902
903 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
904 const u8 *buf, bool oob_required,
905 int page, bool raw)
906 {
907 struct mtd_info *mtd = nand_to_mtd(chip);
908 struct atmel_nand *nand = to_atmel_nand(chip);
909 struct atmel_hsmc_nand_controller *nc;
910 int ret, status;
911
912 nc = to_hsmc_nand_controller(chip->controller);
913
914 atmel_nfc_copy_to_sram(chip, buf, false);
915
916 nc->op.cmds[0] = NAND_CMD_SEQIN;
917 nc->op.ncmds = 1;
918 atmel_nfc_set_op_addr(chip, page, 0x0);
919 nc->op.cs = nand->activecs->id;
920 nc->op.data = ATMEL_NFC_WRITE_DATA;
921
922 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
923 if (ret)
924 return ret;
925
926 ret = atmel_nfc_exec_op(nc, false);
927 if (ret) {
928 atmel_nand_pmecc_disable(chip, raw);
929 dev_err(nc->base.dev,
930 "Failed to transfer NAND page data (err = %d)\n",
931 ret);
932 return ret;
933 }
934
935 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
936
937 atmel_nand_pmecc_disable(chip, raw);
938
939 if (ret)
940 return ret;
941
942 atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
943
944 nc->op.cmds[0] = NAND_CMD_PAGEPROG;
945 nc->op.ncmds = 1;
946 nc->op.cs = nand->activecs->id;
947 ret = atmel_nfc_exec_op(nc, false);
948 if (ret)
949 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
950 ret);
951
952 status = chip->legacy.waitfunc(chip);
953 if (status & NAND_STATUS_FAIL)
954 return -EIO;
955
956 return ret;
957 }
958
959 static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
960 const u8 *buf, int oob_required,
961 int page)
962 {
963 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
964 false);
965 }
966
967 static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
968 const u8 *buf,
969 int oob_required, int page)
970 {
971 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
972 true);
973 }
974
975 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
976 bool oob_required, int page,
977 bool raw)
978 {
979 struct mtd_info *mtd = nand_to_mtd(chip);
980 struct atmel_nand *nand = to_atmel_nand(chip);
981 struct atmel_hsmc_nand_controller *nc;
982 int ret;
983
984 nc = to_hsmc_nand_controller(chip->controller);
985
986 /*
987 * Optimized read page accessors only work when the NAND R/B pin is
988 * connected to a native SoC R/B pin. If that's not the case, fallback
989 * to the non-optimized one.
990 */
991 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
992 nand_read_page_op(chip, page, 0, NULL, 0);
993
994 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
995 raw);
996 }
997
998 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
999
1000 if (mtd->writesize > 512)
1001 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1002
1003 atmel_nfc_set_op_addr(chip, page, 0x0);
1004 nc->op.cs = nand->activecs->id;
1005 nc->op.data = ATMEL_NFC_READ_DATA;
1006
1007 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1008 if (ret)
1009 return ret;
1010
1011 ret = atmel_nfc_exec_op(nc, false);
1012 if (ret) {
1013 atmel_nand_pmecc_disable(chip, raw);
1014 dev_err(nc->base.dev,
1015 "Failed to load NAND page data (err = %d)\n",
1016 ret);
1017 return ret;
1018 }
1019
1020 atmel_nfc_copy_from_sram(chip, buf, true);
1021
1022 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1023
1024 atmel_nand_pmecc_disable(chip, raw);
1025
1026 return ret;
1027 }
1028
1029 static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
1030 int oob_required, int page)
1031 {
1032 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1033 false);
1034 }
1035
1036 static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
1037 u8 *buf, int oob_required,
1038 int page)
1039 {
1040 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1041 true);
1042 }
1043
1044 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1045 {
1046 struct mtd_info *mtd = nand_to_mtd(chip);
1047 struct atmel_nand *nand = to_atmel_nand(chip);
1048 struct atmel_nand_controller *nc;
1049 struct atmel_pmecc_user_req req;
1050
1051 nc = to_nand_controller(chip->controller);
1052
1053 if (!nc->pmecc) {
1054 dev_err(nc->dev, "HW ECC not supported\n");
1055 return -ENOTSUPP;
1056 }
1057
1058 if (nc->caps->legacy_of_bindings) {
1059 u32 val;
1060
1061 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1062 &val))
1063 chip->ecc.strength = val;
1064
1065 if (!of_property_read_u32(nc->dev->of_node,
1066 "atmel,pmecc-sector-size",
1067 &val))
1068 chip->ecc.size = val;
1069 }
1070
1071 if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1072 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1073 else if (chip->ecc.strength)
1074 req.ecc.strength = chip->ecc.strength;
1075 else if (chip->base.eccreq.strength)
1076 req.ecc.strength = chip->base.eccreq.strength;
1077 else
1078 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1079
1080 if (chip->ecc.size)
1081 req.ecc.sectorsize = chip->ecc.size;
1082 else if (chip->base.eccreq.step_size)
1083 req.ecc.sectorsize = chip->base.eccreq.step_size;
1084 else
1085 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1086
1087 req.pagesize = mtd->writesize;
1088 req.oobsize = mtd->oobsize;
1089
1090 if (mtd->writesize <= 512) {
1091 req.ecc.bytes = 4;
1092 req.ecc.ooboffset = 0;
1093 } else {
1094 req.ecc.bytes = mtd->oobsize - 2;
1095 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1096 }
1097
1098 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1099 if (IS_ERR(nand->pmecc))
1100 return PTR_ERR(nand->pmecc);
1101
1102 chip->ecc.algo = NAND_ECC_BCH;
1103 chip->ecc.size = req.ecc.sectorsize;
1104 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1105 chip->ecc.strength = req.ecc.strength;
1106
1107 chip->options |= NAND_NO_SUBPAGE_WRITE;
1108
1109 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1110
1111 return 0;
1112 }
1113
1114 static int atmel_nand_ecc_init(struct nand_chip *chip)
1115 {
1116 struct atmel_nand_controller *nc;
1117 int ret;
1118
1119 nc = to_nand_controller(chip->controller);
1120
1121 switch (chip->ecc.mode) {
1122 case NAND_ECC_NONE:
1123 case NAND_ECC_SOFT:
1124 /*
1125 * Nothing to do, the core will initialize everything for us.
1126 */
1127 break;
1128
1129 case NAND_ECC_HW:
1130 ret = atmel_nand_pmecc_init(chip);
1131 if (ret)
1132 return ret;
1133
1134 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1135 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1136 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1137 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1138 break;
1139
1140 default:
1141 /* Other modes are not supported. */
1142 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1143 chip->ecc.mode);
1144 return -ENOTSUPP;
1145 }
1146
1147 return 0;
1148 }
1149
1150 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1151 {
1152 int ret;
1153
1154 ret = atmel_nand_ecc_init(chip);
1155 if (ret)
1156 return ret;
1157
1158 if (chip->ecc.mode != NAND_ECC_HW)
1159 return 0;
1160
1161 /* Adjust the ECC operations for the HSMC IP. */
1162 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1163 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1164 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1165 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1166
1167 return 0;
1168 }
1169
1170 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1171 const struct nand_data_interface *conf,
1172 struct atmel_smc_cs_conf *smcconf)
1173 {
1174 u32 ncycles, totalcycles, timeps, mckperiodps;
1175 struct atmel_nand_controller *nc;
1176 int ret;
1177
1178 nc = to_nand_controller(nand->base.controller);
1179
1180 /* DDR interface not supported. */
1181 if (conf->type != NAND_SDR_IFACE)
1182 return -ENOTSUPP;
1183
1184 /*
1185 * tRC < 30ns implies EDO mode. This controller does not support this
1186 * mode.
1187 */
1188 if (conf->timings.sdr.tRC_min < 30000)
1189 return -ENOTSUPP;
1190
1191 atmel_smc_cs_conf_init(smcconf);
1192
1193 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1194 mckperiodps *= 1000;
1195
1196 /*
1197 * Set write pulse timing. This one is easy to extract:
1198 *
1199 * NWE_PULSE = tWP
1200 */
1201 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1202 totalcycles = ncycles;
1203 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1204 ncycles);
1205 if (ret)
1206 return ret;
1207
1208 /*
1209 * The write setup timing depends on the operation done on the NAND.
1210 * All operations goes through the same data bus, but the operation
1211 * type depends on the address we are writing to (ALE/CLE address
1212 * lines).
1213 * Since we have no way to differentiate the different operations at
1214 * the SMC level, we must consider the worst case (the biggest setup
1215 * time among all operation types):
1216 *
1217 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1218 */
1219 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1220 conf->timings.sdr.tALS_min);
1221 timeps = max(timeps, conf->timings.sdr.tDS_min);
1222 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1223 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1224 totalcycles += ncycles;
1225 ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1226 ncycles);
1227 if (ret)
1228 return ret;
1229
1230 /*
1231 * As for the write setup timing, the write hold timing depends on the
1232 * operation done on the NAND:
1233 *
1234 * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1235 */
1236 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1237 conf->timings.sdr.tALH_min);
1238 timeps = max3(timeps, conf->timings.sdr.tDH_min,
1239 conf->timings.sdr.tWH_min);
1240 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1241 totalcycles += ncycles;
1242
1243 /*
1244 * The write cycle timing is directly matching tWC, but is also
1245 * dependent on the other timings on the setup and hold timings we
1246 * calculated earlier, which gives:
1247 *
1248 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1249 */
1250 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1251 ncycles = max(totalcycles, ncycles);
1252 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1253 ncycles);
1254 if (ret)
1255 return ret;
1256
1257 /*
1258 * We don't want the CS line to be toggled between each byte/word
1259 * transfer to the NAND. The only way to guarantee that is to have the
1260 * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1261 *
1262 * NCS_WR_PULSE = NWE_CYCLE
1263 */
1264 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1265 ncycles);
1266 if (ret)
1267 return ret;
1268
1269 /*
1270 * As for the write setup timing, the read hold timing depends on the
1271 * operation done on the NAND:
1272 *
1273 * NRD_HOLD = max(tREH, tRHOH)
1274 */
1275 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1276 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1277 totalcycles = ncycles;
1278
1279 /*
1280 * TDF = tRHZ - NRD_HOLD
1281 */
1282 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1283 ncycles -= totalcycles;
1284
1285 /*
1286 * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1287 * we might end up with a config that does not fit in the TDF field.
1288 * Just take the max value in this case and hope that the NAND is more
1289 * tolerant than advertised.
1290 */
1291 if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1292 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1293 else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1294 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1295
1296 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1297 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1298
1299 /*
1300 * Read pulse timing directly matches tRP:
1301 *
1302 * NRD_PULSE = tRP
1303 */
1304 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1305 totalcycles += ncycles;
1306 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1307 ncycles);
1308 if (ret)
1309 return ret;
1310
1311 /*
1312 * The write cycle timing is directly matching tWC, but is also
1313 * dependent on the setup and hold timings we calculated earlier,
1314 * which gives:
1315 *
1316 * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1317 *
1318 * NRD_SETUP is always 0.
1319 */
1320 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1321 ncycles = max(totalcycles, ncycles);
1322 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1323 ncycles);
1324 if (ret)
1325 return ret;
1326
1327 /*
1328 * We don't want the CS line to be toggled between each byte/word
1329 * transfer from the NAND. The only way to guarantee that is to have
1330 * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1331 *
1332 * NCS_RD_PULSE = NRD_CYCLE
1333 */
1334 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1335 ncycles);
1336 if (ret)
1337 return ret;
1338
1339 /* Txxx timings are directly matching tXXX ones. */
1340 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1341 ret = atmel_smc_cs_conf_set_timing(smcconf,
1342 ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1343 ncycles);
1344 if (ret)
1345 return ret;
1346
1347 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1348 ret = atmel_smc_cs_conf_set_timing(smcconf,
1349 ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1350 ncycles);
1351 /*
1352 * Version 4 of the ONFI spec mandates that tADL be at least 400
1353 * nanoseconds, but, depending on the master clock rate, 400 ns may not
1354 * fit in the tADL field of the SMC reg. We need to relax the check and
1355 * accept the -ERANGE return code.
1356 *
1357 * Note that previous versions of the ONFI spec had a lower tADL_min
1358 * (100 or 200 ns). It's not clear why this timing constraint got
1359 * increased but it seems most NANDs are fine with values lower than
1360 * 400ns, so we should be safe.
1361 */
1362 if (ret && ret != -ERANGE)
1363 return ret;
1364
1365 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1366 ret = atmel_smc_cs_conf_set_timing(smcconf,
1367 ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1368 ncycles);
1369 if (ret)
1370 return ret;
1371
1372 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1373 ret = atmel_smc_cs_conf_set_timing(smcconf,
1374 ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1375 ncycles);
1376 if (ret)
1377 return ret;
1378
1379 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1380 ret = atmel_smc_cs_conf_set_timing(smcconf,
1381 ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1382 ncycles);
1383 if (ret)
1384 return ret;
1385
1386 /* Attach the CS line to the NFC logic. */
1387 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1388
1389 /* Set the appropriate data bus width. */
1390 if (nand->base.options & NAND_BUSWIDTH_16)
1391 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1392
1393 /* Operate in NRD/NWE READ/WRITEMODE. */
1394 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1395 ATMEL_SMC_MODE_WRITEMODE_NWE;
1396
1397 return 0;
1398 }
1399
1400 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1401 int csline,
1402 const struct nand_data_interface *conf)
1403 {
1404 struct atmel_nand_controller *nc;
1405 struct atmel_smc_cs_conf smcconf;
1406 struct atmel_nand_cs *cs;
1407 int ret;
1408
1409 nc = to_nand_controller(nand->base.controller);
1410
1411 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1412 if (ret)
1413 return ret;
1414
1415 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1416 return 0;
1417
1418 cs = &nand->cs[csline];
1419 cs->smcconf = smcconf;
1420 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1421
1422 return 0;
1423 }
1424
1425 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1426 int csline,
1427 const struct nand_data_interface *conf)
1428 {
1429 struct atmel_hsmc_nand_controller *nc;
1430 struct atmel_smc_cs_conf smcconf;
1431 struct atmel_nand_cs *cs;
1432 int ret;
1433
1434 nc = to_hsmc_nand_controller(nand->base.controller);
1435
1436 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1437 if (ret)
1438 return ret;
1439
1440 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1441 return 0;
1442
1443 cs = &nand->cs[csline];
1444 cs->smcconf = smcconf;
1445
1446 if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1447 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1448
1449 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1450 &cs->smcconf);
1451
1452 return 0;
1453 }
1454
1455 static int atmel_nand_setup_data_interface(struct nand_chip *chip, int csline,
1456 const struct nand_data_interface *conf)
1457 {
1458 struct atmel_nand *nand = to_atmel_nand(chip);
1459 struct atmel_nand_controller *nc;
1460
1461 nc = to_nand_controller(nand->base.controller);
1462
1463 if (csline >= nand->numcs ||
1464 (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1465 return -EINVAL;
1466
1467 return nc->caps->ops->setup_data_interface(nand, csline, conf);
1468 }
1469
1470 static void atmel_nand_init(struct atmel_nand_controller *nc,
1471 struct atmel_nand *nand)
1472 {
1473 struct nand_chip *chip = &nand->base;
1474 struct mtd_info *mtd = nand_to_mtd(chip);
1475
1476 mtd->dev.parent = nc->dev;
1477 nand->base.controller = &nc->base;
1478
1479 chip->legacy.cmd_ctrl = atmel_nand_cmd_ctrl;
1480 chip->legacy.read_byte = atmel_nand_read_byte;
1481 chip->legacy.write_byte = atmel_nand_write_byte;
1482 chip->legacy.read_buf = atmel_nand_read_buf;
1483 chip->legacy.write_buf = atmel_nand_write_buf;
1484 chip->legacy.select_chip = atmel_nand_select_chip;
1485
1486 if (!nc->mck || !nc->caps->ops->setup_data_interface)
1487 chip->options |= NAND_KEEP_TIMINGS;
1488
1489 /* Some NANDs require a longer delay than the default one (20us). */
1490 chip->legacy.chip_delay = 40;
1491
1492 /*
1493 * Use a bounce buffer when the buffer passed by the MTD user is not
1494 * suitable for DMA.
1495 */
1496 if (nc->dmac)
1497 chip->options |= NAND_USE_BOUNCE_BUFFER;
1498
1499 /* Default to HW ECC if pmecc is available. */
1500 if (nc->pmecc)
1501 chip->ecc.mode = NAND_ECC_HW;
1502 }
1503
1504 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1505 struct atmel_nand *nand)
1506 {
1507 struct nand_chip *chip = &nand->base;
1508 struct atmel_smc_nand_controller *smc_nc;
1509 int i;
1510
1511 atmel_nand_init(nc, nand);
1512
1513 smc_nc = to_smc_nand_controller(chip->controller);
1514 if (!smc_nc->ebi_csa_regmap)
1515 return;
1516
1517 /* Attach the CS to the NAND Flash logic. */
1518 for (i = 0; i < nand->numcs; i++)
1519 regmap_update_bits(smc_nc->ebi_csa_regmap,
1520 smc_nc->ebi_csa->offs,
1521 BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1522
1523 if (smc_nc->ebi_csa->nfd0_on_d16)
1524 regmap_update_bits(smc_nc->ebi_csa_regmap,
1525 smc_nc->ebi_csa->offs,
1526 smc_nc->ebi_csa->nfd0_on_d16,
1527 smc_nc->ebi_csa->nfd0_on_d16);
1528 }
1529
1530 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1531 struct atmel_nand *nand)
1532 {
1533 struct nand_chip *chip = &nand->base;
1534
1535 atmel_nand_init(nc, nand);
1536
1537 /* Overload some methods for the HSMC controller. */
1538 chip->legacy.cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1539 chip->legacy.select_chip = atmel_hsmc_nand_select_chip;
1540 }
1541
1542 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1543 {
1544 struct nand_chip *chip = &nand->base;
1545 struct mtd_info *mtd = nand_to_mtd(chip);
1546 int ret;
1547
1548 ret = mtd_device_unregister(mtd);
1549 if (ret)
1550 return ret;
1551
1552 nand_cleanup(chip);
1553 list_del(&nand->node);
1554
1555 return 0;
1556 }
1557
1558 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1559 struct device_node *np,
1560 int reg_cells)
1561 {
1562 struct atmel_nand *nand;
1563 struct gpio_desc *gpio;
1564 int numcs, ret, i;
1565
1566 numcs = of_property_count_elems_of_size(np, "reg",
1567 reg_cells * sizeof(u32));
1568 if (numcs < 1) {
1569 dev_err(nc->dev, "Missing or invalid reg property\n");
1570 return ERR_PTR(-EINVAL);
1571 }
1572
1573 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
1574 if (!nand) {
1575 dev_err(nc->dev, "Failed to allocate NAND object\n");
1576 return ERR_PTR(-ENOMEM);
1577 }
1578
1579 nand->numcs = numcs;
1580
1581 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1582 &np->fwnode, GPIOD_IN,
1583 "nand-det");
1584 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1585 dev_err(nc->dev,
1586 "Failed to get detect gpio (err = %ld)\n",
1587 PTR_ERR(gpio));
1588 return ERR_CAST(gpio);
1589 }
1590
1591 if (!IS_ERR(gpio))
1592 nand->cdgpio = gpio;
1593
1594 for (i = 0; i < numcs; i++) {
1595 struct resource res;
1596 u32 val;
1597
1598 ret = of_address_to_resource(np, 0, &res);
1599 if (ret) {
1600 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1601 ret);
1602 return ERR_PTR(ret);
1603 }
1604
1605 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1606 &val);
1607 if (ret) {
1608 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1609 ret);
1610 return ERR_PTR(ret);
1611 }
1612
1613 nand->cs[i].id = val;
1614
1615 nand->cs[i].io.dma = res.start;
1616 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1617 if (IS_ERR(nand->cs[i].io.virt))
1618 return ERR_CAST(nand->cs[i].io.virt);
1619
1620 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1621 if (val > ATMEL_NFC_MAX_RB_ID)
1622 return ERR_PTR(-EINVAL);
1623
1624 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1625 nand->cs[i].rb.id = val;
1626 } else {
1627 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1628 "rb", i, &np->fwnode,
1629 GPIOD_IN, "nand-rb");
1630 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1631 dev_err(nc->dev,
1632 "Failed to get R/B gpio (err = %ld)\n",
1633 PTR_ERR(gpio));
1634 return ERR_CAST(gpio);
1635 }
1636
1637 if (!IS_ERR(gpio)) {
1638 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1639 nand->cs[i].rb.gpio = gpio;
1640 }
1641 }
1642
1643 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1644 i, &np->fwnode,
1645 GPIOD_OUT_HIGH,
1646 "nand-cs");
1647 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1648 dev_err(nc->dev,
1649 "Failed to get CS gpio (err = %ld)\n",
1650 PTR_ERR(gpio));
1651 return ERR_CAST(gpio);
1652 }
1653
1654 if (!IS_ERR(gpio))
1655 nand->cs[i].csgpio = gpio;
1656 }
1657
1658 nand_set_flash_node(&nand->base, np);
1659
1660 return nand;
1661 }
1662
1663 static int
1664 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1665 struct atmel_nand *nand)
1666 {
1667 struct nand_chip *chip = &nand->base;
1668 struct mtd_info *mtd = nand_to_mtd(chip);
1669 int ret;
1670
1671 /* No card inserted, skip this NAND. */
1672 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1673 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1674 return 0;
1675 }
1676
1677 nc->caps->ops->nand_init(nc, nand);
1678
1679 ret = nand_scan(chip, nand->numcs);
1680 if (ret) {
1681 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1682 return ret;
1683 }
1684
1685 ret = mtd_device_register(mtd, NULL, 0);
1686 if (ret) {
1687 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1688 nand_cleanup(chip);
1689 return ret;
1690 }
1691
1692 list_add_tail(&nand->node, &nc->chips);
1693
1694 return 0;
1695 }
1696
1697 static int
1698 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1699 {
1700 struct atmel_nand *nand, *tmp;
1701 int ret;
1702
1703 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1704 ret = atmel_nand_controller_remove_nand(nand);
1705 if (ret)
1706 return ret;
1707 }
1708
1709 return 0;
1710 }
1711
1712 static int
1713 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1714 {
1715 struct device *dev = nc->dev;
1716 struct platform_device *pdev = to_platform_device(dev);
1717 struct atmel_nand *nand;
1718 struct gpio_desc *gpio;
1719 struct resource *res;
1720
1721 /*
1722 * Legacy bindings only allow connecting a single NAND with a unique CS
1723 * line to the controller.
1724 */
1725 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1726 GFP_KERNEL);
1727 if (!nand)
1728 return -ENOMEM;
1729
1730 nand->numcs = 1;
1731
1732 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1733 nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1734 if (IS_ERR(nand->cs[0].io.virt))
1735 return PTR_ERR(nand->cs[0].io.virt);
1736
1737 nand->cs[0].io.dma = res->start;
1738
1739 /*
1740 * The old driver was hardcoding the CS id to 3 for all sama5
1741 * controllers. Since this id is only meaningful for the sama5
1742 * controller we can safely assign this id to 3 no matter the
1743 * controller.
1744 * If one wants to connect a NAND to a different CS line, he will
1745 * have to use the new bindings.
1746 */
1747 nand->cs[0].id = 3;
1748
1749 /* R/B GPIO. */
1750 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN);
1751 if (IS_ERR(gpio)) {
1752 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1753 PTR_ERR(gpio));
1754 return PTR_ERR(gpio);
1755 }
1756
1757 if (gpio) {
1758 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1759 nand->cs[0].rb.gpio = gpio;
1760 }
1761
1762 /* CS GPIO. */
1763 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1764 if (IS_ERR(gpio)) {
1765 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1766 PTR_ERR(gpio));
1767 return PTR_ERR(gpio);
1768 }
1769
1770 nand->cs[0].csgpio = gpio;
1771
1772 /* Card detect GPIO. */
1773 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1774 if (IS_ERR(gpio)) {
1775 dev_err(dev,
1776 "Failed to get detect gpio (err = %ld)\n",
1777 PTR_ERR(gpio));
1778 return PTR_ERR(gpio);
1779 }
1780
1781 nand->cdgpio = gpio;
1782
1783 nand_set_flash_node(&nand->base, nc->dev->of_node);
1784
1785 return atmel_nand_controller_add_nand(nc, nand);
1786 }
1787
1788 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1789 {
1790 struct device_node *np, *nand_np;
1791 struct device *dev = nc->dev;
1792 int ret, reg_cells;
1793 u32 val;
1794
1795 /* We do not retrieve the SMC syscon when parsing old DTs. */
1796 if (nc->caps->legacy_of_bindings)
1797 return atmel_nand_controller_legacy_add_nands(nc);
1798
1799 np = dev->of_node;
1800
1801 ret = of_property_read_u32(np, "#address-cells", &val);
1802 if (ret) {
1803 dev_err(dev, "missing #address-cells property\n");
1804 return ret;
1805 }
1806
1807 reg_cells = val;
1808
1809 ret = of_property_read_u32(np, "#size-cells", &val);
1810 if (ret) {
1811 dev_err(dev, "missing #address-cells property\n");
1812 return ret;
1813 }
1814
1815 reg_cells += val;
1816
1817 for_each_child_of_node(np, nand_np) {
1818 struct atmel_nand *nand;
1819
1820 nand = atmel_nand_create(nc, nand_np, reg_cells);
1821 if (IS_ERR(nand)) {
1822 ret = PTR_ERR(nand);
1823 goto err;
1824 }
1825
1826 ret = atmel_nand_controller_add_nand(nc, nand);
1827 if (ret)
1828 goto err;
1829 }
1830
1831 return 0;
1832
1833 err:
1834 atmel_nand_controller_remove_nands(nc);
1835
1836 return ret;
1837 }
1838
1839 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1840 {
1841 if (nc->dmac)
1842 dma_release_channel(nc->dmac);
1843
1844 clk_put(nc->mck);
1845 }
1846
1847 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1848 .offs = AT91SAM9260_MATRIX_EBICSA,
1849 };
1850
1851 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1852 .offs = AT91SAM9261_MATRIX_EBICSA,
1853 };
1854
1855 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1856 .offs = AT91SAM9263_MATRIX_EBI0CSA,
1857 };
1858
1859 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1860 .offs = AT91SAM9RL_MATRIX_EBICSA,
1861 };
1862
1863 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1864 .offs = AT91SAM9G45_MATRIX_EBICSA,
1865 };
1866
1867 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1868 .offs = AT91SAM9N12_MATRIX_EBICSA,
1869 };
1870
1871 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1872 .offs = AT91SAM9X5_MATRIX_EBICSA,
1873 };
1874
1875 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1876 .offs = AT91_SFR_CCFG_EBICSA,
1877 .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1878 };
1879
1880 static const struct of_device_id atmel_ebi_csa_regmap_of_ids[] = {
1881 {
1882 .compatible = "atmel,at91sam9260-matrix",
1883 .data = &at91sam9260_ebi_csa,
1884 },
1885 {
1886 .compatible = "atmel,at91sam9261-matrix",
1887 .data = &at91sam9261_ebi_csa,
1888 },
1889 {
1890 .compatible = "atmel,at91sam9263-matrix",
1891 .data = &at91sam9263_ebi_csa,
1892 },
1893 {
1894 .compatible = "atmel,at91sam9rl-matrix",
1895 .data = &at91sam9rl_ebi_csa,
1896 },
1897 {
1898 .compatible = "atmel,at91sam9g45-matrix",
1899 .data = &at91sam9g45_ebi_csa,
1900 },
1901 {
1902 .compatible = "atmel,at91sam9n12-matrix",
1903 .data = &at91sam9n12_ebi_csa,
1904 },
1905 {
1906 .compatible = "atmel,at91sam9x5-matrix",
1907 .data = &at91sam9x5_ebi_csa,
1908 },
1909 {
1910 .compatible = "microchip,sam9x60-sfr",
1911 .data = &sam9x60_ebi_csa,
1912 },
1913 { /* sentinel */ },
1914 };
1915
1916 static int atmel_nand_attach_chip(struct nand_chip *chip)
1917 {
1918 struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1919 struct atmel_nand *nand = to_atmel_nand(chip);
1920 struct mtd_info *mtd = nand_to_mtd(chip);
1921 int ret;
1922
1923 ret = nc->caps->ops->ecc_init(chip);
1924 if (ret)
1925 return ret;
1926
1927 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1928 /*
1929 * We keep the MTD name unchanged to avoid breaking platforms
1930 * where the MTD cmdline parser is used and the bootloader
1931 * has not been updated to use the new naming scheme.
1932 */
1933 mtd->name = "atmel_nand";
1934 } else if (!mtd->name) {
1935 /*
1936 * If the new bindings are used and the bootloader has not been
1937 * updated to pass a new mtdparts parameter on the cmdline, you
1938 * should define the following property in your nand node:
1939 *
1940 * label = "atmel_nand";
1941 *
1942 * This way, mtd->name will be set by the core when
1943 * nand_set_flash_node() is called.
1944 */
1945 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1946 "%s:nand.%d", dev_name(nc->dev),
1947 nand->cs[0].id);
1948 if (!mtd->name) {
1949 dev_err(nc->dev, "Failed to allocate mtd->name\n");
1950 return -ENOMEM;
1951 }
1952 }
1953
1954 return 0;
1955 }
1956
1957 static const struct nand_controller_ops atmel_nand_controller_ops = {
1958 .attach_chip = atmel_nand_attach_chip,
1959 .setup_data_interface = atmel_nand_setup_data_interface,
1960 };
1961
1962 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1963 struct platform_device *pdev,
1964 const struct atmel_nand_controller_caps *caps)
1965 {
1966 struct device *dev = &pdev->dev;
1967 struct device_node *np = dev->of_node;
1968 int ret;
1969
1970 nand_controller_init(&nc->base);
1971 nc->base.ops = &atmel_nand_controller_ops;
1972 INIT_LIST_HEAD(&nc->chips);
1973 nc->dev = dev;
1974 nc->caps = caps;
1975
1976 platform_set_drvdata(pdev, nc);
1977
1978 nc->pmecc = devm_atmel_pmecc_get(dev);
1979 if (IS_ERR(nc->pmecc)) {
1980 ret = PTR_ERR(nc->pmecc);
1981 if (ret != -EPROBE_DEFER)
1982 dev_err(dev, "Could not get PMECC object (err = %d)\n",
1983 ret);
1984 return ret;
1985 }
1986
1987 if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
1988 dma_cap_mask_t mask;
1989
1990 dma_cap_zero(mask);
1991 dma_cap_set(DMA_MEMCPY, mask);
1992
1993 nc->dmac = dma_request_channel(mask, NULL, NULL);
1994 if (!nc->dmac)
1995 dev_err(nc->dev, "Failed to request DMA channel\n");
1996 }
1997
1998 /* We do not retrieve the SMC syscon when parsing old DTs. */
1999 if (nc->caps->legacy_of_bindings)
2000 return 0;
2001
2002 nc->mck = of_clk_get(dev->parent->of_node, 0);
2003 if (IS_ERR(nc->mck)) {
2004 dev_err(dev, "Failed to retrieve MCK clk\n");
2005 return PTR_ERR(nc->mck);
2006 }
2007
2008 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2009 if (!np) {
2010 dev_err(dev, "Missing or invalid atmel,smc property\n");
2011 return -EINVAL;
2012 }
2013
2014 nc->smc = syscon_node_to_regmap(np);
2015 of_node_put(np);
2016 if (IS_ERR(nc->smc)) {
2017 ret = PTR_ERR(nc->smc);
2018 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2019 return ret;
2020 }
2021
2022 return 0;
2023 }
2024
2025 static int
2026 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2027 {
2028 struct device *dev = nc->base.dev;
2029 const struct of_device_id *match;
2030 struct device_node *np;
2031 int ret;
2032
2033 /* We do not retrieve the EBICSA regmap when parsing old DTs. */
2034 if (nc->base.caps->legacy_of_bindings)
2035 return 0;
2036
2037 np = of_parse_phandle(dev->parent->of_node,
2038 nc->base.caps->ebi_csa_regmap_name, 0);
2039 if (!np)
2040 return 0;
2041
2042 match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);
2043 if (!match) {
2044 of_node_put(np);
2045 return 0;
2046 }
2047
2048 nc->ebi_csa_regmap = syscon_node_to_regmap(np);
2049 of_node_put(np);
2050 if (IS_ERR(nc->ebi_csa_regmap)) {
2051 ret = PTR_ERR(nc->ebi_csa_regmap);
2052 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
2053 return ret;
2054 }
2055
2056 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
2057
2058 /*
2059 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2060 * add 4 to ->ebi_csa->offs.
2061 */
2062 if (of_device_is_compatible(dev->parent->of_node,
2063 "atmel,at91sam9263-ebi1"))
2064 nc->ebi_csa->offs += 4;
2065
2066 return 0;
2067 }
2068
2069 static int
2070 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2071 {
2072 struct regmap_config regmap_conf = {
2073 .reg_bits = 32,
2074 .val_bits = 32,
2075 .reg_stride = 4,
2076 };
2077
2078 struct device *dev = nc->base.dev;
2079 struct device_node *nand_np, *nfc_np;
2080 void __iomem *iomem;
2081 struct resource res;
2082 int ret;
2083
2084 nand_np = dev->of_node;
2085 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2086 if (!nfc_np) {
2087 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2088 return -ENODEV;
2089 }
2090
2091 nc->clk = of_clk_get(nfc_np, 0);
2092 if (IS_ERR(nc->clk)) {
2093 ret = PTR_ERR(nc->clk);
2094 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2095 ret);
2096 goto out;
2097 }
2098
2099 ret = clk_prepare_enable(nc->clk);
2100 if (ret) {
2101 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2102 ret);
2103 goto out;
2104 }
2105
2106 nc->irq = of_irq_get(nand_np, 0);
2107 if (nc->irq <= 0) {
2108 ret = nc->irq ?: -ENXIO;
2109 if (ret != -EPROBE_DEFER)
2110 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2111 ret);
2112 goto out;
2113 }
2114
2115 ret = of_address_to_resource(nfc_np, 0, &res);
2116 if (ret) {
2117 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2118 ret);
2119 goto out;
2120 }
2121
2122 iomem = devm_ioremap_resource(dev, &res);
2123 if (IS_ERR(iomem)) {
2124 ret = PTR_ERR(iomem);
2125 goto out;
2126 }
2127
2128 regmap_conf.name = "nfc-io";
2129 regmap_conf.max_register = resource_size(&res) - 4;
2130 nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2131 if (IS_ERR(nc->io)) {
2132 ret = PTR_ERR(nc->io);
2133 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2134 ret);
2135 goto out;
2136 }
2137
2138 ret = of_address_to_resource(nfc_np, 1, &res);
2139 if (ret) {
2140 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2141 ret);
2142 goto out;
2143 }
2144
2145 iomem = devm_ioremap_resource(dev, &res);
2146 if (IS_ERR(iomem)) {
2147 ret = PTR_ERR(iomem);
2148 goto out;
2149 }
2150
2151 regmap_conf.name = "smc";
2152 regmap_conf.max_register = resource_size(&res) - 4;
2153 nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2154 if (IS_ERR(nc->base.smc)) {
2155 ret = PTR_ERR(nc->base.smc);
2156 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2157 ret);
2158 goto out;
2159 }
2160
2161 ret = of_address_to_resource(nfc_np, 2, &res);
2162 if (ret) {
2163 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2164 ret);
2165 goto out;
2166 }
2167
2168 nc->sram.virt = devm_ioremap_resource(dev, &res);
2169 if (IS_ERR(nc->sram.virt)) {
2170 ret = PTR_ERR(nc->sram.virt);
2171 goto out;
2172 }
2173
2174 nc->sram.dma = res.start;
2175
2176 out:
2177 of_node_put(nfc_np);
2178
2179 return ret;
2180 }
2181
2182 static int
2183 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2184 {
2185 struct device *dev = nc->base.dev;
2186 struct device_node *np;
2187 int ret;
2188
2189 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2190 if (!np) {
2191 dev_err(dev, "Missing or invalid atmel,smc property\n");
2192 return -EINVAL;
2193 }
2194
2195 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2196
2197 nc->irq = of_irq_get(np, 0);
2198 of_node_put(np);
2199 if (nc->irq <= 0) {
2200 ret = nc->irq ?: -ENXIO;
2201 if (ret != -EPROBE_DEFER)
2202 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2203 ret);
2204 return ret;
2205 }
2206
2207 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2208 if (!np) {
2209 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2210 return -EINVAL;
2211 }
2212
2213 nc->io = syscon_node_to_regmap(np);
2214 of_node_put(np);
2215 if (IS_ERR(nc->io)) {
2216 ret = PTR_ERR(nc->io);
2217 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2218 return ret;
2219 }
2220
2221 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2222 "atmel,nfc-sram", 0);
2223 if (!nc->sram.pool) {
2224 dev_err(nc->base.dev, "Missing SRAM\n");
2225 return -ENOMEM;
2226 }
2227
2228 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2229 ATMEL_NFC_SRAM_SIZE,
2230 &nc->sram.dma);
2231 if (!nc->sram.virt) {
2232 dev_err(nc->base.dev,
2233 "Could not allocate memory from the NFC SRAM pool\n");
2234 return -ENOMEM;
2235 }
2236
2237 return 0;
2238 }
2239
2240 static int
2241 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2242 {
2243 struct atmel_hsmc_nand_controller *hsmc_nc;
2244 int ret;
2245
2246 ret = atmel_nand_controller_remove_nands(nc);
2247 if (ret)
2248 return ret;
2249
2250 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2251 if (hsmc_nc->sram.pool)
2252 gen_pool_free(hsmc_nc->sram.pool,
2253 (unsigned long)hsmc_nc->sram.virt,
2254 ATMEL_NFC_SRAM_SIZE);
2255
2256 if (hsmc_nc->clk) {
2257 clk_disable_unprepare(hsmc_nc->clk);
2258 clk_put(hsmc_nc->clk);
2259 }
2260
2261 atmel_nand_controller_cleanup(nc);
2262
2263 return 0;
2264 }
2265
2266 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2267 const struct atmel_nand_controller_caps *caps)
2268 {
2269 struct device *dev = &pdev->dev;
2270 struct atmel_hsmc_nand_controller *nc;
2271 int ret;
2272
2273 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2274 if (!nc)
2275 return -ENOMEM;
2276
2277 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2278 if (ret)
2279 return ret;
2280
2281 if (caps->legacy_of_bindings)
2282 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2283 else
2284 ret = atmel_hsmc_nand_controller_init(nc);
2285
2286 if (ret)
2287 return ret;
2288
2289 /* Make sure all irqs are masked before registering our IRQ handler. */
2290 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2291 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2292 IRQF_SHARED, "nfc", nc);
2293 if (ret) {
2294 dev_err(dev,
2295 "Could not get register NFC interrupt handler (err = %d)\n",
2296 ret);
2297 goto err;
2298 }
2299
2300 /* Initial NFC configuration. */
2301 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2302 ATMEL_HSMC_NFC_CFG_DTO_MAX);
2303
2304 ret = atmel_nand_controller_add_nands(&nc->base);
2305 if (ret)
2306 goto err;
2307
2308 return 0;
2309
2310 err:
2311 atmel_hsmc_nand_controller_remove(&nc->base);
2312
2313 return ret;
2314 }
2315
2316 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2317 .probe = atmel_hsmc_nand_controller_probe,
2318 .remove = atmel_hsmc_nand_controller_remove,
2319 .ecc_init = atmel_hsmc_nand_ecc_init,
2320 .nand_init = atmel_hsmc_nand_init,
2321 .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2322 };
2323
2324 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2325 .has_dma = true,
2326 .ale_offs = BIT(21),
2327 .cle_offs = BIT(22),
2328 .ops = &atmel_hsmc_nc_ops,
2329 };
2330
2331 /* Only used to parse old bindings. */
2332 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2333 .has_dma = true,
2334 .ale_offs = BIT(21),
2335 .cle_offs = BIT(22),
2336 .ops = &atmel_hsmc_nc_ops,
2337 .legacy_of_bindings = true,
2338 };
2339
2340 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2341 const struct atmel_nand_controller_caps *caps)
2342 {
2343 struct device *dev = &pdev->dev;
2344 struct atmel_smc_nand_controller *nc;
2345 int ret;
2346
2347 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2348 if (!nc)
2349 return -ENOMEM;
2350
2351 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2352 if (ret)
2353 return ret;
2354
2355 ret = atmel_smc_nand_controller_init(nc);
2356 if (ret)
2357 return ret;
2358
2359 return atmel_nand_controller_add_nands(&nc->base);
2360 }
2361
2362 static int
2363 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2364 {
2365 int ret;
2366
2367 ret = atmel_nand_controller_remove_nands(nc);
2368 if (ret)
2369 return ret;
2370
2371 atmel_nand_controller_cleanup(nc);
2372
2373 return 0;
2374 }
2375
2376 /*
2377 * The SMC reg layout of at91rm9200 is completely different which prevents us
2378 * from re-using atmel_smc_nand_setup_data_interface() for the
2379 * ->setup_data_interface() hook.
2380 * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2381 * ->setup_data_interface() unassigned.
2382 */
2383 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2384 .probe = atmel_smc_nand_controller_probe,
2385 .remove = atmel_smc_nand_controller_remove,
2386 .ecc_init = atmel_nand_ecc_init,
2387 .nand_init = atmel_smc_nand_init,
2388 };
2389
2390 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2391 .ale_offs = BIT(21),
2392 .cle_offs = BIT(22),
2393 .ebi_csa_regmap_name = "atmel,matrix",
2394 .ops = &at91rm9200_nc_ops,
2395 };
2396
2397 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2398 .probe = atmel_smc_nand_controller_probe,
2399 .remove = atmel_smc_nand_controller_remove,
2400 .ecc_init = atmel_nand_ecc_init,
2401 .nand_init = atmel_smc_nand_init,
2402 .setup_data_interface = atmel_smc_nand_setup_data_interface,
2403 };
2404
2405 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2406 .ale_offs = BIT(21),
2407 .cle_offs = BIT(22),
2408 .ebi_csa_regmap_name = "atmel,matrix",
2409 .ops = &atmel_smc_nc_ops,
2410 };
2411
2412 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2413 .ale_offs = BIT(22),
2414 .cle_offs = BIT(21),
2415 .ebi_csa_regmap_name = "atmel,matrix",
2416 .ops = &atmel_smc_nc_ops,
2417 };
2418
2419 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2420 .has_dma = true,
2421 .ale_offs = BIT(21),
2422 .cle_offs = BIT(22),
2423 .ebi_csa_regmap_name = "atmel,matrix",
2424 .ops = &atmel_smc_nc_ops,
2425 };
2426
2427 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2428 .has_dma = true,
2429 .ale_offs = BIT(21),
2430 .cle_offs = BIT(22),
2431 .ebi_csa_regmap_name = "microchip,sfr",
2432 .ops = &atmel_smc_nc_ops,
2433 };
2434
2435 /* Only used to parse old bindings. */
2436 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2437 .ale_offs = BIT(21),
2438 .cle_offs = BIT(22),
2439 .ops = &atmel_smc_nc_ops,
2440 .legacy_of_bindings = true,
2441 };
2442
2443 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2444 .ale_offs = BIT(22),
2445 .cle_offs = BIT(21),
2446 .ops = &atmel_smc_nc_ops,
2447 .legacy_of_bindings = true,
2448 };
2449
2450 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2451 .has_dma = true,
2452 .ale_offs = BIT(21),
2453 .cle_offs = BIT(22),
2454 .ops = &atmel_smc_nc_ops,
2455 .legacy_of_bindings = true,
2456 };
2457
2458 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2459 {
2460 .compatible = "atmel,at91rm9200-nand-controller",
2461 .data = &atmel_rm9200_nc_caps,
2462 },
2463 {
2464 .compatible = "atmel,at91sam9260-nand-controller",
2465 .data = &atmel_sam9260_nc_caps,
2466 },
2467 {
2468 .compatible = "atmel,at91sam9261-nand-controller",
2469 .data = &atmel_sam9261_nc_caps,
2470 },
2471 {
2472 .compatible = "atmel,at91sam9g45-nand-controller",
2473 .data = &atmel_sam9g45_nc_caps,
2474 },
2475 {
2476 .compatible = "atmel,sama5d3-nand-controller",
2477 .data = &atmel_sama5_nc_caps,
2478 },
2479 {
2480 .compatible = "microchip,sam9x60-nand-controller",
2481 .data = &microchip_sam9x60_nc_caps,
2482 },
2483 /* Support for old/deprecated bindings: */
2484 {
2485 .compatible = "atmel,at91rm9200-nand",
2486 .data = &atmel_rm9200_nand_caps,
2487 },
2488 {
2489 .compatible = "atmel,sama5d4-nand",
2490 .data = &atmel_rm9200_nand_caps,
2491 },
2492 {
2493 .compatible = "atmel,sama5d2-nand",
2494 .data = &atmel_rm9200_nand_caps,
2495 },
2496 { /* sentinel */ },
2497 };
2498 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2499
2500 static int atmel_nand_controller_probe(struct platform_device *pdev)
2501 {
2502 const struct atmel_nand_controller_caps *caps;
2503
2504 if (pdev->id_entry)
2505 caps = (void *)pdev->id_entry->driver_data;
2506 else
2507 caps = of_device_get_match_data(&pdev->dev);
2508
2509 if (!caps) {
2510 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2511 return -EINVAL;
2512 }
2513
2514 if (caps->legacy_of_bindings) {
2515 struct device_node *nfc_node;
2516 u32 ale_offs = 21;
2517
2518 /*
2519 * If we are parsing legacy DT props and the DT contains a
2520 * valid NFC node, forward the request to the sama5 logic.
2521 */
2522 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2523 "atmel,sama5d3-nfc");
2524 if (nfc_node) {
2525 caps = &atmel_sama5_nand_caps;
2526 of_node_put(nfc_node);
2527 }
2528
2529 /*
2530 * Even if the compatible says we are dealing with an
2531 * at91rm9200 controller, the atmel,nand-has-dma specify that
2532 * this controller supports DMA, which means we are in fact
2533 * dealing with an at91sam9g45+ controller.
2534 */
2535 if (!caps->has_dma &&
2536 of_property_read_bool(pdev->dev.of_node,
2537 "atmel,nand-has-dma"))
2538 caps = &atmel_sam9g45_nand_caps;
2539
2540 /*
2541 * All SoCs except the at91sam9261 are assigning ALE to A21 and
2542 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2543 * actually dealing with an at91sam9261 controller.
2544 */
2545 of_property_read_u32(pdev->dev.of_node,
2546 "atmel,nand-addr-offset", &ale_offs);
2547 if (ale_offs != 21)
2548 caps = &atmel_sam9261_nand_caps;
2549 }
2550
2551 return caps->ops->probe(pdev, caps);
2552 }
2553
2554 static int atmel_nand_controller_remove(struct platform_device *pdev)
2555 {
2556 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2557
2558 return nc->caps->ops->remove(nc);
2559 }
2560
2561 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2562 {
2563 struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2564 struct atmel_nand *nand;
2565
2566 if (nc->pmecc)
2567 atmel_pmecc_reset(nc->pmecc);
2568
2569 list_for_each_entry(nand, &nc->chips, node) {
2570 int i;
2571
2572 for (i = 0; i < nand->numcs; i++)
2573 nand_reset(&nand->base, i);
2574 }
2575
2576 return 0;
2577 }
2578
2579 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2580 atmel_nand_controller_resume);
2581
2582 static struct platform_driver atmel_nand_controller_driver = {
2583 .driver = {
2584 .name = "atmel-nand-controller",
2585 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2586 .pm = &atmel_nand_controller_pm_ops,
2587 },
2588 .probe = atmel_nand_controller_probe,
2589 .remove = atmel_nand_controller_remove,
2590 };
2591 module_platform_driver(atmel_nand_controller_driver);
2592
2593 MODULE_LICENSE("GPL");
2594 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2595 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2596 MODULE_ALIAS("platform:atmel-nand-controller");
Linux with added FPC-III support