?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mmc: host: sh_mobile_sdhi: move card_busy from tmio to sdhi
[linux/fpc-iii.git] / drivers / pci / host / pci-aardvark.c
blobef9893fa3176d2db4579bf809998bd1c97d073db
1 /*
2 * Driver for the Aardvark PCIe controller, used on Marvell Armada
3 * 3700.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/kernel.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/of_address.h>
23 #include <linux/of_pci.h>
24
25 /* PCIe core registers */
26 #define PCIE_CORE_CMD_STATUS_REG 0x4
27 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
28 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
29 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
30 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
31 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
32 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
33 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
34 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
35 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
36 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
37 #define PCIE_CORE_LINK_TRAINING BIT(5)
38 #define PCIE_CORE_LINK_WIDTH_SHIFT 20
39 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
42 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
43 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
44
45 /* PIO registers base address and register offsets */
46 #define PIO_BASE_ADDR 0x4000
47 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
48 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
49 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
50 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
51 #define PIO_COMPLETION_STATUS_SHIFT 7
52 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
53 #define PIO_COMPLETION_STATUS_OK 0
54 #define PIO_COMPLETION_STATUS_UR 1
55 #define PIO_COMPLETION_STATUS_CRS 2
56 #define PIO_COMPLETION_STATUS_CA 4
57 #define PIO_NON_POSTED_REQ BIT(0)
58 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
59 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
60 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
61 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
62 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
63 #define PIO_START (PIO_BASE_ADDR + 0x1c)
64 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
65 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
66
67 /* Aardvark Control registers */
68 #define CONTROL_BASE_ADDR 0x4800
69 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
70 #define PCIE_GEN_SEL_MSK 0x3
71 #define PCIE_GEN_SEL_SHIFT 0x0
72 #define SPEED_GEN_1 0
73 #define SPEED_GEN_2 1
74 #define SPEED_GEN_3 2
75 #define IS_RC_MSK 1
76 #define IS_RC_SHIFT 2
77 #define LANE_CNT_MSK 0x18
78 #define LANE_CNT_SHIFT 0x3
79 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
81 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
82 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
83 #define LINK_TRAINING_EN BIT(6)
84 #define LEGACY_INTA BIT(28)
85 #define LEGACY_INTB BIT(29)
86 #define LEGACY_INTC BIT(30)
87 #define LEGACY_INTD BIT(31)
88 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
89 #define HOT_RESET_GEN BIT(0)
90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
91 #define PCIE_CORE_CTRL2_RESERVED 0x7
92 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
93 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
94 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
95 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
96 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
97 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
98 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
99 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
100 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
101 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
102 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
103 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
104 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
105 #define PCIE_ISR1_FLUSH BIT(5)
106 #define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
107 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
108 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
109 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
110 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
111 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
112
113 /* PCIe window configuration */
114 #define OB_WIN_BASE_ADDR 0x4c00
115 #define OB_WIN_BLOCK_SIZE 0x20
116 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
117 OB_WIN_BLOCK_SIZE * (win) + \
118 (offset))
119 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
120 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
121 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
122 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
123 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
124 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
125 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
126
127 /* PCIe window types */
128 #define OB_PCIE_MEM 0x0
129 #define OB_PCIE_IO 0x4
130
131 /* LMI registers base address and register offsets */
132 #define LMI_BASE_ADDR 0x6000
133 #define CFG_REG (LMI_BASE_ADDR + 0x0)
134 #define LTSSM_SHIFT 24
135 #define LTSSM_MASK 0x3f
136 #define LTSSM_L0 0x10
137 #define RC_BAR_CONFIG 0x300
138
139 /* PCIe core controller registers */
140 #define CTRL_CORE_BASE_ADDR 0x18000
141 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
142 #define CTRL_MODE_SHIFT 0x0
143 #define CTRL_MODE_MASK 0x1
144 #define PCIE_CORE_MODE_DIRECT 0x0
145 #define PCIE_CORE_MODE_COMMAND 0x1
146
147 /* PCIe Central Interrupts Registers */
148 #define CENTRAL_INT_BASE_ADDR 0x1b000
149 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
150 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
151 #define PCIE_IRQ_CMDQ_INT BIT(0)
152 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
153 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
154 #define PCIE_IRQ_DMA_INT BIT(4)
155 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
156 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
157 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
158 #define PCIE_IRQ_COMPQ_INT BIT(12)
159 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
160 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
161 #define PCIE_IRQ_CORE_INT BIT(16)
162 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
163 #define PCIE_IRQ_DPMU_INT BIT(18)
164 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
165 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
166 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
167 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
168 #define PCIE_IRQ_EP_STATUS BIT(23)
169 #define PCIE_IRQ_ALL_MASK 0xfff0fb
170 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
171
172 /* Transaction types */
173 #define PCIE_CONFIG_RD_TYPE0 0x8
174 #define PCIE_CONFIG_RD_TYPE1 0x9
175 #define PCIE_CONFIG_WR_TYPE0 0xa
176 #define PCIE_CONFIG_WR_TYPE1 0xb
177
178 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
179 #define PCIE_BDF(dev) (dev << 4)
180 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
181 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
182 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
183 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
184 #define PCIE_CONF_ADDR(bus, devfn, where) \
185 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
186 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
187
188 #define PIO_TIMEOUT_MS 1
189
190 #define LINK_WAIT_MAX_RETRIES 10
191 #define LINK_WAIT_USLEEP_MIN 90000
192 #define LINK_WAIT_USLEEP_MAX 100000
193
194 #define LEGACY_IRQ_NUM 4
195 #define MSI_IRQ_NUM 32
196
197 struct advk_pcie {
198 struct platform_device *pdev;
199 void __iomem *base;
200 struct list_head resources;
201 struct irq_domain *irq_domain;
202 struct irq_chip irq_chip;
203 struct msi_controller msi;
204 struct irq_domain *msi_domain;
205 struct irq_chip msi_irq_chip;
206 DECLARE_BITMAP(msi_irq_in_use, MSI_IRQ_NUM);
207 struct mutex msi_used_lock;
208 u16 msi_msg;
209 int root_bus_nr;
210 };
211
212 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
213 {
214 writel(val, pcie->base + reg);
215 }
216
217 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
218 {
219 return readl(pcie->base + reg);
220 }
221
222 static int advk_pcie_link_up(struct advk_pcie *pcie)
223 {
224 u32 val, ltssm_state;
225
226 val = advk_readl(pcie, CFG_REG);
227 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
228 return ltssm_state >= LTSSM_L0;
229 }
230
231 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
232 {
233 int retries;
234
235 /* check if the link is up or not */
236 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
237 if (advk_pcie_link_up(pcie)) {
238 dev_info(&pcie->pdev->dev, "link up\n");
239 return 0;
240 }
241
242 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
243 }
244
245 dev_err(&pcie->pdev->dev, "link never came up\n");
246
247 return -ETIMEDOUT;
248 }
249
250 /*
251 * Set PCIe address window register which could be used for memory
252 * mapping.
253 */
254 static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
255 u32 win_num, u32 match_ms,
256 u32 match_ls, u32 mask_ms,
257 u32 mask_ls, u32 remap_ms,
258 u32 remap_ls, u32 action)
259 {
260 advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
261 advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
262 advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
263 advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
264 advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
265 advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
266 advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
267 advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
268 }
269
270 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
271 {
272 u32 reg;
273 int i;
274
275 /* Point PCIe unit MBUS decode windows to DRAM space */
276 for (i = 0; i < 8; i++)
277 advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
278
279 /* Set to Direct mode */
280 reg = advk_readl(pcie, CTRL_CONFIG_REG);
281 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
282 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
283 advk_writel(pcie, reg, CTRL_CONFIG_REG);
284
285 /* Set PCI global control register to RC mode */
286 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
287 reg |= (IS_RC_MSK << IS_RC_SHIFT);
288 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
289
290 /* Set Advanced Error Capabilities and Control PF0 register */
291 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
292 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
293 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
294 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
295 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
296
297 /* Set PCIe Device Control and Status 1 PF0 register */
298 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
299 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
300 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
301 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
302 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
303
304 /* Program PCIe Control 2 to disable strict ordering */
305 reg = PCIE_CORE_CTRL2_RESERVED |
306 PCIE_CORE_CTRL2_TD_ENABLE;
307 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
308
309 /* Set GEN2 */
310 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
311 reg &= ~PCIE_GEN_SEL_MSK;
312 reg |= SPEED_GEN_2;
313 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
314
315 /* Set lane X1 */
316 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
317 reg &= ~LANE_CNT_MSK;
318 reg |= LANE_COUNT_1;
319 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
320
321 /* Enable link training */
322 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
323 reg |= LINK_TRAINING_EN;
324 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
325
326 /* Enable MSI */
327 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
328 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
329 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
330
331 /* Clear all interrupts */
332 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
333 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
334 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
335
336 /* Disable All ISR0/1 Sources */
337 reg = PCIE_ISR0_ALL_MASK;
338 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
339 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
340
341 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
342
343 /* Unmask all MSI's */
344 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
345
346 /* Enable summary interrupt for GIC SPI source */
347 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
348 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
349
350 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
351 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
352 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
353
354 /* Bypass the address window mapping for PIO */
355 reg = advk_readl(pcie, PIO_CTRL);
356 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
357 advk_writel(pcie, reg, PIO_CTRL);
358
359 /* Start link training */
360 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
361 reg |= PCIE_CORE_LINK_TRAINING;
362 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
363
364 advk_pcie_wait_for_link(pcie);
365
366 reg = PCIE_CORE_LINK_L0S_ENTRY |
367 (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
368 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
369
370 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
371 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
372 PCIE_CORE_CMD_IO_ACCESS_EN |
373 PCIE_CORE_CMD_MEM_IO_REQ_EN;
374 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
375 }
376
377 static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
378 {
379 u32 reg;
380 unsigned int status;
381 char *strcomp_status, *str_posted;
382
383 reg = advk_readl(pcie, PIO_STAT);
384 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
385 PIO_COMPLETION_STATUS_SHIFT;
386
387 if (!status)
388 return;
389
390 switch (status) {
391 case PIO_COMPLETION_STATUS_UR:
392 strcomp_status = "UR";
393 break;
394 case PIO_COMPLETION_STATUS_CRS:
395 strcomp_status = "CRS";
396 break;
397 case PIO_COMPLETION_STATUS_CA:
398 strcomp_status = "CA";
399 break;
400 default:
401 strcomp_status = "Unknown";
402 break;
403 }
404
405 if (reg & PIO_NON_POSTED_REQ)
406 str_posted = "Non-posted";
407 else
408 str_posted = "Posted";
409
410 dev_err(&pcie->pdev->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
411 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
412 }
413
414 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
415 {
416 unsigned long timeout;
417
418 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
419
420 while (time_before(jiffies, timeout)) {
421 u32 start, isr;
422
423 start = advk_readl(pcie, PIO_START);
424 isr = advk_readl(pcie, PIO_ISR);
425 if (!start && isr)
426 return 0;
427 }
428
429 dev_err(&pcie->pdev->dev, "config read/write timed out\n");
430 return -ETIMEDOUT;
431 }
432
433 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
434 int where, int size, u32 *val)
435 {
436 struct advk_pcie *pcie = bus->sysdata;
437 u32 reg;
438 int ret;
439
440 if (PCI_SLOT(devfn) != 0) {
441 *val = 0xffffffff;
442 return PCIBIOS_DEVICE_NOT_FOUND;
443 }
444
445 /* Start PIO */
446 advk_writel(pcie, 0, PIO_START);
447 advk_writel(pcie, 1, PIO_ISR);
448
449 /* Program the control register */
450 reg = advk_readl(pcie, PIO_CTRL);
451 reg &= ~PIO_CTRL_TYPE_MASK;
452 if (bus->number == pcie->root_bus_nr)
453 reg |= PCIE_CONFIG_RD_TYPE0;
454 else
455 reg |= PCIE_CONFIG_RD_TYPE1;
456 advk_writel(pcie, reg, PIO_CTRL);
457
458 /* Program the address registers */
459 reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
460 advk_writel(pcie, reg, PIO_ADDR_LS);
461 advk_writel(pcie, 0, PIO_ADDR_MS);
462
463 /* Program the data strobe */
464 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
465
466 /* Start the transfer */
467 advk_writel(pcie, 1, PIO_START);
468
469 ret = advk_pcie_wait_pio(pcie);
470 if (ret < 0)
471 return PCIBIOS_SET_FAILED;
472
473 advk_pcie_check_pio_status(pcie);
474
475 /* Get the read result */
476 *val = advk_readl(pcie, PIO_RD_DATA);
477 if (size == 1)
478 *val = (*val >> (8 * (where & 3))) & 0xff;
479 else if (size == 2)
480 *val = (*val >> (8 * (where & 3))) & 0xffff;
481
482 return PCIBIOS_SUCCESSFUL;
483 }
484
485 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
486 int where, int size, u32 val)
487 {
488 struct advk_pcie *pcie = bus->sysdata;
489 u32 reg;
490 u32 data_strobe = 0x0;
491 int offset;
492 int ret;
493
494 if (PCI_SLOT(devfn) != 0)
495 return PCIBIOS_DEVICE_NOT_FOUND;
496
497 if (where % size)
498 return PCIBIOS_SET_FAILED;
499
500 /* Start PIO */
501 advk_writel(pcie, 0, PIO_START);
502 advk_writel(pcie, 1, PIO_ISR);
503
504 /* Program the control register */
505 reg = advk_readl(pcie, PIO_CTRL);
506 reg &= ~PIO_CTRL_TYPE_MASK;
507 if (bus->number == pcie->root_bus_nr)
508 reg |= PCIE_CONFIG_WR_TYPE0;
509 else
510 reg |= PCIE_CONFIG_WR_TYPE1;
511 advk_writel(pcie, reg, PIO_CTRL);
512
513 /* Program the address registers */
514 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
515 advk_writel(pcie, reg, PIO_ADDR_LS);
516 advk_writel(pcie, 0, PIO_ADDR_MS);
517
518 /* Calculate the write strobe */
519 offset = where & 0x3;
520 reg = val << (8 * offset);
521 data_strobe = GENMASK(size - 1, 0) << offset;
522
523 /* Program the data register */
524 advk_writel(pcie, reg, PIO_WR_DATA);
525
526 /* Program the data strobe */
527 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
528
529 /* Start the transfer */
530 advk_writel(pcie, 1, PIO_START);
531
532 ret = advk_pcie_wait_pio(pcie);
533 if (ret < 0)
534 return PCIBIOS_SET_FAILED;
535
536 advk_pcie_check_pio_status(pcie);
537
538 return PCIBIOS_SUCCESSFUL;
539 }
540
541 static struct pci_ops advk_pcie_ops = {
542 .read = advk_pcie_rd_conf,
543 .write = advk_pcie_wr_conf,
544 };
545
546 static int advk_pcie_alloc_msi(struct advk_pcie *pcie)
547 {
548 int hwirq;
549
550 mutex_lock(&pcie->msi_used_lock);
551 hwirq = find_first_zero_bit(pcie->msi_irq_in_use, MSI_IRQ_NUM);
552 if (hwirq >= MSI_IRQ_NUM)
553 hwirq = -ENOSPC;
554 else
555 set_bit(hwirq, pcie->msi_irq_in_use);
556 mutex_unlock(&pcie->msi_used_lock);
557
558 return hwirq;
559 }
560
561 static void advk_pcie_free_msi(struct advk_pcie *pcie, int hwirq)
562 {
563 mutex_lock(&pcie->msi_used_lock);
564 if (!test_bit(hwirq, pcie->msi_irq_in_use))
565 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%d\n",
566 hwirq);
567 else
568 clear_bit(hwirq, pcie->msi_irq_in_use);
569 mutex_unlock(&pcie->msi_used_lock);
570 }
571
572 static int advk_pcie_setup_msi_irq(struct msi_controller *chip,
573 struct pci_dev *pdev,
574 struct msi_desc *desc)
575 {
576 struct advk_pcie *pcie = pdev->bus->sysdata;
577 struct msi_msg msg;
578 int virq, hwirq;
579 phys_addr_t msi_msg_phys;
580
581 /* We support MSI, but not MSI-X */
582 if (desc->msi_attrib.is_msix)
583 return -EINVAL;
584
585 hwirq = advk_pcie_alloc_msi(pcie);
586 if (hwirq < 0)
587 return hwirq;
588
589 virq = irq_create_mapping(pcie->msi_domain, hwirq);
590 if (!virq) {
591 advk_pcie_free_msi(pcie, hwirq);
592 return -EINVAL;
593 }
594
595 irq_set_msi_desc(virq, desc);
596
597 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
598
599 msg.address_lo = lower_32_bits(msi_msg_phys);
600 msg.address_hi = upper_32_bits(msi_msg_phys);
601 msg.data = virq;
602
603 pci_write_msi_msg(virq, &msg);
604
605 return 0;
606 }
607
608 static void advk_pcie_teardown_msi_irq(struct msi_controller *chip,
609 unsigned int irq)
610 {
611 struct irq_data *d = irq_get_irq_data(irq);
612 struct msi_desc *msi = irq_data_get_msi_desc(d);
613 struct advk_pcie *pcie = msi_desc_to_pci_sysdata(msi);
614 unsigned long hwirq = d->hwirq;
615
616 irq_dispose_mapping(irq);
617 advk_pcie_free_msi(pcie, hwirq);
618 }
619
620 static int advk_pcie_msi_map(struct irq_domain *domain,
621 unsigned int virq, irq_hw_number_t hw)
622 {
623 struct advk_pcie *pcie = domain->host_data;
624
625 irq_set_chip_and_handler(virq, &pcie->msi_irq_chip,
626 handle_simple_irq);
627
628 return 0;
629 }
630
631 static const struct irq_domain_ops advk_pcie_msi_irq_ops = {
632 .map = advk_pcie_msi_map,
633 };
634
635 static void advk_pcie_irq_mask(struct irq_data *d)
636 {
637 struct advk_pcie *pcie = d->domain->host_data;
638 irq_hw_number_t hwirq = irqd_to_hwirq(d);
639 u32 mask;
640
641 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
642 mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
643 advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
644 }
645
646 static void advk_pcie_irq_unmask(struct irq_data *d)
647 {
648 struct advk_pcie *pcie = d->domain->host_data;
649 irq_hw_number_t hwirq = irqd_to_hwirq(d);
650 u32 mask;
651
652 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
653 mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
654 advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
655 }
656
657 static int advk_pcie_irq_map(struct irq_domain *h,
658 unsigned int virq, irq_hw_number_t hwirq)
659 {
660 struct advk_pcie *pcie = h->host_data;
661
662 advk_pcie_irq_mask(irq_get_irq_data(virq));
663 irq_set_status_flags(virq, IRQ_LEVEL);
664 irq_set_chip_and_handler(virq, &pcie->irq_chip,
665 handle_level_irq);
666 irq_set_chip_data(virq, pcie);
667
668 return 0;
669 }
670
671 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
672 .map = advk_pcie_irq_map,
673 .xlate = irq_domain_xlate_onecell,
674 };
675
676 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
677 {
678 struct device *dev = &pcie->pdev->dev;
679 struct device_node *node = dev->of_node;
680 struct irq_chip *msi_irq_chip;
681 struct msi_controller *msi;
682 phys_addr_t msi_msg_phys;
683 int ret;
684
685 msi_irq_chip = &pcie->msi_irq_chip;
686
687 msi_irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-msi",
688 dev_name(dev));
689 if (!msi_irq_chip->name)
690 return -ENOMEM;
691
692 msi_irq_chip->irq_enable = pci_msi_unmask_irq;
693 msi_irq_chip->irq_disable = pci_msi_mask_irq;
694 msi_irq_chip->irq_mask = pci_msi_mask_irq;
695 msi_irq_chip->irq_unmask = pci_msi_unmask_irq;
696
697 msi = &pcie->msi;
698
699 msi->setup_irq = advk_pcie_setup_msi_irq;
700 msi->teardown_irq = advk_pcie_teardown_msi_irq;
701 msi->of_node = node;
702
703 mutex_init(&pcie->msi_used_lock);
704
705 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
706
707 advk_writel(pcie, lower_32_bits(msi_msg_phys),
708 PCIE_MSI_ADDR_LOW_REG);
709 advk_writel(pcie, upper_32_bits(msi_msg_phys),
710 PCIE_MSI_ADDR_HIGH_REG);
711
712 pcie->msi_domain =
713 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
714 &advk_pcie_msi_irq_ops, pcie);
715 if (!pcie->msi_domain)
716 return -ENOMEM;
717
718 ret = of_pci_msi_chip_add(msi);
719 if (ret < 0) {
720 irq_domain_remove(pcie->msi_domain);
721 return ret;
722 }
723
724 return 0;
725 }
726
727 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
728 {
729 of_pci_msi_chip_remove(&pcie->msi);
730 irq_domain_remove(pcie->msi_domain);
731 }
732
733 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
734 {
735 struct device *dev = &pcie->pdev->dev;
736 struct device_node *node = dev->of_node;
737 struct device_node *pcie_intc_node;
738 struct irq_chip *irq_chip;
739
740 pcie_intc_node = of_get_next_child(node, NULL);
741 if (!pcie_intc_node) {
742 dev_err(dev, "No PCIe Intc node found\n");
743 return -ENODEV;
744 }
745
746 irq_chip = &pcie->irq_chip;
747
748 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
749 dev_name(dev));
750 if (!irq_chip->name) {
751 of_node_put(pcie_intc_node);
752 return -ENOMEM;
753 }
754
755 irq_chip->irq_mask = advk_pcie_irq_mask;
756 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
757 irq_chip->irq_unmask = advk_pcie_irq_unmask;
758
759 pcie->irq_domain =
760 irq_domain_add_linear(pcie_intc_node, LEGACY_IRQ_NUM,
761 &advk_pcie_irq_domain_ops, pcie);
762 if (!pcie->irq_domain) {
763 dev_err(dev, "Failed to get a INTx IRQ domain\n");
764 of_node_put(pcie_intc_node);
765 return -ENOMEM;
766 }
767
768 return 0;
769 }
770
771 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
772 {
773 irq_domain_remove(pcie->irq_domain);
774 }
775
776 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
777 {
778 u32 msi_val, msi_mask, msi_status, msi_idx;
779 u16 msi_data;
780
781 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
782 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
783 msi_status = msi_val & ~msi_mask;
784
785 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
786 if (!(BIT(msi_idx) & msi_status))
787 continue;
788
789 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
790 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
791 generic_handle_irq(msi_data);
792 }
793
794 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
795 PCIE_ISR0_REG);
796 }
797
798 static void advk_pcie_handle_int(struct advk_pcie *pcie)
799 {
800 u32 val, mask, status;
801 int i, virq;
802
803 val = advk_readl(pcie, PCIE_ISR0_REG);
804 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
805 status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
806
807 if (!status) {
808 advk_writel(pcie, val, PCIE_ISR0_REG);
809 return;
810 }
811
812 /* Process MSI interrupts */
813 if (status & PCIE_ISR0_MSI_INT_PENDING)
814 advk_pcie_handle_msi(pcie);
815
816 /* Process legacy interrupts */
817 for (i = 0; i < LEGACY_IRQ_NUM; i++) {
818 if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
819 continue;
820
821 advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
822 PCIE_ISR0_REG);
823
824 virq = irq_find_mapping(pcie->irq_domain, i);
825 generic_handle_irq(virq);
826 }
827 }
828
829 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
830 {
831 struct advk_pcie *pcie = arg;
832 u32 status;
833
834 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
835 if (!(status & PCIE_IRQ_CORE_INT))
836 return IRQ_NONE;
837
838 advk_pcie_handle_int(pcie);
839
840 /* Clear interrupt */
841 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
842
843 return IRQ_HANDLED;
844 }
845
846 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
847 {
848 int err, res_valid = 0;
849 struct device *dev = &pcie->pdev->dev;
850 struct device_node *np = dev->of_node;
851 struct resource_entry *win;
852 resource_size_t iobase;
853
854 INIT_LIST_HEAD(&pcie->resources);
855
856 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
857 &iobase);
858 if (err)
859 return err;
860
861 err = devm_request_pci_bus_resources(dev, &pcie->resources);
862 if (err)
863 goto out_release_res;
864
865 resource_list_for_each_entry(win, &pcie->resources) {
866 struct resource *res = win->res;
867
868 switch (resource_type(res)) {
869 case IORESOURCE_IO:
870 advk_pcie_set_ob_win(pcie, 1,
871 upper_32_bits(res->start),
872 lower_32_bits(res->start),
873 0, 0xF8000000, 0,
874 lower_32_bits(res->start),
875 OB_PCIE_IO);
876 err = pci_remap_iospace(res, iobase);
877 if (err)
878 dev_warn(dev, "error %d: failed to map resource %pR\n",
879 err, res);
880 break;
881 case IORESOURCE_MEM:
882 advk_pcie_set_ob_win(pcie, 0,
883 upper_32_bits(res->start),
884 lower_32_bits(res->start),
885 0x0, 0xF8000000, 0,
886 lower_32_bits(res->start),
887 (2 << 20) | OB_PCIE_MEM);
888 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
889 break;
890 case IORESOURCE_BUS:
891 pcie->root_bus_nr = res->start;
892 break;
893 }
894 }
895
896 if (!res_valid) {
897 dev_err(dev, "non-prefetchable memory resource required\n");
898 err = -EINVAL;
899 goto out_release_res;
900 }
901
902 return 0;
903
904 out_release_res:
905 pci_free_resource_list(&pcie->resources);
906 return err;
907 }
908
909 static int advk_pcie_probe(struct platform_device *pdev)
910 {
911 struct advk_pcie *pcie;
912 struct resource *res;
913 struct pci_bus *bus, *child;
914 struct msi_controller *msi;
915 struct device_node *msi_node;
916 int ret, irq;
917
918 pcie = devm_kzalloc(&pdev->dev, sizeof(struct advk_pcie),
919 GFP_KERNEL);
920 if (!pcie)
921 return -ENOMEM;
922
923 pcie->pdev = pdev;
924 platform_set_drvdata(pdev, pcie);
925
926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
927 pcie->base = devm_ioremap_resource(&pdev->dev, res);
928 if (IS_ERR(pcie->base)) {
929 dev_err(&pdev->dev, "Failed to map registers\n");
930 return PTR_ERR(pcie->base);
931 }
932
933 irq = platform_get_irq(pdev, 0);
934 ret = devm_request_irq(&pdev->dev, irq, advk_pcie_irq_handler,
935 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
936 pcie);
937 if (ret) {
938 dev_err(&pdev->dev, "Failed to register interrupt\n");
939 return ret;
940 }
941
942 ret = advk_pcie_parse_request_of_pci_ranges(pcie);
943 if (ret) {
944 dev_err(&pdev->dev, "Failed to parse resources\n");
945 return ret;
946 }
947
948 advk_pcie_setup_hw(pcie);
949
950 ret = advk_pcie_init_irq_domain(pcie);
951 if (ret) {
952 dev_err(&pdev->dev, "Failed to initialize irq\n");
953 return ret;
954 }
955
956 ret = advk_pcie_init_msi_irq_domain(pcie);
957 if (ret) {
958 dev_err(&pdev->dev, "Failed to initialize irq\n");
959 advk_pcie_remove_irq_domain(pcie);
960 return ret;
961 }
962
963 msi_node = of_parse_phandle(pdev->dev.of_node, "msi-parent", 0);
964 if (msi_node)
965 msi = of_pci_find_msi_chip_by_node(msi_node);
966 else
967 msi = NULL;
968
969 bus = pci_scan_root_bus_msi(&pdev->dev, 0, &advk_pcie_ops,
970 pcie, &pcie->resources, &pcie->msi);
971 if (!bus) {
972 advk_pcie_remove_msi_irq_domain(pcie);
973 advk_pcie_remove_irq_domain(pcie);
974 return -ENOMEM;
975 }
976
977 pci_bus_assign_resources(bus);
978
979 list_for_each_entry(child, &bus->children, node)
980 pcie_bus_configure_settings(child);
981
982 pci_bus_add_devices(bus);
983
984 return 0;
985 }
986
987 static const struct of_device_id advk_pcie_of_match_table[] = {
988 { .compatible = "marvell,armada-3700-pcie", },
989 {},
990 };
991
992 static struct platform_driver advk_pcie_driver = {
993 .driver = {
994 .name = "advk-pcie",
995 .of_match_table = advk_pcie_of_match_table,
996 /* Driver unloading/unbinding currently not supported */
997 .suppress_bind_attrs = true,
998 },
999 .probe = advk_pcie_probe,
1000 };
1001 builtin_platform_driver(advk_pcie_driver);
Linux with added FPC-III support