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mmc: host: sh_mobile_sdhi: move card_busy from tmio to sdhi
[linux/fpc-iii.git] / drivers / pci / host / pcie-rcar.c
blob65db7a2215090ff4508141dc131fb37104b9a34b
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * Author: Phil Edworthy <phil.edworthy@renesas.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33
34 #define DRV_NAME "rcar-pcie"
35
36 #define PCIECAR 0x000010
37 #define PCIECCTLR 0x000018
38 #define CONFIG_SEND_ENABLE (1 << 31)
39 #define TYPE0 (0 << 8)
40 #define TYPE1 (1 << 8)
41 #define PCIECDR 0x000020
42 #define PCIEMSR 0x000028
43 #define PCIEINTXR 0x000400
44 #define PCIEMSITXR 0x000840
45
46 /* Transfer control */
47 #define PCIETCTLR 0x02000
48 #define CFINIT 1
49 #define PCIETSTR 0x02004
50 #define DATA_LINK_ACTIVE 1
51 #define PCIEERRFR 0x02020
52 #define UNSUPPORTED_REQUEST (1 << 4)
53 #define PCIEMSIFR 0x02044
54 #define PCIEMSIALR 0x02048
55 #define MSIFE 1
56 #define PCIEMSIAUR 0x0204c
57 #define PCIEMSIIER 0x02050
58
59 /* root port address */
60 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
61
62 /* local address reg & mask */
63 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
64 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
65 #define LAM_PREFETCH (1 << 3)
66 #define LAM_64BIT (1 << 2)
67 #define LAR_ENABLE (1 << 1)
68
69 /* PCIe address reg & mask */
70 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
71 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
72 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
73 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
74 #define PAR_ENABLE (1 << 31)
75 #define IO_SPACE (1 << 8)
76
77 /* Configuration */
78 #define PCICONF(x) (0x010000 + ((x) * 0x4))
79 #define PMCAP(x) (0x010040 + ((x) * 0x4))
80 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
81 #define VCCAP(x) (0x010100 + ((x) * 0x4))
82
83 /* link layer */
84 #define IDSETR1 0x011004
85 #define TLCTLR 0x011048
86 #define MACSR 0x011054
87 #define MACCTLR 0x011058
88 #define SCRAMBLE_DISABLE (1 << 27)
89
90 /* R-Car H1 PHY */
91 #define H1_PCIEPHYADRR 0x04000c
92 #define WRITE_CMD (1 << 16)
93 #define PHY_ACK (1 << 24)
94 #define RATE_POS 12
95 #define LANE_POS 8
96 #define ADR_POS 0
97 #define H1_PCIEPHYDOUTR 0x040014
98 #define H1_PCIEPHYSR 0x040018
99
100 /* R-Car Gen2 PHY */
101 #define GEN2_PCIEPHYADDR 0x780
102 #define GEN2_PCIEPHYDATA 0x784
103 #define GEN2_PCIEPHYCTRL 0x78c
104
105 #define INT_PCI_MSI_NR 32
106
107 #define RCONF(x) (PCICONF(0)+(x))
108 #define RPMCAP(x) (PMCAP(0)+(x))
109 #define REXPCAP(x) (EXPCAP(0)+(x))
110 #define RVCCAP(x) (VCCAP(0)+(x))
111
112 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
113 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
114 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
115
116 #define RCAR_PCI_MAX_RESOURCES 4
117 #define MAX_NR_INBOUND_MAPS 6
118
119 struct rcar_msi {
120 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
121 struct irq_domain *domain;
122 struct msi_controller chip;
123 unsigned long pages;
124 struct mutex lock;
125 int irq1;
126 int irq2;
127 };
128
129 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
130 {
131 return container_of(chip, struct rcar_msi, chip);
132 }
133
134 /* Structure representing the PCIe interface */
135 struct rcar_pcie {
136 struct device *dev;
137 void __iomem *base;
138 struct list_head resources;
139 int root_bus_nr;
140 struct clk *clk;
141 struct clk *bus_clk;
142 struct rcar_msi msi;
143 };
144
145 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
146 unsigned long reg)
147 {
148 writel(val, pcie->base + reg);
149 }
150
151 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
152 unsigned long reg)
153 {
154 return readl(pcie->base + reg);
155 }
156
157 enum {
158 RCAR_PCI_ACCESS_READ,
159 RCAR_PCI_ACCESS_WRITE,
160 };
161
162 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
163 {
164 int shift = 8 * (where & 3);
165 u32 val = rcar_pci_read_reg(pcie, where & ~3);
166
167 val &= ~(mask << shift);
168 val |= data << shift;
169 rcar_pci_write_reg(pcie, val, where & ~3);
170 }
171
172 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
173 {
174 int shift = 8 * (where & 3);
175 u32 val = rcar_pci_read_reg(pcie, where & ~3);
176
177 return val >> shift;
178 }
179
180 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
181 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
182 unsigned char access_type, struct pci_bus *bus,
183 unsigned int devfn, int where, u32 *data)
184 {
185 int dev, func, reg, index;
186
187 dev = PCI_SLOT(devfn);
188 func = PCI_FUNC(devfn);
189 reg = where & ~3;
190 index = reg / 4;
191
192 /*
193 * While each channel has its own memory-mapped extended config
194 * space, it's generally only accessible when in endpoint mode.
195 * When in root complex mode, the controller is unable to target
196 * itself with either type 0 or type 1 accesses, and indeed, any
197 * controller initiated target transfer to its own config space
198 * result in a completer abort.
199 *
200 * Each channel effectively only supports a single device, but as
201 * the same channel <-> device access works for any PCI_SLOT()
202 * value, we cheat a bit here and bind the controller's config
203 * space to devfn 0 in order to enable self-enumeration. In this
204 * case the regular ECAR/ECDR path is sidelined and the mangled
205 * config access itself is initiated as an internal bus transaction.
206 */
207 if (pci_is_root_bus(bus)) {
208 if (dev != 0)
209 return PCIBIOS_DEVICE_NOT_FOUND;
210
211 if (access_type == RCAR_PCI_ACCESS_READ) {
212 *data = rcar_pci_read_reg(pcie, PCICONF(index));
213 } else {
214 /* Keep an eye out for changes to the root bus number */
215 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
216 pcie->root_bus_nr = *data & 0xff;
217
218 rcar_pci_write_reg(pcie, *data, PCICONF(index));
219 }
220
221 return PCIBIOS_SUCCESSFUL;
222 }
223
224 if (pcie->root_bus_nr < 0)
225 return PCIBIOS_DEVICE_NOT_FOUND;
226
227 /* Clear errors */
228 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
229
230 /* Set the PIO address */
231 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
232 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
233
234 /* Enable the configuration access */
235 if (bus->parent->number == pcie->root_bus_nr)
236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
237 else
238 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
239
240 /* Check for errors */
241 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
242 return PCIBIOS_DEVICE_NOT_FOUND;
243
244 /* Check for master and target aborts */
245 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
246 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
247 return PCIBIOS_DEVICE_NOT_FOUND;
248
249 if (access_type == RCAR_PCI_ACCESS_READ)
250 *data = rcar_pci_read_reg(pcie, PCIECDR);
251 else
252 rcar_pci_write_reg(pcie, *data, PCIECDR);
253
254 /* Disable the configuration access */
255 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
256
257 return PCIBIOS_SUCCESSFUL;
258 }
259
260 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
261 int where, int size, u32 *val)
262 {
263 struct rcar_pcie *pcie = bus->sysdata;
264 int ret;
265
266 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
267 bus, devfn, where, val);
268 if (ret != PCIBIOS_SUCCESSFUL) {
269 *val = 0xffffffff;
270 return ret;
271 }
272
273 if (size == 1)
274 *val = (*val >> (8 * (where & 3))) & 0xff;
275 else if (size == 2)
276 *val = (*val >> (8 * (where & 2))) & 0xffff;
277
278 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
279 bus->number, devfn, where, size, (unsigned long)*val);
280
281 return ret;
282 }
283
284 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
285 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
286 int where, int size, u32 val)
287 {
288 struct rcar_pcie *pcie = bus->sysdata;
289 int shift, ret;
290 u32 data;
291
292 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
293 bus, devfn, where, &data);
294 if (ret != PCIBIOS_SUCCESSFUL)
295 return ret;
296
297 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
298 bus->number, devfn, where, size, (unsigned long)val);
299
300 if (size == 1) {
301 shift = 8 * (where & 3);
302 data &= ~(0xff << shift);
303 data |= ((val & 0xff) << shift);
304 } else if (size == 2) {
305 shift = 8 * (where & 2);
306 data &= ~(0xffff << shift);
307 data |= ((val & 0xffff) << shift);
308 } else
309 data = val;
310
311 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
312 bus, devfn, where, &data);
313
314 return ret;
315 }
316
317 static struct pci_ops rcar_pcie_ops = {
318 .read = rcar_pcie_read_conf,
319 .write = rcar_pcie_write_conf,
320 };
321
322 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
323 struct resource *res)
324 {
325 /* Setup PCIe address space mappings for each resource */
326 resource_size_t size;
327 resource_size_t res_start;
328 u32 mask;
329
330 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
331
332 /*
333 * The PAMR mask is calculated in units of 128Bytes, which
334 * keeps things pretty simple.
335 */
336 size = resource_size(res);
337 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
338 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
339
340 if (res->flags & IORESOURCE_IO)
341 res_start = pci_pio_to_address(res->start);
342 else
343 res_start = res->start;
344
345 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
346 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
347 PCIEPALR(win));
348
349 /* First resource is for IO */
350 mask = PAR_ENABLE;
351 if (res->flags & IORESOURCE_IO)
352 mask |= IO_SPACE;
353
354 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
355 }
356
357 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
358 {
359 struct resource_entry *win;
360 int i = 0;
361
362 /* Setup PCI resources */
363 resource_list_for_each_entry(win, &pci->resources) {
364 struct resource *res = win->res;
365
366 if (!res->flags)
367 continue;
368
369 switch (resource_type(res)) {
370 case IORESOURCE_IO:
371 case IORESOURCE_MEM:
372 rcar_pcie_setup_window(i, pci, res);
373 i++;
374 break;
375 case IORESOURCE_BUS:
376 pci->root_bus_nr = res->start;
377 break;
378 default:
379 continue;
380 }
381
382 pci_add_resource(resource, res);
383 }
384
385 return 1;
386 }
387
388 static int rcar_pcie_enable(struct rcar_pcie *pcie)
389 {
390 struct pci_bus *bus, *child;
391 LIST_HEAD(res);
392
393 rcar_pcie_setup(&res, pcie);
394
395 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
396
397 if (IS_ENABLED(CONFIG_PCI_MSI))
398 bus = pci_scan_root_bus_msi(pcie->dev, pcie->root_bus_nr,
399 &rcar_pcie_ops, pcie, &res, &pcie->msi.chip);
400 else
401 bus = pci_scan_root_bus(pcie->dev, pcie->root_bus_nr,
402 &rcar_pcie_ops, pcie, &res);
403
404 if (!bus) {
405 dev_err(pcie->dev, "Scanning rootbus failed");
406 return -ENODEV;
407 }
408
409 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
410
411 pci_bus_size_bridges(bus);
412 pci_bus_assign_resources(bus);
413
414 list_for_each_entry(child, &bus->children, node)
415 pcie_bus_configure_settings(child);
416
417 pci_bus_add_devices(bus);
418
419 return 0;
420 }
421
422 static int phy_wait_for_ack(struct rcar_pcie *pcie)
423 {
424 unsigned int timeout = 100;
425
426 while (timeout--) {
427 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
428 return 0;
429
430 udelay(100);
431 }
432
433 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
434
435 return -ETIMEDOUT;
436 }
437
438 static void phy_write_reg(struct rcar_pcie *pcie,
439 unsigned int rate, unsigned int addr,
440 unsigned int lane, unsigned int data)
441 {
442 unsigned long phyaddr;
443
444 phyaddr = WRITE_CMD |
445 ((rate & 1) << RATE_POS) |
446 ((lane & 0xf) << LANE_POS) |
447 ((addr & 0xff) << ADR_POS);
448
449 /* Set write data */
450 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
451 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
452
453 /* Ignore errors as they will be dealt with if the data link is down */
454 phy_wait_for_ack(pcie);
455
456 /* Clear command */
457 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
458 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
459
460 /* Ignore errors as they will be dealt with if the data link is down */
461 phy_wait_for_ack(pcie);
462 }
463
464 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
465 {
466 unsigned int timeout = 10;
467
468 while (timeout--) {
469 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
470 return 0;
471
472 msleep(5);
473 }
474
475 return -ETIMEDOUT;
476 }
477
478 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
479 {
480 int err;
481
482 /* Begin initialization */
483 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
484
485 /* Set mode */
486 rcar_pci_write_reg(pcie, 1, PCIEMSR);
487
488 /*
489 * Initial header for port config space is type 1, set the device
490 * class to match. Hardware takes care of propagating the IDSETR
491 * settings, so there is no need to bother with a quirk.
492 */
493 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
494
495 /*
496 * Setup Secondary Bus Number & Subordinate Bus Number, even though
497 * they aren't used, to avoid bridge being detected as broken.
498 */
499 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
500 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
501
502 /* Initialize default capabilities. */
503 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
504 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
505 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
506 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
507 PCI_HEADER_TYPE_BRIDGE);
508
509 /* Enable data link layer active state reporting */
510 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
511 PCI_EXP_LNKCAP_DLLLARC);
512
513 /* Write out the physical slot number = 0 */
514 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
515
516 /* Set the completion timer timeout to the maximum 50ms. */
517 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
518
519 /* Terminate list of capabilities (Next Capability Offset=0) */
520 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
521
522 /* Enable MSI */
523 if (IS_ENABLED(CONFIG_PCI_MSI))
524 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
525
526 /* Finish initialization - establish a PCI Express link */
527 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
528
529 /* This will timeout if we don't have a link. */
530 err = rcar_pcie_wait_for_dl(pcie);
531 if (err)
532 return err;
533
534 /* Enable INTx interrupts */
535 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
536
537 wmb();
538
539 return 0;
540 }
541
542 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
543 {
544 unsigned int timeout = 10;
545
546 /* Initialize the phy */
547 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
548 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
549 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
550 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
551 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
552 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
553 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
554 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
555 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
556 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
557 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
558 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
559
560 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
561 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
562 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
563
564 while (timeout--) {
565 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
566 return rcar_pcie_hw_init(pcie);
567
568 msleep(5);
569 }
570
571 return -ETIMEDOUT;
572 }
573
574 static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
575 {
576 /*
577 * These settings come from the R-Car Series, 2nd Generation User's
578 * Manual, section 50.3.1 (2) Initialization of the physical layer.
579 */
580 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
581 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
582 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
583 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
584
585 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
586 /* The following value is for DC connection, no termination resistor */
587 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
588 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
589 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
590
591 return rcar_pcie_hw_init(pcie);
592 }
593
594 static int rcar_msi_alloc(struct rcar_msi *chip)
595 {
596 int msi;
597
598 mutex_lock(&chip->lock);
599
600 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
601 if (msi < INT_PCI_MSI_NR)
602 set_bit(msi, chip->used);
603 else
604 msi = -ENOSPC;
605
606 mutex_unlock(&chip->lock);
607
608 return msi;
609 }
610
611 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
612 {
613 mutex_lock(&chip->lock);
614 clear_bit(irq, chip->used);
615 mutex_unlock(&chip->lock);
616 }
617
618 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
619 {
620 struct rcar_pcie *pcie = data;
621 struct rcar_msi *msi = &pcie->msi;
622 unsigned long reg;
623
624 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
625
626 /* MSI & INTx share an interrupt - we only handle MSI here */
627 if (!reg)
628 return IRQ_NONE;
629
630 while (reg) {
631 unsigned int index = find_first_bit(&reg, 32);
632 unsigned int irq;
633
634 /* clear the interrupt */
635 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
636
637 irq = irq_find_mapping(msi->domain, index);
638 if (irq) {
639 if (test_bit(index, msi->used))
640 generic_handle_irq(irq);
641 else
642 dev_info(pcie->dev, "unhandled MSI\n");
643 } else {
644 /* Unknown MSI, just clear it */
645 dev_dbg(pcie->dev, "unexpected MSI\n");
646 }
647
648 /* see if there's any more pending in this vector */
649 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
650 }
651
652 return IRQ_HANDLED;
653 }
654
655 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
656 struct msi_desc *desc)
657 {
658 struct rcar_msi *msi = to_rcar_msi(chip);
659 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
660 struct msi_msg msg;
661 unsigned int irq;
662 int hwirq;
663
664 hwirq = rcar_msi_alloc(msi);
665 if (hwirq < 0)
666 return hwirq;
667
668 irq = irq_create_mapping(msi->domain, hwirq);
669 if (!irq) {
670 rcar_msi_free(msi, hwirq);
671 return -EINVAL;
672 }
673
674 irq_set_msi_desc(irq, desc);
675
676 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
677 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
678 msg.data = hwirq;
679
680 pci_write_msi_msg(irq, &msg);
681
682 return 0;
683 }
684
685 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
686 {
687 struct rcar_msi *msi = to_rcar_msi(chip);
688 struct irq_data *d = irq_get_irq_data(irq);
689
690 rcar_msi_free(msi, d->hwirq);
691 }
692
693 static struct irq_chip rcar_msi_irq_chip = {
694 .name = "R-Car PCIe MSI",
695 .irq_enable = pci_msi_unmask_irq,
696 .irq_disable = pci_msi_mask_irq,
697 .irq_mask = pci_msi_mask_irq,
698 .irq_unmask = pci_msi_unmask_irq,
699 };
700
701 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
702 irq_hw_number_t hwirq)
703 {
704 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
705 irq_set_chip_data(irq, domain->host_data);
706
707 return 0;
708 }
709
710 static const struct irq_domain_ops msi_domain_ops = {
711 .map = rcar_msi_map,
712 };
713
714 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
715 {
716 struct platform_device *pdev = to_platform_device(pcie->dev);
717 struct rcar_msi *msi = &pcie->msi;
718 unsigned long base;
719 int err;
720
721 mutex_init(&msi->lock);
722
723 msi->chip.dev = pcie->dev;
724 msi->chip.setup_irq = rcar_msi_setup_irq;
725 msi->chip.teardown_irq = rcar_msi_teardown_irq;
726
727 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
728 &msi_domain_ops, &msi->chip);
729 if (!msi->domain) {
730 dev_err(&pdev->dev, "failed to create IRQ domain\n");
731 return -ENOMEM;
732 }
733
734 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
735 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
736 IRQF_SHARED | IRQF_NO_THREAD,
737 rcar_msi_irq_chip.name, pcie);
738 if (err < 0) {
739 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
740 goto err;
741 }
742
743 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
744 IRQF_SHARED | IRQF_NO_THREAD,
745 rcar_msi_irq_chip.name, pcie);
746 if (err < 0) {
747 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
748 goto err;
749 }
750
751 /* setup MSI data target */
752 msi->pages = __get_free_pages(GFP_KERNEL, 0);
753 base = virt_to_phys((void *)msi->pages);
754
755 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
756 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
757
758 /* enable all MSI interrupts */
759 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
760
761 return 0;
762
763 err:
764 irq_domain_remove(msi->domain);
765 return err;
766 }
767
768 static int rcar_pcie_get_resources(struct platform_device *pdev,
769 struct rcar_pcie *pcie)
770 {
771 struct resource res;
772 int err, i;
773
774 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
775 if (err)
776 return err;
777
778 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
779 if (IS_ERR(pcie->clk)) {
780 dev_err(pcie->dev, "cannot get platform clock\n");
781 return PTR_ERR(pcie->clk);
782 }
783 err = clk_prepare_enable(pcie->clk);
784 if (err)
785 goto fail_clk;
786
787 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
788 if (IS_ERR(pcie->bus_clk)) {
789 dev_err(pcie->dev, "cannot get pcie bus clock\n");
790 err = PTR_ERR(pcie->bus_clk);
791 goto fail_clk;
792 }
793 err = clk_prepare_enable(pcie->bus_clk);
794 if (err)
795 goto err_map_reg;
796
797 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
798 if (!i) {
799 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
800 err = -ENOENT;
801 goto err_map_reg;
802 }
803 pcie->msi.irq1 = i;
804
805 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
806 if (!i) {
807 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
808 err = -ENOENT;
809 goto err_map_reg;
810 }
811 pcie->msi.irq2 = i;
812
813 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
814 if (IS_ERR(pcie->base)) {
815 err = PTR_ERR(pcie->base);
816 goto err_map_reg;
817 }
818
819 return 0;
820
821 err_map_reg:
822 clk_disable_unprepare(pcie->bus_clk);
823 fail_clk:
824 clk_disable_unprepare(pcie->clk);
825
826 return err;
827 }
828
829 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
830 struct of_pci_range *range,
831 int *index)
832 {
833 u64 restype = range->flags;
834 u64 cpu_addr = range->cpu_addr;
835 u64 cpu_end = range->cpu_addr + range->size;
836 u64 pci_addr = range->pci_addr;
837 u32 flags = LAM_64BIT | LAR_ENABLE;
838 u64 mask;
839 u64 size;
840 int idx = *index;
841
842 if (restype & IORESOURCE_PREFETCH)
843 flags |= LAM_PREFETCH;
844
845 /*
846 * If the size of the range is larger than the alignment of the start
847 * address, we have to use multiple entries to perform the mapping.
848 */
849 if (cpu_addr > 0) {
850 unsigned long nr_zeros = __ffs64(cpu_addr);
851 u64 alignment = 1ULL << nr_zeros;
852
853 size = min(range->size, alignment);
854 } else {
855 size = range->size;
856 }
857 /* Hardware supports max 4GiB inbound region */
858 size = min(size, 1ULL << 32);
859
860 mask = roundup_pow_of_two(size) - 1;
861 mask &= ~0xf;
862
863 while (cpu_addr < cpu_end) {
864 /*
865 * Set up 64-bit inbound regions as the range parser doesn't
866 * distinguish between 32 and 64-bit types.
867 */
868 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
869 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
870 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
871
872 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
873 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
874 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
875
876 pci_addr += size;
877 cpu_addr += size;
878 idx += 2;
879
880 if (idx > MAX_NR_INBOUND_MAPS) {
881 dev_err(pcie->dev, "Failed to map inbound regions!\n");
882 return -EINVAL;
883 }
884 }
885 *index = idx;
886
887 return 0;
888 }
889
890 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
891 struct device_node *node)
892 {
893 const int na = 3, ns = 2;
894 int rlen;
895
896 parser->node = node;
897 parser->pna = of_n_addr_cells(node);
898 parser->np = parser->pna + na + ns;
899
900 parser->range = of_get_property(node, "dma-ranges", &rlen);
901 if (!parser->range)
902 return -ENOENT;
903
904 parser->end = parser->range + rlen / sizeof(__be32);
905 return 0;
906 }
907
908 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
909 struct device_node *np)
910 {
911 struct of_pci_range range;
912 struct of_pci_range_parser parser;
913 int index = 0;
914 int err;
915
916 if (pci_dma_range_parser_init(&parser, np))
917 return -EINVAL;
918
919 /* Get the dma-ranges from DT */
920 for_each_of_pci_range(&parser, &range) {
921 u64 end = range.cpu_addr + range.size - 1;
922 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
923 range.flags, range.cpu_addr, end, range.pci_addr);
924
925 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
926 if (err)
927 return err;
928 }
929
930 return 0;
931 }
932
933 static const struct of_device_id rcar_pcie_of_match[] = {
934 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
935 { .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init_gen2 },
936 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init_gen2 },
937 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init_gen2 },
938 { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
939 {},
940 };
941
942 static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
943 {
944 int err;
945 struct device *dev = pci->dev;
946 struct device_node *np = dev->of_node;
947 resource_size_t iobase;
948 struct resource_entry *win;
949
950 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources, &iobase);
951 if (err)
952 return err;
953
954 err = devm_request_pci_bus_resources(dev, &pci->resources);
955 if (err)
956 goto out_release_res;
957
958 resource_list_for_each_entry(win, &pci->resources) {
959 struct resource *res = win->res;
960
961 if (resource_type(res) == IORESOURCE_IO) {
962 err = pci_remap_iospace(res, iobase);
963 if (err)
964 dev_warn(dev, "error %d: failed to map resource %pR\n",
965 err, res);
966 }
967 }
968
969 return 0;
970
971 out_release_res:
972 pci_free_resource_list(&pci->resources);
973 return err;
974 }
975
976 static int rcar_pcie_probe(struct platform_device *pdev)
977 {
978 struct rcar_pcie *pcie;
979 unsigned int data;
980 const struct of_device_id *of_id;
981 int err;
982 int (*hw_init_fn)(struct rcar_pcie *);
983
984 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
985 if (!pcie)
986 return -ENOMEM;
987
988 pcie->dev = &pdev->dev;
989 platform_set_drvdata(pdev, pcie);
990
991 INIT_LIST_HEAD(&pcie->resources);
992
993 rcar_pcie_parse_request_of_pci_ranges(pcie);
994
995 err = rcar_pcie_get_resources(pdev, pcie);
996 if (err < 0) {
997 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
998 return err;
999 }
1000
1001 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
1002 if (err)
1003 return err;
1004
1005 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
1006 if (!of_id || !of_id->data)
1007 return -EINVAL;
1008 hw_init_fn = of_id->data;
1009
1010 pm_runtime_enable(pcie->dev);
1011 err = pm_runtime_get_sync(pcie->dev);
1012 if (err < 0) {
1013 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1014 goto err_pm_disable;
1015 }
1016
1017 /* Failure to get a link might just be that no cards are inserted */
1018 err = hw_init_fn(pcie);
1019 if (err) {
1020 dev_info(&pdev->dev, "PCIe link down\n");
1021 err = 0;
1022 goto err_pm_put;
1023 }
1024
1025 data = rcar_pci_read_reg(pcie, MACSR);
1026 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1027
1028 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1029 err = rcar_pcie_enable_msi(pcie);
1030 if (err < 0) {
1031 dev_err(&pdev->dev,
1032 "failed to enable MSI support: %d\n",
1033 err);
1034 goto err_pm_put;
1035 }
1036 }
1037
1038 err = rcar_pcie_enable(pcie);
1039 if (err)
1040 goto err_pm_put;
1041
1042 return 0;
1043
1044 err_pm_put:
1045 pm_runtime_put(pcie->dev);
1046
1047 err_pm_disable:
1048 pm_runtime_disable(pcie->dev);
1049 return err;
1050 }
1051
1052 static struct platform_driver rcar_pcie_driver = {
1053 .driver = {
1054 .name = DRV_NAME,
1055 .of_match_table = rcar_pcie_of_match,
1056 .suppress_bind_attrs = true,
1057 },
1058 .probe = rcar_pcie_probe,
1059 };
1060 builtin_platform_driver(rcar_pcie_driver);
Linux with added FPC-III support