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mmc: host: sh_mobile_sdhi: move card_busy from tmio to sdhi
[linux/fpc-iii.git] / drivers / pinctrl / nomadik / pinctrl-nomadik.c
blob35f62180db4e0427393f715ba5ba450d5c6fbeef
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/of_device.h>
26 #include <linux/of_address.h>
27 #include <linux/bitops.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf.h>
32 /* Since we request GPIOs from ourself */
33 #include <linux/pinctrl/consumer.h>
34 #include "pinctrl-nomadik.h"
35 #include "../core.h"
36 #include "../pinctrl-utils.h"
37
38 /*
39 * The GPIO module in the Nomadik family of Systems-on-Chip is an
40 * AMBA device, managing 32 pins and alternate functions. The logic block
41 * is currently used in the Nomadik and ux500.
42 *
43 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
44 */
45
46 /*
47 * pin configurations are represented by 32-bit integers:
48 *
49 * bit 0.. 8 - Pin Number (512 Pins Maximum)
50 * bit 9..10 - Alternate Function Selection
51 * bit 11..12 - Pull up/down state
52 * bit 13 - Sleep mode behaviour
53 * bit 14 - Direction
54 * bit 15 - Value (if output)
55 * bit 16..18 - SLPM pull up/down state
56 * bit 19..20 - SLPM direction
57 * bit 21..22 - SLPM Value (if output)
58 * bit 23..25 - PDIS value (if input)
59 * bit 26 - Gpio mode
60 * bit 27 - Sleep mode
61 *
62 * to facilitate the definition, the following macros are provided
63 *
64 * PIN_CFG_DEFAULT - default config (0):
65 * pull up/down = disabled
66 * sleep mode = input/wakeup
67 * direction = input
68 * value = low
69 * SLPM direction = same as normal
70 * SLPM pull = same as normal
71 * SLPM value = same as normal
72 *
73 * PIN_CFG - default config with alternate function
74 */
75
76 typedef unsigned long pin_cfg_t;
77
78 #define PIN_NUM_MASK 0x1ff
79 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
80
81 #define PIN_ALT_SHIFT 9
82 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
83 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
84 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
85 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
86 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
87 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
88
89 #define PIN_PULL_SHIFT 11
90 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
91 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
92 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
93 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
94 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
95
96 #define PIN_SLPM_SHIFT 13
97 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
98 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
99 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
100 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
101 /* These two replace the above in DB8500v2+ */
102 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
103 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
104 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
105
106 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
107 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
108
109 #define PIN_DIR_SHIFT 14
110 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
111 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
112 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
113 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
114
115 #define PIN_VAL_SHIFT 15
116 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
117 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
118 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
119 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
120
121 #define PIN_SLPM_PULL_SHIFT 16
122 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
123 #define PIN_SLPM_PULL(x) \
124 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
125 #define PIN_SLPM_PULL_NONE \
126 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
127 #define PIN_SLPM_PULL_UP \
128 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
129 #define PIN_SLPM_PULL_DOWN \
130 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
131
132 #define PIN_SLPM_DIR_SHIFT 19
133 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
134 #define PIN_SLPM_DIR(x) \
135 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
136 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
137 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
138
139 #define PIN_SLPM_VAL_SHIFT 21
140 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
141 #define PIN_SLPM_VAL(x) \
142 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
143 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
144 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
145
146 #define PIN_SLPM_PDIS_SHIFT 23
147 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
148 #define PIN_SLPM_PDIS(x) \
149 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
150 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
151 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
152 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
153
154 #define PIN_LOWEMI_SHIFT 25
155 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
156 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
157 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
158 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
159
160 #define PIN_GPIOMODE_SHIFT 26
161 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
162 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
163 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
164 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
165
166 #define PIN_SLEEPMODE_SHIFT 27
167 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
168 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
169 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
170 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
171
172
173 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
174 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
175 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
176 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
177 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
178 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
179
180 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
181 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
182 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
183 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
184 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
185
186 #define PIN_CFG_DEFAULT (0)
187
188 #define PIN_CFG(num, alt) \
189 (PIN_CFG_DEFAULT |\
190 (PIN_NUM(num) | PIN_##alt))
191
192 #define PIN_CFG_INPUT(num, alt, pull) \
193 (PIN_CFG_DEFAULT |\
194 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
195
196 #define PIN_CFG_OUTPUT(num, alt, val) \
197 (PIN_CFG_DEFAULT |\
198 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
199
200 /*
201 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
202 * the "gpio" namespace for generic and cross-machine functions
203 */
204
205 #define GPIO_BLOCK_SHIFT 5
206 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
207 #define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)
208
209 /* Register in the logic block */
210 #define NMK_GPIO_DAT 0x00
211 #define NMK_GPIO_DATS 0x04
212 #define NMK_GPIO_DATC 0x08
213 #define NMK_GPIO_PDIS 0x0c
214 #define NMK_GPIO_DIR 0x10
215 #define NMK_GPIO_DIRS 0x14
216 #define NMK_GPIO_DIRC 0x18
217 #define NMK_GPIO_SLPC 0x1c
218 #define NMK_GPIO_AFSLA 0x20
219 #define NMK_GPIO_AFSLB 0x24
220 #define NMK_GPIO_LOWEMI 0x28
221
222 #define NMK_GPIO_RIMSC 0x40
223 #define NMK_GPIO_FIMSC 0x44
224 #define NMK_GPIO_IS 0x48
225 #define NMK_GPIO_IC 0x4c
226 #define NMK_GPIO_RWIMSC 0x50
227 #define NMK_GPIO_FWIMSC 0x54
228 #define NMK_GPIO_WKS 0x58
229 /* These appear in DB8540 and later ASICs */
230 #define NMK_GPIO_EDGELEVEL 0x5C
231 #define NMK_GPIO_LEVEL 0x60
232
233
234 /* Pull up/down values */
235 enum nmk_gpio_pull {
236 NMK_GPIO_PULL_NONE,
237 NMK_GPIO_PULL_UP,
238 NMK_GPIO_PULL_DOWN,
239 };
240
241 /* Sleep mode */
242 enum nmk_gpio_slpm {
243 NMK_GPIO_SLPM_INPUT,
244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
245 NMK_GPIO_SLPM_NOCHANGE,
246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
247 };
248
249 struct nmk_gpio_chip {
250 struct gpio_chip chip;
251 struct irq_chip irqchip;
252 void __iomem *addr;
253 struct clk *clk;
254 unsigned int bank;
255 unsigned int parent_irq;
256 int latent_parent_irq;
257 u32 (*get_latent_status)(unsigned int bank);
258 void (*set_ioforce)(bool enable);
259 spinlock_t lock;
260 bool sleepmode;
261 /* Keep track of configured edges */
262 u32 edge_rising;
263 u32 edge_falling;
264 u32 real_wake;
265 u32 rwimsc;
266 u32 fwimsc;
267 u32 rimsc;
268 u32 fimsc;
269 u32 pull_up;
270 u32 lowemi;
271 };
272
273 /**
274 * struct nmk_pinctrl - state container for the Nomadik pin controller
275 * @dev: containing device pointer
276 * @pctl: corresponding pin controller device
277 * @soc: SoC data for this specific chip
278 * @prcm_base: PRCM register range virtual base
279 */
280 struct nmk_pinctrl {
281 struct device *dev;
282 struct pinctrl_dev *pctl;
283 const struct nmk_pinctrl_soc_data *soc;
284 void __iomem *prcm_base;
285 };
286
287 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
288
289 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
290
291 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
292
293 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
294 unsigned offset, int gpio_mode)
295 {
296 u32 afunc, bfunc;
297
298 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
299 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
300 if (gpio_mode & NMK_GPIO_ALT_A)
301 afunc |= BIT(offset);
302 if (gpio_mode & NMK_GPIO_ALT_B)
303 bfunc |= BIT(offset);
304 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
305 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
306 }
307
308 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
309 unsigned offset, enum nmk_gpio_slpm mode)
310 {
311 u32 slpm;
312
313 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
314 if (mode == NMK_GPIO_SLPM_NOCHANGE)
315 slpm |= BIT(offset);
316 else
317 slpm &= ~BIT(offset);
318 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
319 }
320
321 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
322 unsigned offset, enum nmk_gpio_pull pull)
323 {
324 u32 pdis;
325
326 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
327 if (pull == NMK_GPIO_PULL_NONE) {
328 pdis |= BIT(offset);
329 nmk_chip->pull_up &= ~BIT(offset);
330 } else {
331 pdis &= ~BIT(offset);
332 }
333
334 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
335
336 if (pull == NMK_GPIO_PULL_UP) {
337 nmk_chip->pull_up |= BIT(offset);
338 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
339 } else if (pull == NMK_GPIO_PULL_DOWN) {
340 nmk_chip->pull_up &= ~BIT(offset);
341 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
342 }
343 }
344
345 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
346 unsigned offset, bool lowemi)
347 {
348 bool enabled = nmk_chip->lowemi & BIT(offset);
349
350 if (lowemi == enabled)
351 return;
352
353 if (lowemi)
354 nmk_chip->lowemi |= BIT(offset);
355 else
356 nmk_chip->lowemi &= ~BIT(offset);
357
358 writel_relaxed(nmk_chip->lowemi,
359 nmk_chip->addr + NMK_GPIO_LOWEMI);
360 }
361
362 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
363 unsigned offset)
364 {
365 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
366 }
367
368 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
369 unsigned offset, int val)
370 {
371 if (val)
372 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
373 else
374 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
375 }
376
377 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
378 unsigned offset, int val)
379 {
380 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
381 __nmk_gpio_set_output(nmk_chip, offset, val);
382 }
383
384 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
385 unsigned offset, int gpio_mode,
386 bool glitch)
387 {
388 u32 rwimsc = nmk_chip->rwimsc;
389 u32 fwimsc = nmk_chip->fwimsc;
390
391 if (glitch && nmk_chip->set_ioforce) {
392 u32 bit = BIT(offset);
393
394 /* Prevent spurious wakeups */
395 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
396 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
397
398 nmk_chip->set_ioforce(true);
399 }
400
401 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
402
403 if (glitch && nmk_chip->set_ioforce) {
404 nmk_chip->set_ioforce(false);
405
406 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
407 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
408 }
409 }
410
411 static void
412 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
413 {
414 u32 falling = nmk_chip->fimsc & BIT(offset);
415 u32 rising = nmk_chip->rimsc & BIT(offset);
416 int gpio = nmk_chip->chip.base + offset;
417 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);
418 struct irq_data *d = irq_get_irq_data(irq);
419
420 if (!rising && !falling)
421 return;
422
423 if (!d || !irqd_irq_disabled(d))
424 return;
425
426 if (rising) {
427 nmk_chip->rimsc &= ~BIT(offset);
428 writel_relaxed(nmk_chip->rimsc,
429 nmk_chip->addr + NMK_GPIO_RIMSC);
430 }
431
432 if (falling) {
433 nmk_chip->fimsc &= ~BIT(offset);
434 writel_relaxed(nmk_chip->fimsc,
435 nmk_chip->addr + NMK_GPIO_FIMSC);
436 }
437
438 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
439 }
440
441 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
442 {
443 u32 val;
444
445 val = readl(reg);
446 val = ((val & ~mask) | (value & mask));
447 writel(val, reg);
448 }
449
450 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
451 unsigned offset, unsigned alt_num)
452 {
453 int i;
454 u16 reg;
455 u8 bit;
456 u8 alt_index;
457 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
458 const u16 *gpiocr_regs;
459
460 if (!npct->prcm_base)
461 return;
462
463 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
464 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
465 alt_num);
466 return;
467 }
468
469 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
470 if (npct->soc->altcx_pins[i].pin == offset)
471 break;
472 }
473 if (i == npct->soc->npins_altcx) {
474 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
475 offset);
476 return;
477 }
478
479 pin_desc = npct->soc->altcx_pins + i;
480 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
481
482 /*
483 * If alt_num is NULL, just clear current ALTCx selection
484 * to make sure we come back to a pure ALTC selection
485 */
486 if (!alt_num) {
487 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
488 if (pin_desc->altcx[i].used == true) {
489 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
490 bit = pin_desc->altcx[i].control_bit;
491 if (readl(npct->prcm_base + reg) & BIT(bit)) {
492 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
493 dev_dbg(npct->dev,
494 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
495 offset, i+1);
496 }
497 }
498 }
499 return;
500 }
501
502 alt_index = alt_num - 1;
503 if (pin_desc->altcx[alt_index].used == false) {
504 dev_warn(npct->dev,
505 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
506 offset, alt_num);
507 return;
508 }
509
510 /*
511 * Check if any other ALTCx functions are activated on this pin
512 * and disable it first.
513 */
514 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
515 if (i == alt_index)
516 continue;
517 if (pin_desc->altcx[i].used == true) {
518 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
519 bit = pin_desc->altcx[i].control_bit;
520 if (readl(npct->prcm_base + reg) & BIT(bit)) {
521 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
522 dev_dbg(npct->dev,
523 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
524 offset, i+1);
525 }
526 }
527 }
528
529 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
530 bit = pin_desc->altcx[alt_index].control_bit;
531 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
532 offset, alt_index+1);
533 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
534 }
535
536 /*
537 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
538 * - Save SLPM registers
539 * - Set SLPM=0 for the IOs you want to switch and others to 1
540 * - Configure the GPIO registers for the IOs that are being switched
541 * - Set IOFORCE=1
542 * - Modify the AFLSA/B registers for the IOs that are being switched
543 * - Set IOFORCE=0
544 * - Restore SLPM registers
545 * - Any spurious wake up event during switch sequence to be ignored and
546 * cleared
547 */
548 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
549 {
550 int i;
551
552 for (i = 0; i < NUM_BANKS; i++) {
553 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
554 unsigned int temp = slpm[i];
555
556 if (!chip)
557 break;
558
559 clk_enable(chip->clk);
560
561 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
562 writel(temp, chip->addr + NMK_GPIO_SLPC);
563 }
564 }
565
566 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
567 {
568 int i;
569
570 for (i = 0; i < NUM_BANKS; i++) {
571 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
572
573 if (!chip)
574 break;
575
576 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
577
578 clk_disable(chip->clk);
579 }
580 }
581
582 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
583 {
584 int i;
585 u16 reg;
586 u8 bit;
587 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
588 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
589 const u16 *gpiocr_regs;
590
591 if (!npct->prcm_base)
592 return NMK_GPIO_ALT_C;
593
594 for (i = 0; i < npct->soc->npins_altcx; i++) {
595 if (npct->soc->altcx_pins[i].pin == gpio)
596 break;
597 }
598 if (i == npct->soc->npins_altcx)
599 return NMK_GPIO_ALT_C;
600
601 pin_desc = npct->soc->altcx_pins + i;
602 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
603 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
604 if (pin_desc->altcx[i].used == true) {
605 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
606 bit = pin_desc->altcx[i].control_bit;
607 if (readl(npct->prcm_base + reg) & BIT(bit))
608 return NMK_GPIO_ALT_C+i+1;
609 }
610 }
611 return NMK_GPIO_ALT_C;
612 }
613
614 /* IRQ functions */
615
616 static void nmk_gpio_irq_ack(struct irq_data *d)
617 {
618 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
619 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
620
621 clk_enable(nmk_chip->clk);
622 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
623 clk_disable(nmk_chip->clk);
624 }
625
626 enum nmk_gpio_irq_type {
627 NORMAL,
628 WAKE,
629 };
630
631 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
632 int offset, enum nmk_gpio_irq_type which,
633 bool enable)
634 {
635 u32 *rimscval;
636 u32 *fimscval;
637 u32 rimscreg;
638 u32 fimscreg;
639
640 if (which == NORMAL) {
641 rimscreg = NMK_GPIO_RIMSC;
642 fimscreg = NMK_GPIO_FIMSC;
643 rimscval = &nmk_chip->rimsc;
644 fimscval = &nmk_chip->fimsc;
645 } else {
646 rimscreg = NMK_GPIO_RWIMSC;
647 fimscreg = NMK_GPIO_FWIMSC;
648 rimscval = &nmk_chip->rwimsc;
649 fimscval = &nmk_chip->fwimsc;
650 }
651
652 /* we must individually set/clear the two edges */
653 if (nmk_chip->edge_rising & BIT(offset)) {
654 if (enable)
655 *rimscval |= BIT(offset);
656 else
657 *rimscval &= ~BIT(offset);
658 writel(*rimscval, nmk_chip->addr + rimscreg);
659 }
660 if (nmk_chip->edge_falling & BIT(offset)) {
661 if (enable)
662 *fimscval |= BIT(offset);
663 else
664 *fimscval &= ~BIT(offset);
665 writel(*fimscval, nmk_chip->addr + fimscreg);
666 }
667 }
668
669 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
670 int offset, bool on)
671 {
672 /*
673 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
674 * disabled, since setting SLPM to 1 increases power consumption, and
675 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
676 */
677 if (nmk_chip->sleepmode && on) {
678 __nmk_gpio_set_slpm(nmk_chip, offset,
679 NMK_GPIO_SLPM_WAKEUP_ENABLE);
680 }
681
682 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
683 }
684
685 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
686 {
687 struct nmk_gpio_chip *nmk_chip;
688 unsigned long flags;
689
690 nmk_chip = irq_data_get_irq_chip_data(d);
691 if (!nmk_chip)
692 return -EINVAL;
693
694 clk_enable(nmk_chip->clk);
695 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
696 spin_lock(&nmk_chip->lock);
697
698 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
699
700 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
701 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
702
703 spin_unlock(&nmk_chip->lock);
704 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
705 clk_disable(nmk_chip->clk);
706
707 return 0;
708 }
709
710 static void nmk_gpio_irq_mask(struct irq_data *d)
711 {
712 nmk_gpio_irq_maskunmask(d, false);
713 }
714
715 static void nmk_gpio_irq_unmask(struct irq_data *d)
716 {
717 nmk_gpio_irq_maskunmask(d, true);
718 }
719
720 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
721 {
722 struct nmk_gpio_chip *nmk_chip;
723 unsigned long flags;
724
725 nmk_chip = irq_data_get_irq_chip_data(d);
726 if (!nmk_chip)
727 return -EINVAL;
728
729 clk_enable(nmk_chip->clk);
730 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
731 spin_lock(&nmk_chip->lock);
732
733 if (irqd_irq_disabled(d))
734 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
735
736 if (on)
737 nmk_chip->real_wake |= BIT(d->hwirq);
738 else
739 nmk_chip->real_wake &= ~BIT(d->hwirq);
740
741 spin_unlock(&nmk_chip->lock);
742 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
743 clk_disable(nmk_chip->clk);
744
745 return 0;
746 }
747
748 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
749 {
750 bool enabled = !irqd_irq_disabled(d);
751 bool wake = irqd_is_wakeup_set(d);
752 struct nmk_gpio_chip *nmk_chip;
753 unsigned long flags;
754
755 nmk_chip = irq_data_get_irq_chip_data(d);
756 if (!nmk_chip)
757 return -EINVAL;
758 if (type & IRQ_TYPE_LEVEL_HIGH)
759 return -EINVAL;
760 if (type & IRQ_TYPE_LEVEL_LOW)
761 return -EINVAL;
762
763 clk_enable(nmk_chip->clk);
764 spin_lock_irqsave(&nmk_chip->lock, flags);
765
766 if (enabled)
767 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
768
769 if (enabled || wake)
770 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
771
772 nmk_chip->edge_rising &= ~BIT(d->hwirq);
773 if (type & IRQ_TYPE_EDGE_RISING)
774 nmk_chip->edge_rising |= BIT(d->hwirq);
775
776 nmk_chip->edge_falling &= ~BIT(d->hwirq);
777 if (type & IRQ_TYPE_EDGE_FALLING)
778 nmk_chip->edge_falling |= BIT(d->hwirq);
779
780 if (enabled)
781 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
782
783 if (enabled || wake)
784 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
785
786 spin_unlock_irqrestore(&nmk_chip->lock, flags);
787 clk_disable(nmk_chip->clk);
788
789 return 0;
790 }
791
792 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
793 {
794 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
795
796 clk_enable(nmk_chip->clk);
797 nmk_gpio_irq_unmask(d);
798 return 0;
799 }
800
801 static void nmk_gpio_irq_shutdown(struct irq_data *d)
802 {
803 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
804
805 nmk_gpio_irq_mask(d);
806 clk_disable(nmk_chip->clk);
807 }
808
809 static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
810 {
811 struct irq_chip *host_chip = irq_desc_get_chip(desc);
812 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
813
814 chained_irq_enter(host_chip, desc);
815
816 while (status) {
817 int bit = __ffs(status);
818
819 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit));
820 status &= ~BIT(bit);
821 }
822
823 chained_irq_exit(host_chip, desc);
824 }
825
826 static void nmk_gpio_irq_handler(struct irq_desc *desc)
827 {
828 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
829 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
830 u32 status;
831
832 clk_enable(nmk_chip->clk);
833 status = readl(nmk_chip->addr + NMK_GPIO_IS);
834 clk_disable(nmk_chip->clk);
835
836 __nmk_gpio_irq_handler(desc, status);
837 }
838
839 static void nmk_gpio_latent_irq_handler(struct irq_desc *desc)
840 {
841 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
842 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
843 u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
844
845 __nmk_gpio_irq_handler(desc, status);
846 }
847
848 /* I/O Functions */
849
850 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
851 {
852 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
853 int dir;
854
855 clk_enable(nmk_chip->clk);
856
857 dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
858
859 clk_disable(nmk_chip->clk);
860
861 return dir;
862 }
863
864 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
865 {
866 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
867
868 clk_enable(nmk_chip->clk);
869
870 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
871
872 clk_disable(nmk_chip->clk);
873
874 return 0;
875 }
876
877 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
878 {
879 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
880 int value;
881
882 clk_enable(nmk_chip->clk);
883
884 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
885
886 clk_disable(nmk_chip->clk);
887
888 return value;
889 }
890
891 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
892 int val)
893 {
894 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
895
896 clk_enable(nmk_chip->clk);
897
898 __nmk_gpio_set_output(nmk_chip, offset, val);
899
900 clk_disable(nmk_chip->clk);
901 }
902
903 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
904 int val)
905 {
906 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
907
908 clk_enable(nmk_chip->clk);
909
910 __nmk_gpio_make_output(nmk_chip, offset, val);
911
912 clk_disable(nmk_chip->clk);
913
914 return 0;
915 }
916
917 #ifdef CONFIG_DEBUG_FS
918 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
919 {
920 u32 afunc, bfunc;
921
922 clk_enable(nmk_chip->clk);
923
924 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
925 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
926
927 clk_disable(nmk_chip->clk);
928
929 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
930 }
931
932 #include <linux/seq_file.h>
933
934 static void nmk_gpio_dbg_show_one(struct seq_file *s,
935 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
936 unsigned offset, unsigned gpio)
937 {
938 const char *label = gpiochip_is_requested(chip, offset);
939 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
940 int mode;
941 bool is_out;
942 bool data_out;
943 bool pull;
944 const char *modes[] = {
945 [NMK_GPIO_ALT_GPIO] = "gpio",
946 [NMK_GPIO_ALT_A] = "altA",
947 [NMK_GPIO_ALT_B] = "altB",
948 [NMK_GPIO_ALT_C] = "altC",
949 [NMK_GPIO_ALT_C+1] = "altC1",
950 [NMK_GPIO_ALT_C+2] = "altC2",
951 [NMK_GPIO_ALT_C+3] = "altC3",
952 [NMK_GPIO_ALT_C+4] = "altC4",
953 };
954 const char *pulls[] = {
955 "none ",
956 "pull down",
957 "pull up ",
958 };
959
960 clk_enable(nmk_chip->clk);
961 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
962 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
963 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
964 mode = nmk_gpio_get_mode(nmk_chip, offset);
965 if ((mode == NMK_GPIO_ALT_C) && pctldev)
966 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
967
968 if (is_out) {
969 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
970 gpio,
971 label ?: "(none)",
972 data_out ? "hi" : "lo",
973 (mode < 0) ? "unknown" : modes[mode]);
974 } else {
975 int irq = gpio_to_irq(gpio);
976 struct irq_desc *desc = irq_to_desc(irq);
977 int pullidx = 0;
978 int val;
979
980 if (pull)
981 pullidx = data_out ? 2 : 1;
982
983 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
984 gpio,
985 label ?: "(none)",
986 pulls[pullidx],
987 (mode < 0) ? "unknown" : modes[mode]);
988
989 val = nmk_gpio_get_input(chip, offset);
990 seq_printf(s, " VAL %d", val);
991
992 /*
993 * This races with request_irq(), set_irq_type(),
994 * and set_irq_wake() ... but those are "rare".
995 */
996 if (irq > 0 && desc && desc->action) {
997 char *trigger;
998
999 if (nmk_chip->edge_rising & BIT(offset))
1000 trigger = "edge-rising";
1001 else if (nmk_chip->edge_falling & BIT(offset))
1002 trigger = "edge-falling";
1003 else
1004 trigger = "edge-undefined";
1005
1006 seq_printf(s, " irq-%d %s%s",
1007 irq, trigger,
1008 irqd_is_wakeup_set(&desc->irq_data)
1009 ? " wakeup" : "");
1010 }
1011 }
1012 clk_disable(nmk_chip->clk);
1013 }
1014
1015 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1016 {
1017 unsigned i;
1018 unsigned gpio = chip->base;
1019
1020 for (i = 0; i < chip->ngpio; i++, gpio++) {
1021 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1022 seq_printf(s, "\n");
1023 }
1024 }
1025
1026 #else
1027 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1028 struct pinctrl_dev *pctldev,
1029 struct gpio_chip *chip,
1030 unsigned offset, unsigned gpio)
1031 {
1032 }
1033 #define nmk_gpio_dbg_show NULL
1034 #endif
1035
1036 /*
1037 * We will allocate memory for the state container using devm* allocators
1038 * binding to the first device reaching this point, it doesn't matter if
1039 * it is the pin controller or GPIO driver. However we need to use the right
1040 * platform device when looking up resources so pay attention to pdev.
1041 */
1042 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1043 struct platform_device *pdev)
1044 {
1045 struct nmk_gpio_chip *nmk_chip;
1046 struct platform_device *gpio_pdev;
1047 struct gpio_chip *chip;
1048 struct resource *res;
1049 struct clk *clk;
1050 void __iomem *base;
1051 u32 id;
1052
1053 gpio_pdev = of_find_device_by_node(np);
1054 if (!gpio_pdev) {
1055 pr_err("populate \"%s\": device not found\n", np->name);
1056 return ERR_PTR(-ENODEV);
1057 }
1058 if (of_property_read_u32(np, "gpio-bank", &id)) {
1059 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1060 return ERR_PTR(-EINVAL);
1061 }
1062
1063 /* Already populated? */
1064 nmk_chip = nmk_gpio_chips[id];
1065 if (nmk_chip)
1066 return nmk_chip;
1067
1068 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1069 if (!nmk_chip)
1070 return ERR_PTR(-ENOMEM);
1071
1072 nmk_chip->bank = id;
1073 chip = &nmk_chip->chip;
1074 chip->base = id * NMK_GPIO_PER_CHIP;
1075 chip->ngpio = NMK_GPIO_PER_CHIP;
1076 chip->label = dev_name(&gpio_pdev->dev);
1077 chip->parent = &gpio_pdev->dev;
1078
1079 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1080 base = devm_ioremap_resource(&pdev->dev, res);
1081 if (IS_ERR(base))
1082 return base;
1083 nmk_chip->addr = base;
1084
1085 clk = clk_get(&gpio_pdev->dev, NULL);
1086 if (IS_ERR(clk))
1087 return (void *) clk;
1088 clk_prepare(clk);
1089 nmk_chip->clk = clk;
1090
1091 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1092 nmk_gpio_chips[id] = nmk_chip;
1093 return nmk_chip;
1094 }
1095
1096 static int nmk_gpio_probe(struct platform_device *dev)
1097 {
1098 struct device_node *np = dev->dev.of_node;
1099 struct nmk_gpio_chip *nmk_chip;
1100 struct gpio_chip *chip;
1101 struct irq_chip *irqchip;
1102 int latent_irq;
1103 bool supports_sleepmode;
1104 int irq;
1105 int ret;
1106
1107 nmk_chip = nmk_gpio_populate_chip(np, dev);
1108 if (IS_ERR(nmk_chip)) {
1109 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1110 return PTR_ERR(nmk_chip);
1111 }
1112
1113 if (of_get_property(np, "st,supports-sleepmode", NULL))
1114 supports_sleepmode = true;
1115 else
1116 supports_sleepmode = false;
1117
1118 /* Correct platform device ID */
1119 dev->id = nmk_chip->bank;
1120
1121 irq = platform_get_irq(dev, 0);
1122 if (irq < 0)
1123 return irq;
1124
1125 /* It's OK for this IRQ not to be present */
1126 latent_irq = platform_get_irq(dev, 1);
1127
1128 /*
1129 * The virt address in nmk_chip->addr is in the nomadik register space,
1130 * so we can simply convert the resource address, without remapping
1131 */
1132 nmk_chip->parent_irq = irq;
1133 nmk_chip->latent_parent_irq = latent_irq;
1134 nmk_chip->sleepmode = supports_sleepmode;
1135 spin_lock_init(&nmk_chip->lock);
1136
1137 chip = &nmk_chip->chip;
1138 chip->request = gpiochip_generic_request;
1139 chip->free = gpiochip_generic_free;
1140 chip->get_direction = nmk_gpio_get_dir;
1141 chip->direction_input = nmk_gpio_make_input;
1142 chip->get = nmk_gpio_get_input;
1143 chip->direction_output = nmk_gpio_make_output;
1144 chip->set = nmk_gpio_set_output;
1145 chip->dbg_show = nmk_gpio_dbg_show;
1146 chip->can_sleep = false;
1147 chip->owner = THIS_MODULE;
1148
1149 irqchip = &nmk_chip->irqchip;
1150 irqchip->irq_ack = nmk_gpio_irq_ack;
1151 irqchip->irq_mask = nmk_gpio_irq_mask;
1152 irqchip->irq_unmask = nmk_gpio_irq_unmask;
1153 irqchip->irq_set_type = nmk_gpio_irq_set_type;
1154 irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
1155 irqchip->irq_startup = nmk_gpio_irq_startup;
1156 irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
1157 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
1158 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
1159 dev->id,
1160 chip->base,
1161 chip->base + chip->ngpio - 1);
1162
1163 clk_enable(nmk_chip->clk);
1164 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1165 clk_disable(nmk_chip->clk);
1166 chip->of_node = np;
1167
1168 ret = gpiochip_add_data(chip, nmk_chip);
1169 if (ret)
1170 return ret;
1171
1172 platform_set_drvdata(dev, nmk_chip);
1173
1174 /*
1175 * Let the generic code handle this edge IRQ, the the chained
1176 * handler will perform the actual work of handling the parent
1177 * interrupt.
1178 */
1179 ret = gpiochip_irqchip_add(chip,
1180 irqchip,
1181 0,
1182 handle_edge_irq,
1183 IRQ_TYPE_EDGE_FALLING);
1184 if (ret) {
1185 dev_err(&dev->dev, "could not add irqchip\n");
1186 gpiochip_remove(&nmk_chip->chip);
1187 return -ENODEV;
1188 }
1189 /* Then register the chain on the parent IRQ */
1190 gpiochip_set_chained_irqchip(chip,
1191 irqchip,
1192 nmk_chip->parent_irq,
1193 nmk_gpio_irq_handler);
1194 if (nmk_chip->latent_parent_irq > 0)
1195 gpiochip_set_chained_irqchip(chip,
1196 irqchip,
1197 nmk_chip->latent_parent_irq,
1198 nmk_gpio_latent_irq_handler);
1199
1200 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1201
1202 return 0;
1203 }
1204
1205 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1206 {
1207 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1208
1209 return npct->soc->ngroups;
1210 }
1211
1212 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1213 unsigned selector)
1214 {
1215 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1216
1217 return npct->soc->groups[selector].name;
1218 }
1219
1220 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1221 const unsigned **pins,
1222 unsigned *num_pins)
1223 {
1224 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1225
1226 *pins = npct->soc->groups[selector].pins;
1227 *num_pins = npct->soc->groups[selector].npins;
1228 return 0;
1229 }
1230
1231 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1232 {
1233 int i;
1234 struct nmk_gpio_chip *nmk_gpio;
1235
1236 for(i = 0; i < NMK_MAX_BANKS; i++) {
1237 nmk_gpio = nmk_gpio_chips[i];
1238 if (!nmk_gpio)
1239 continue;
1240 if (pin >= nmk_gpio->chip.base &&
1241 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1242 return nmk_gpio;
1243 }
1244 return NULL;
1245 }
1246
1247 static struct gpio_chip *find_gc_from_pin(unsigned pin)
1248 {
1249 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1250
1251 if (nmk_gpio)
1252 return &nmk_gpio->chip;
1253 return NULL;
1254 }
1255
1256 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1257 unsigned offset)
1258 {
1259 struct gpio_chip *chip = find_gc_from_pin(offset);
1260
1261 if (!chip) {
1262 seq_printf(s, "invalid pin offset");
1263 return;
1264 }
1265 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1266 }
1267
1268 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1269 unsigned *num_maps, const char *group,
1270 const char *function)
1271 {
1272 if (*num_maps == *reserved_maps)
1273 return -ENOSPC;
1274
1275 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1276 (*map)[*num_maps].data.mux.group = group;
1277 (*map)[*num_maps].data.mux.function = function;
1278 (*num_maps)++;
1279
1280 return 0;
1281 }
1282
1283 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1284 unsigned *reserved_maps,
1285 unsigned *num_maps, const char *group,
1286 unsigned long *configs, unsigned num_configs)
1287 {
1288 unsigned long *dup_configs;
1289
1290 if (*num_maps == *reserved_maps)
1291 return -ENOSPC;
1292
1293 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1294 GFP_KERNEL);
1295 if (!dup_configs)
1296 return -ENOMEM;
1297
1298 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1299
1300 (*map)[*num_maps].data.configs.group_or_pin = group;
1301 (*map)[*num_maps].data.configs.configs = dup_configs;
1302 (*map)[*num_maps].data.configs.num_configs = num_configs;
1303 (*num_maps)++;
1304
1305 return 0;
1306 }
1307
1308 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1309 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1310 .size = ARRAY_SIZE(y), }
1311
1312 static const unsigned long nmk_pin_input_modes[] = {
1313 PIN_INPUT_NOPULL,
1314 PIN_INPUT_PULLUP,
1315 PIN_INPUT_PULLDOWN,
1316 };
1317
1318 static const unsigned long nmk_pin_output_modes[] = {
1319 PIN_OUTPUT_LOW,
1320 PIN_OUTPUT_HIGH,
1321 PIN_DIR_OUTPUT,
1322 };
1323
1324 static const unsigned long nmk_pin_sleep_modes[] = {
1325 PIN_SLEEPMODE_DISABLED,
1326 PIN_SLEEPMODE_ENABLED,
1327 };
1328
1329 static const unsigned long nmk_pin_sleep_input_modes[] = {
1330 PIN_SLPM_INPUT_NOPULL,
1331 PIN_SLPM_INPUT_PULLUP,
1332 PIN_SLPM_INPUT_PULLDOWN,
1333 PIN_SLPM_DIR_INPUT,
1334 };
1335
1336 static const unsigned long nmk_pin_sleep_output_modes[] = {
1337 PIN_SLPM_OUTPUT_LOW,
1338 PIN_SLPM_OUTPUT_HIGH,
1339 PIN_SLPM_DIR_OUTPUT,
1340 };
1341
1342 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1343 PIN_SLPM_WAKEUP_DISABLE,
1344 PIN_SLPM_WAKEUP_ENABLE,
1345 };
1346
1347 static const unsigned long nmk_pin_gpio_modes[] = {
1348 PIN_GPIOMODE_DISABLED,
1349 PIN_GPIOMODE_ENABLED,
1350 };
1351
1352 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1353 PIN_SLPM_PDIS_DISABLED,
1354 PIN_SLPM_PDIS_ENABLED,
1355 };
1356
1357 struct nmk_cfg_param {
1358 const char *property;
1359 unsigned long config;
1360 const unsigned long *choice;
1361 int size;
1362 };
1363
1364 static const struct nmk_cfg_param nmk_cfg_params[] = {
1365 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1366 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1367 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1368 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1369 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1370 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1371 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1372 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1373 };
1374
1375 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1376 {
1377 int ret = 0;
1378
1379 if (nmk_cfg_params[index].choice == NULL)
1380 *config = nmk_cfg_params[index].config;
1381 else {
1382 /* test if out of range */
1383 if (val < nmk_cfg_params[index].size) {
1384 *config = nmk_cfg_params[index].config |
1385 nmk_cfg_params[index].choice[val];
1386 }
1387 }
1388 return ret;
1389 }
1390
1391 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1392 {
1393 int i, pin_number;
1394 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1395
1396 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1397 for (i = 0; i < npct->soc->npins; i++)
1398 if (npct->soc->pins[i].number == pin_number)
1399 return npct->soc->pins[i].name;
1400 return NULL;
1401 }
1402
1403 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1404 unsigned long *configs)
1405 {
1406 bool has_config = 0;
1407 unsigned long cfg = 0;
1408 int i, val, ret;
1409
1410 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1411 ret = of_property_read_u32(np,
1412 nmk_cfg_params[i].property, &val);
1413 if (ret != -EINVAL) {
1414 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1415 *configs |= cfg;
1416 has_config = 1;
1417 }
1418 }
1419 }
1420
1421 return has_config;
1422 }
1423
1424 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1425 struct device_node *np,
1426 struct pinctrl_map **map,
1427 unsigned *reserved_maps,
1428 unsigned *num_maps)
1429 {
1430 int ret;
1431 const char *function = NULL;
1432 unsigned long configs = 0;
1433 bool has_config = 0;
1434 struct property *prop;
1435 struct device_node *np_config;
1436
1437 ret = of_property_read_string(np, "function", &function);
1438 if (ret >= 0) {
1439 const char *group;
1440
1441 ret = of_property_count_strings(np, "groups");
1442 if (ret < 0)
1443 goto exit;
1444
1445 ret = pinctrl_utils_reserve_map(pctldev, map,
1446 reserved_maps,
1447 num_maps, ret);
1448 if (ret < 0)
1449 goto exit;
1450
1451 of_property_for_each_string(np, "groups", prop, group) {
1452 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1453 group, function);
1454 if (ret < 0)
1455 goto exit;
1456 }
1457 }
1458
1459 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1460 np_config = of_parse_phandle(np, "ste,config", 0);
1461 if (np_config)
1462 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1463 if (has_config) {
1464 const char *gpio_name;
1465 const char *pin;
1466
1467 ret = of_property_count_strings(np, "pins");
1468 if (ret < 0)
1469 goto exit;
1470 ret = pinctrl_utils_reserve_map(pctldev, map,
1471 reserved_maps,
1472 num_maps, ret);
1473 if (ret < 0)
1474 goto exit;
1475
1476 of_property_for_each_string(np, "pins", prop, pin) {
1477 gpio_name = nmk_find_pin_name(pctldev, pin);
1478
1479 ret = nmk_dt_add_map_configs(map, reserved_maps,
1480 num_maps,
1481 gpio_name, &configs, 1);
1482 if (ret < 0)
1483 goto exit;
1484 }
1485 }
1486
1487 exit:
1488 return ret;
1489 }
1490
1491 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1492 struct device_node *np_config,
1493 struct pinctrl_map **map, unsigned *num_maps)
1494 {
1495 unsigned reserved_maps;
1496 struct device_node *np;
1497 int ret;
1498
1499 reserved_maps = 0;
1500 *map = NULL;
1501 *num_maps = 0;
1502
1503 for_each_child_of_node(np_config, np) {
1504 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1505 &reserved_maps, num_maps);
1506 if (ret < 0) {
1507 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1508 return ret;
1509 }
1510 }
1511
1512 return 0;
1513 }
1514
1515 static const struct pinctrl_ops nmk_pinctrl_ops = {
1516 .get_groups_count = nmk_get_groups_cnt,
1517 .get_group_name = nmk_get_group_name,
1518 .get_group_pins = nmk_get_group_pins,
1519 .pin_dbg_show = nmk_pin_dbg_show,
1520 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1521 .dt_free_map = pinctrl_utils_free_map,
1522 };
1523
1524 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1525 {
1526 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1527
1528 return npct->soc->nfunctions;
1529 }
1530
1531 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1532 unsigned function)
1533 {
1534 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1535
1536 return npct->soc->functions[function].name;
1537 }
1538
1539 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1540 unsigned function,
1541 const char * const **groups,
1542 unsigned * const num_groups)
1543 {
1544 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1545
1546 *groups = npct->soc->functions[function].groups;
1547 *num_groups = npct->soc->functions[function].ngroups;
1548
1549 return 0;
1550 }
1551
1552 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1553 unsigned group)
1554 {
1555 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1556 const struct nmk_pingroup *g;
1557 static unsigned int slpm[NUM_BANKS];
1558 unsigned long flags = 0;
1559 bool glitch;
1560 int ret = -EINVAL;
1561 int i;
1562
1563 g = &npct->soc->groups[group];
1564
1565 if (g->altsetting < 0)
1566 return -EINVAL;
1567
1568 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1569
1570 /*
1571 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1572 * we may pass through an undesired state. In this case we take
1573 * some extra care.
1574 *
1575 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1576 * - Save SLPM registers (since we have a shadow register in the
1577 * nmk_chip we're using that as backup)
1578 * - Set SLPM=0 for the IOs you want to switch and others to 1
1579 * - Configure the GPIO registers for the IOs that are being switched
1580 * - Set IOFORCE=1
1581 * - Modify the AFLSA/B registers for the IOs that are being switched
1582 * - Set IOFORCE=0
1583 * - Restore SLPM registers
1584 * - Any spurious wake up event during switch sequence to be ignored
1585 * and cleared
1586 *
1587 * We REALLY need to save ALL slpm registers, because the external
1588 * IOFORCE will switch *all* ports to their sleepmode setting to as
1589 * to avoid glitches. (Not just one port!)
1590 */
1591 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1592
1593 if (glitch) {
1594 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1595
1596 /* Initially don't put any pins to sleep when switching */
1597 memset(slpm, 0xff, sizeof(slpm));
1598
1599 /*
1600 * Then mask the pins that need to be sleeping now when we're
1601 * switching to the ALT C function.
1602 */
1603 for (i = 0; i < g->npins; i++)
1604 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1605 nmk_gpio_glitch_slpm_init(slpm);
1606 }
1607
1608 for (i = 0; i < g->npins; i++) {
1609 struct nmk_gpio_chip *nmk_chip;
1610 unsigned bit;
1611
1612 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1613 if (!nmk_chip) {
1614 dev_err(npct->dev,
1615 "invalid pin offset %d in group %s at index %d\n",
1616 g->pins[i], g->name, i);
1617 goto out_glitch;
1618 }
1619 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1620
1621 clk_enable(nmk_chip->clk);
1622 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1623 /*
1624 * If the pin is switching to altfunc, and there was an
1625 * interrupt installed on it which has been lazy disabled,
1626 * actually mask the interrupt to prevent spurious interrupts
1627 * that would occur while the pin is under control of the
1628 * peripheral. Only SKE does this.
1629 */
1630 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1631
1632 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1633 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1634 clk_disable(nmk_chip->clk);
1635
1636 /*
1637 * Call PRCM GPIOCR config function in case ALTC
1638 * has been selected:
1639 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1640 * must be set.
1641 * - If selection is pure ALTC and previous selection was ALTCx,
1642 * then some bits in PRCM GPIOCR registers must be cleared.
1643 */
1644 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1645 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1646 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1647 }
1648
1649 /* When all pins are successfully reconfigured we get here */
1650 ret = 0;
1651
1652 out_glitch:
1653 if (glitch) {
1654 nmk_gpio_glitch_slpm_restore(slpm);
1655 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1656 }
1657
1658 return ret;
1659 }
1660
1661 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1662 struct pinctrl_gpio_range *range,
1663 unsigned offset)
1664 {
1665 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1666 struct nmk_gpio_chip *nmk_chip;
1667 struct gpio_chip *chip;
1668 unsigned bit;
1669
1670 if (!range) {
1671 dev_err(npct->dev, "invalid range\n");
1672 return -EINVAL;
1673 }
1674 if (!range->gc) {
1675 dev_err(npct->dev, "missing GPIO chip in range\n");
1676 return -EINVAL;
1677 }
1678 chip = range->gc;
1679 nmk_chip = gpiochip_get_data(chip);
1680
1681 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1682
1683 clk_enable(nmk_chip->clk);
1684 bit = offset % NMK_GPIO_PER_CHIP;
1685 /* There is no glitch when converting any pin to GPIO */
1686 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1687 clk_disable(nmk_chip->clk);
1688
1689 return 0;
1690 }
1691
1692 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1693 struct pinctrl_gpio_range *range,
1694 unsigned offset)
1695 {
1696 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1697
1698 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1699 /* Set the pin to some default state, GPIO is usually default */
1700 }
1701
1702 static const struct pinmux_ops nmk_pinmux_ops = {
1703 .get_functions_count = nmk_pmx_get_funcs_cnt,
1704 .get_function_name = nmk_pmx_get_func_name,
1705 .get_function_groups = nmk_pmx_get_func_groups,
1706 .set_mux = nmk_pmx_set,
1707 .gpio_request_enable = nmk_gpio_request_enable,
1708 .gpio_disable_free = nmk_gpio_disable_free,
1709 .strict = true,
1710 };
1711
1712 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1713 unsigned long *config)
1714 {
1715 /* Not implemented */
1716 return -EINVAL;
1717 }
1718
1719 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1720 unsigned long *configs, unsigned num_configs)
1721 {
1722 static const char *pullnames[] = {
1723 [NMK_GPIO_PULL_NONE] = "none",
1724 [NMK_GPIO_PULL_UP] = "up",
1725 [NMK_GPIO_PULL_DOWN] = "down",
1726 [3] /* illegal */ = "??"
1727 };
1728 static const char *slpmnames[] = {
1729 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1730 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1731 };
1732 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1733 struct nmk_gpio_chip *nmk_chip;
1734 unsigned bit;
1735 pin_cfg_t cfg;
1736 int pull, slpm, output, val, i;
1737 bool lowemi, gpiomode, sleep;
1738
1739 nmk_chip = find_nmk_gpio_from_pin(pin);
1740 if (!nmk_chip) {
1741 dev_err(npct->dev,
1742 "invalid pin offset %d\n", pin);
1743 return -EINVAL;
1744 }
1745
1746 for (i = 0; i < num_configs; i++) {
1747 /*
1748 * The pin config contains pin number and altfunction fields,
1749 * here we just ignore that part. It's being handled by the
1750 * framework and pinmux callback respectively.
1751 */
1752 cfg = (pin_cfg_t) configs[i];
1753 pull = PIN_PULL(cfg);
1754 slpm = PIN_SLPM(cfg);
1755 output = PIN_DIR(cfg);
1756 val = PIN_VAL(cfg);
1757 lowemi = PIN_LOWEMI(cfg);
1758 gpiomode = PIN_GPIOMODE(cfg);
1759 sleep = PIN_SLEEPMODE(cfg);
1760
1761 if (sleep) {
1762 int slpm_pull = PIN_SLPM_PULL(cfg);
1763 int slpm_output = PIN_SLPM_DIR(cfg);
1764 int slpm_val = PIN_SLPM_VAL(cfg);
1765
1766 /* All pins go into GPIO mode at sleep */
1767 gpiomode = true;
1768
1769 /*
1770 * The SLPM_* values are normal values + 1 to allow zero
1771 * to mean "same as normal".
1772 */
1773 if (slpm_pull)
1774 pull = slpm_pull - 1;
1775 if (slpm_output)
1776 output = slpm_output - 1;
1777 if (slpm_val)
1778 val = slpm_val - 1;
1779
1780 dev_dbg(nmk_chip->chip.parent,
1781 "pin %d: sleep pull %s, dir %s, val %s\n",
1782 pin,
1783 slpm_pull ? pullnames[pull] : "same",
1784 slpm_output ? (output ? "output" : "input")
1785 : "same",
1786 slpm_val ? (val ? "high" : "low") : "same");
1787 }
1788
1789 dev_dbg(nmk_chip->chip.parent,
1790 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1791 pin, cfg, pullnames[pull], slpmnames[slpm],
1792 output ? "output " : "input",
1793 output ? (val ? "high" : "low") : "",
1794 lowemi ? "on" : "off");
1795
1796 clk_enable(nmk_chip->clk);
1797 bit = pin % NMK_GPIO_PER_CHIP;
1798 if (gpiomode)
1799 /* No glitch when going to GPIO mode */
1800 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1801 if (output)
1802 __nmk_gpio_make_output(nmk_chip, bit, val);
1803 else {
1804 __nmk_gpio_make_input(nmk_chip, bit);
1805 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1806 }
1807 /* TODO: isn't this only applicable on output pins? */
1808 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1809
1810 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1811 clk_disable(nmk_chip->clk);
1812 } /* for each config */
1813
1814 return 0;
1815 }
1816
1817 static const struct pinconf_ops nmk_pinconf_ops = {
1818 .pin_config_get = nmk_pin_config_get,
1819 .pin_config_set = nmk_pin_config_set,
1820 };
1821
1822 static struct pinctrl_desc nmk_pinctrl_desc = {
1823 .name = "pinctrl-nomadik",
1824 .pctlops = &nmk_pinctrl_ops,
1825 .pmxops = &nmk_pinmux_ops,
1826 .confops = &nmk_pinconf_ops,
1827 .owner = THIS_MODULE,
1828 };
1829
1830 static const struct of_device_id nmk_pinctrl_match[] = {
1831 {
1832 .compatible = "stericsson,stn8815-pinctrl",
1833 .data = (void *)PINCTRL_NMK_STN8815,
1834 },
1835 {
1836 .compatible = "stericsson,db8500-pinctrl",
1837 .data = (void *)PINCTRL_NMK_DB8500,
1838 },
1839 {
1840 .compatible = "stericsson,db8540-pinctrl",
1841 .data = (void *)PINCTRL_NMK_DB8540,
1842 },
1843 {},
1844 };
1845
1846 #ifdef CONFIG_PM_SLEEP
1847 static int nmk_pinctrl_suspend(struct device *dev)
1848 {
1849 struct nmk_pinctrl *npct;
1850
1851 npct = dev_get_drvdata(dev);
1852 if (!npct)
1853 return -EINVAL;
1854
1855 return pinctrl_force_sleep(npct->pctl);
1856 }
1857
1858 static int nmk_pinctrl_resume(struct device *dev)
1859 {
1860 struct nmk_pinctrl *npct;
1861
1862 npct = dev_get_drvdata(dev);
1863 if (!npct)
1864 return -EINVAL;
1865
1866 return pinctrl_force_default(npct->pctl);
1867 }
1868 #endif
1869
1870 static int nmk_pinctrl_probe(struct platform_device *pdev)
1871 {
1872 const struct of_device_id *match;
1873 struct device_node *np = pdev->dev.of_node;
1874 struct device_node *prcm_np;
1875 struct nmk_pinctrl *npct;
1876 unsigned int version = 0;
1877 int i;
1878
1879 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1880 if (!npct)
1881 return -ENOMEM;
1882
1883 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1884 if (!match)
1885 return -ENODEV;
1886 version = (unsigned int) match->data;
1887
1888 /* Poke in other ASIC variants here */
1889 if (version == PINCTRL_NMK_STN8815)
1890 nmk_pinctrl_stn8815_init(&npct->soc);
1891 if (version == PINCTRL_NMK_DB8500)
1892 nmk_pinctrl_db8500_init(&npct->soc);
1893 if (version == PINCTRL_NMK_DB8540)
1894 nmk_pinctrl_db8540_init(&npct->soc);
1895
1896 /*
1897 * Since we depend on the GPIO chips to provide clock and register base
1898 * for the pin control operations, make sure that we have these
1899 * populated before we continue. Follow the phandles to instantiate
1900 * them. The GPIO portion of the actual hardware may be probed before
1901 * or after this point: it shouldn't matter as the APIs are orthogonal.
1902 */
1903 for (i = 0; i < NMK_MAX_BANKS; i++) {
1904 struct device_node *gpio_np;
1905 struct nmk_gpio_chip *nmk_chip;
1906
1907 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1908 if (gpio_np) {
1909 dev_info(&pdev->dev,
1910 "populate NMK GPIO %d \"%s\"\n",
1911 i, gpio_np->name);
1912 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1913 if (IS_ERR(nmk_chip))
1914 dev_err(&pdev->dev,
1915 "could not populate nmk chip struct "
1916 "- continue anyway\n");
1917 of_node_put(gpio_np);
1918 }
1919 }
1920
1921 prcm_np = of_parse_phandle(np, "prcm", 0);
1922 if (prcm_np)
1923 npct->prcm_base = of_iomap(prcm_np, 0);
1924 if (!npct->prcm_base) {
1925 if (version == PINCTRL_NMK_STN8815) {
1926 dev_info(&pdev->dev,
1927 "No PRCM base, "
1928 "assuming no ALT-Cx control is available\n");
1929 } else {
1930 dev_err(&pdev->dev, "missing PRCM base address\n");
1931 return -EINVAL;
1932 }
1933 }
1934
1935 nmk_pinctrl_desc.pins = npct->soc->pins;
1936 nmk_pinctrl_desc.npins = npct->soc->npins;
1937 npct->dev = &pdev->dev;
1938
1939 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1940 if (IS_ERR(npct->pctl)) {
1941 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1942 return PTR_ERR(npct->pctl);
1943 }
1944
1945 platform_set_drvdata(pdev, npct);
1946 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1947
1948 return 0;
1949 }
1950
1951 static const struct of_device_id nmk_gpio_match[] = {
1952 { .compatible = "st,nomadik-gpio", },
1953 {}
1954 };
1955
1956 static struct platform_driver nmk_gpio_driver = {
1957 .driver = {
1958 .name = "gpio",
1959 .of_match_table = nmk_gpio_match,
1960 },
1961 .probe = nmk_gpio_probe,
1962 };
1963
1964 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1965 nmk_pinctrl_suspend,
1966 nmk_pinctrl_resume);
1967
1968 static struct platform_driver nmk_pinctrl_driver = {
1969 .driver = {
1970 .name = "pinctrl-nomadik",
1971 .of_match_table = nmk_pinctrl_match,
1972 .pm = &nmk_pinctrl_pm_ops,
1973 },
1974 .probe = nmk_pinctrl_probe,
1975 };
1976
1977 static int __init nmk_gpio_init(void)
1978 {
1979 return platform_driver_register(&nmk_gpio_driver);
1980 }
1981 subsys_initcall(nmk_gpio_init);
1982
1983 static int __init nmk_pinctrl_init(void)
1984 {
1985 return platform_driver_register(&nmk_pinctrl_driver);
1986 }
1987 core_initcall(nmk_pinctrl_init);
1988
1989 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1990 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1991 MODULE_LICENSE("GPL");
Linux with added FPC-III support