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x86, UV: Fix for nodes with memory and no cpus
[linux/fpc-iii.git] / drivers / infiniband / hw / ehca / ehca_qp.c
blob00c1081597141c7e2fac0b8f1a72f7273e04d50c
1 /*
2 * IBM eServer eHCA Infiniband device driver for Linux on POWER
3 *
4 * QP functions
5 *
6 * Authors: Joachim Fenkes <fenkes@de.ibm.com>
7 * Stefan Roscher <stefan.roscher@de.ibm.com>
8 * Waleri Fomin <fomin@de.ibm.com>
9 * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
10 * Reinhard Ernst <rernst@de.ibm.com>
11 * Heiko J Schick <schickhj@de.ibm.com>
12 *
13 * Copyright (c) 2005 IBM Corporation
14 *
15 * All rights reserved.
16 *
17 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
18 * BSD.
19 *
20 * OpenIB BSD License
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 *
25 * Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following disclaimer.
27 *
28 * Redistributions in binary form must reproduce the above copyright notice,
29 * this list of conditions and the following disclaimer in the documentation
30 * and/or other materials
31 * provided with the distribution.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
41 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 * POSSIBILITY OF SUCH DAMAGE.
44 */
45
46 #include "ehca_classes.h"
47 #include "ehca_tools.h"
48 #include "ehca_qes.h"
49 #include "ehca_iverbs.h"
50 #include "hcp_if.h"
51 #include "hipz_fns.h"
52
53 static struct kmem_cache *qp_cache;
54
55 /*
56 * attributes not supported by query qp
57 */
58 #define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \
59 IB_QP_MAX_QP_RD_ATOMIC | \
60 IB_QP_ACCESS_FLAGS | \
61 IB_QP_EN_SQD_ASYNC_NOTIFY)
62
63 /*
64 * ehca (internal) qp state values
65 */
66 enum ehca_qp_state {
67 EHCA_QPS_RESET = 1,
68 EHCA_QPS_INIT = 2,
69 EHCA_QPS_RTR = 3,
70 EHCA_QPS_RTS = 5,
71 EHCA_QPS_SQD = 6,
72 EHCA_QPS_SQE = 8,
73 EHCA_QPS_ERR = 128
74 };
75
76 /*
77 * qp state transitions as defined by IB Arch Rel 1.1 page 431
78 */
79 enum ib_qp_statetrans {
80 IB_QPST_ANY2RESET,
81 IB_QPST_ANY2ERR,
82 IB_QPST_RESET2INIT,
83 IB_QPST_INIT2RTR,
84 IB_QPST_INIT2INIT,
85 IB_QPST_RTR2RTS,
86 IB_QPST_RTS2SQD,
87 IB_QPST_RTS2RTS,
88 IB_QPST_SQD2RTS,
89 IB_QPST_SQE2RTS,
90 IB_QPST_SQD2SQD,
91 IB_QPST_MAX /* nr of transitions, this must be last!!! */
92 };
93
94 /*
95 * ib2ehca_qp_state maps IB to ehca qp_state
96 * returns ehca qp state corresponding to given ib qp state
97 */
98 static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state)
99 {
100 switch (ib_qp_state) {
101 case IB_QPS_RESET:
102 return EHCA_QPS_RESET;
103 case IB_QPS_INIT:
104 return EHCA_QPS_INIT;
105 case IB_QPS_RTR:
106 return EHCA_QPS_RTR;
107 case IB_QPS_RTS:
108 return EHCA_QPS_RTS;
109 case IB_QPS_SQD:
110 return EHCA_QPS_SQD;
111 case IB_QPS_SQE:
112 return EHCA_QPS_SQE;
113 case IB_QPS_ERR:
114 return EHCA_QPS_ERR;
115 default:
116 ehca_gen_err("invalid ib_qp_state=%x", ib_qp_state);
117 return -EINVAL;
118 }
119 }
120
121 /*
122 * ehca2ib_qp_state maps ehca to IB qp_state
123 * returns ib qp state corresponding to given ehca qp state
124 */
125 static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state
126 ehca_qp_state)
127 {
128 switch (ehca_qp_state) {
129 case EHCA_QPS_RESET:
130 return IB_QPS_RESET;
131 case EHCA_QPS_INIT:
132 return IB_QPS_INIT;
133 case EHCA_QPS_RTR:
134 return IB_QPS_RTR;
135 case EHCA_QPS_RTS:
136 return IB_QPS_RTS;
137 case EHCA_QPS_SQD:
138 return IB_QPS_SQD;
139 case EHCA_QPS_SQE:
140 return IB_QPS_SQE;
141 case EHCA_QPS_ERR:
142 return IB_QPS_ERR;
143 default:
144 ehca_gen_err("invalid ehca_qp_state=%x", ehca_qp_state);
145 return -EINVAL;
146 }
147 }
148
149 /*
150 * ehca_qp_type used as index for req_attr and opt_attr of
151 * struct ehca_modqp_statetrans
152 */
153 enum ehca_qp_type {
154 QPT_RC = 0,
155 QPT_UC = 1,
156 QPT_UD = 2,
157 QPT_SQP = 3,
158 QPT_MAX
159 };
160
161 /*
162 * ib2ehcaqptype maps Ib to ehca qp_type
163 * returns ehca qp type corresponding to ib qp type
164 */
165 static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype)
166 {
167 switch (ibqptype) {
168 case IB_QPT_SMI:
169 case IB_QPT_GSI:
170 return QPT_SQP;
171 case IB_QPT_RC:
172 return QPT_RC;
173 case IB_QPT_UC:
174 return QPT_UC;
175 case IB_QPT_UD:
176 return QPT_UD;
177 default:
178 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
179 return -EINVAL;
180 }
181 }
182
183 static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate,
184 int ib_tostate)
185 {
186 int index = -EINVAL;
187 switch (ib_tostate) {
188 case IB_QPS_RESET:
189 index = IB_QPST_ANY2RESET;
190 break;
191 case IB_QPS_INIT:
192 switch (ib_fromstate) {
193 case IB_QPS_RESET:
194 index = IB_QPST_RESET2INIT;
195 break;
196 case IB_QPS_INIT:
197 index = IB_QPST_INIT2INIT;
198 break;
199 }
200 break;
201 case IB_QPS_RTR:
202 if (ib_fromstate == IB_QPS_INIT)
203 index = IB_QPST_INIT2RTR;
204 break;
205 case IB_QPS_RTS:
206 switch (ib_fromstate) {
207 case IB_QPS_RTR:
208 index = IB_QPST_RTR2RTS;
209 break;
210 case IB_QPS_RTS:
211 index = IB_QPST_RTS2RTS;
212 break;
213 case IB_QPS_SQD:
214 index = IB_QPST_SQD2RTS;
215 break;
216 case IB_QPS_SQE:
217 index = IB_QPST_SQE2RTS;
218 break;
219 }
220 break;
221 case IB_QPS_SQD:
222 if (ib_fromstate == IB_QPS_RTS)
223 index = IB_QPST_RTS2SQD;
224 break;
225 case IB_QPS_SQE:
226 break;
227 case IB_QPS_ERR:
228 index = IB_QPST_ANY2ERR;
229 break;
230 default:
231 break;
232 }
233 return index;
234 }
235
236 /*
237 * ibqptype2servicetype returns hcp service type corresponding to given
238 * ib qp type used by create_qp()
239 */
240 static inline int ibqptype2servicetype(enum ib_qp_type ibqptype)
241 {
242 switch (ibqptype) {
243 case IB_QPT_SMI:
244 case IB_QPT_GSI:
245 return ST_UD;
246 case IB_QPT_RC:
247 return ST_RC;
248 case IB_QPT_UC:
249 return ST_UC;
250 case IB_QPT_UD:
251 return ST_UD;
252 case IB_QPT_RAW_IPV6:
253 return -EINVAL;
254 case IB_QPT_RAW_ETY:
255 return -EINVAL;
256 default:
257 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
258 return -EINVAL;
259 }
260 }
261
262 /*
263 * init userspace queue info from ipz_queue data
264 */
265 static inline void queue2resp(struct ipzu_queue_resp *resp,
266 struct ipz_queue *queue)
267 {
268 resp->qe_size = queue->qe_size;
269 resp->act_nr_of_sg = queue->act_nr_of_sg;
270 resp->queue_length = queue->queue_length;
271 resp->pagesize = queue->pagesize;
272 resp->toggle_state = queue->toggle_state;
273 resp->offset = queue->offset;
274 }
275
276 /*
277 * init_qp_queue initializes/constructs r/squeue and registers queue pages.
278 */
279 static inline int init_qp_queue(struct ehca_shca *shca,
280 struct ehca_pd *pd,
281 struct ehca_qp *my_qp,
282 struct ipz_queue *queue,
283 int q_type,
284 u64 expected_hret,
285 struct ehca_alloc_queue_parms *parms,
286 int wqe_size)
287 {
288 int ret, cnt, ipz_rc, nr_q_pages;
289 void *vpage;
290 u64 rpage, h_ret;
291 struct ib_device *ib_dev = &shca->ib_device;
292 struct ipz_adapter_handle ipz_hca_handle = shca->ipz_hca_handle;
293
294 if (!parms->queue_size)
295 return 0;
296
297 if (parms->is_small) {
298 nr_q_pages = 1;
299 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
300 128 << parms->page_size,
301 wqe_size, parms->act_nr_sges, 1);
302 } else {
303 nr_q_pages = parms->queue_size;
304 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
305 EHCA_PAGESIZE, wqe_size,
306 parms->act_nr_sges, 0);
307 }
308
309 if (!ipz_rc) {
310 ehca_err(ib_dev, "Cannot allocate page for queue. ipz_rc=%i",
311 ipz_rc);
312 return -EBUSY;
313 }
314
315 /* register queue pages */
316 for (cnt = 0; cnt < nr_q_pages; cnt++) {
317 vpage = ipz_qpageit_get_inc(queue);
318 if (!vpage) {
319 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
320 "failed p_vpage= %p", vpage);
321 ret = -EINVAL;
322 goto init_qp_queue1;
323 }
324 rpage = virt_to_abs(vpage);
325
326 h_ret = hipz_h_register_rpage_qp(ipz_hca_handle,
327 my_qp->ipz_qp_handle,
328 NULL, 0, q_type,
329 rpage, parms->is_small ? 0 : 1,
330 my_qp->galpas.kernel);
331 if (cnt == (nr_q_pages - 1)) { /* last page! */
332 if (h_ret != expected_hret) {
333 ehca_err(ib_dev, "hipz_qp_register_rpage() "
334 "h_ret=%lli", h_ret);
335 ret = ehca2ib_return_code(h_ret);
336 goto init_qp_queue1;
337 }
338 vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue);
339 if (vpage) {
340 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
341 "should not succeed vpage=%p", vpage);
342 ret = -EINVAL;
343 goto init_qp_queue1;
344 }
345 } else {
346 if (h_ret != H_PAGE_REGISTERED) {
347 ehca_err(ib_dev, "hipz_qp_register_rpage() "
348 "h_ret=%lli", h_ret);
349 ret = ehca2ib_return_code(h_ret);
350 goto init_qp_queue1;
351 }
352 }
353 }
354
355 ipz_qeit_reset(queue);
356
357 return 0;
358
359 init_qp_queue1:
360 ipz_queue_dtor(pd, queue);
361 return ret;
362 }
363
364 static inline int ehca_calc_wqe_size(int act_nr_sge, int is_llqp)
365 {
366 if (is_llqp)
367 return 128 << act_nr_sge;
368 else
369 return offsetof(struct ehca_wqe,
370 u.nud.sg_list[act_nr_sge]);
371 }
372
373 static void ehca_determine_small_queue(struct ehca_alloc_queue_parms *queue,
374 int req_nr_sge, int is_llqp)
375 {
376 u32 wqe_size, q_size;
377 int act_nr_sge = req_nr_sge;
378
379 if (!is_llqp)
380 /* round up #SGEs so WQE size is a power of 2 */
381 for (act_nr_sge = 4; act_nr_sge <= 252;
382 act_nr_sge = 4 + 2 * act_nr_sge)
383 if (act_nr_sge >= req_nr_sge)
384 break;
385
386 wqe_size = ehca_calc_wqe_size(act_nr_sge, is_llqp);
387 q_size = wqe_size * (queue->max_wr + 1);
388
389 if (q_size <= 512)
390 queue->page_size = 2;
391 else if (q_size <= 1024)
392 queue->page_size = 3;
393 else
394 queue->page_size = 0;
395
396 queue->is_small = (queue->page_size != 0);
397 }
398
399 /* needs to be called with cq->spinlock held */
400 void ehca_add_to_err_list(struct ehca_qp *qp, int on_sq)
401 {
402 struct list_head *list, *node;
403
404 /* TODO: support low latency QPs */
405 if (qp->ext_type == EQPT_LLQP)
406 return;
407
408 if (on_sq) {
409 list = &qp->send_cq->sqp_err_list;
410 node = &qp->sq_err_node;
411 } else {
412 list = &qp->recv_cq->rqp_err_list;
413 node = &qp->rq_err_node;
414 }
415
416 if (list_empty(node))
417 list_add_tail(node, list);
418
419 return;
420 }
421
422 static void del_from_err_list(struct ehca_cq *cq, struct list_head *node)
423 {
424 unsigned long flags;
425
426 spin_lock_irqsave(&cq->spinlock, flags);
427
428 if (!list_empty(node))
429 list_del_init(node);
430
431 spin_unlock_irqrestore(&cq->spinlock, flags);
432 }
433
434 static void reset_queue_map(struct ehca_queue_map *qmap)
435 {
436 int i;
437
438 qmap->tail = qmap->entries - 1;
439 qmap->left_to_poll = 0;
440 qmap->next_wqe_idx = 0;
441 for (i = 0; i < qmap->entries; i++) {
442 qmap->map[i].reported = 1;
443 qmap->map[i].cqe_req = 0;
444 }
445 }
446
447 /*
448 * Create an ib_qp struct that is either a QP or an SRQ, depending on
449 * the value of the is_srq parameter. If init_attr and srq_init_attr share
450 * fields, the field out of init_attr is used.
451 */
452 static struct ehca_qp *internal_create_qp(
453 struct ib_pd *pd,
454 struct ib_qp_init_attr *init_attr,
455 struct ib_srq_init_attr *srq_init_attr,
456 struct ib_udata *udata, int is_srq)
457 {
458 struct ehca_qp *my_qp, *my_srq = NULL;
459 struct ehca_pd *my_pd = container_of(pd, struct ehca_pd, ib_pd);
460 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
461 ib_device);
462 struct ib_ucontext *context = NULL;
463 u64 h_ret;
464 int is_llqp = 0, has_srq = 0;
465 int qp_type, max_send_sge, max_recv_sge, ret;
466
467 /* h_call's out parameters */
468 struct ehca_alloc_qp_parms parms;
469 u32 swqe_size = 0, rwqe_size = 0, ib_qp_num;
470 unsigned long flags;
471
472 if (!atomic_add_unless(&shca->num_qps, 1, shca->max_num_qps)) {
473 ehca_err(pd->device, "Unable to create QP, max number of %i "
474 "QPs reached.", shca->max_num_qps);
475 ehca_err(pd->device, "To increase the maximum number of QPs "
476 "use the number_of_qps module parameter.\n");
477 return ERR_PTR(-ENOSPC);
478 }
479
480 if (init_attr->create_flags) {
481 atomic_dec(&shca->num_qps);
482 return ERR_PTR(-EINVAL);
483 }
484
485 memset(&parms, 0, sizeof(parms));
486 qp_type = init_attr->qp_type;
487
488 if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR &&
489 init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) {
490 ehca_err(pd->device, "init_attr->sg_sig_type=%x not allowed",
491 init_attr->sq_sig_type);
492 atomic_dec(&shca->num_qps);
493 return ERR_PTR(-EINVAL);
494 }
495
496 /* save LLQP info */
497 if (qp_type & 0x80) {
498 is_llqp = 1;
499 parms.ext_type = EQPT_LLQP;
500 parms.ll_comp_flags = qp_type & LLQP_COMP_MASK;
501 }
502 qp_type &= 0x1F;
503 init_attr->qp_type &= 0x1F;
504
505 /* handle SRQ base QPs */
506 if (init_attr->srq) {
507 my_srq = container_of(init_attr->srq, struct ehca_qp, ib_srq);
508
509 if (qp_type == IB_QPT_UC) {
510 ehca_err(pd->device, "UC with SRQ not supported");
511 atomic_dec(&shca->num_qps);
512 return ERR_PTR(-EINVAL);
513 }
514
515 has_srq = 1;
516 parms.ext_type = EQPT_SRQBASE;
517 parms.srq_qpn = my_srq->real_qp_num;
518 }
519
520 if (is_llqp && has_srq) {
521 ehca_err(pd->device, "LLQPs can't have an SRQ");
522 atomic_dec(&shca->num_qps);
523 return ERR_PTR(-EINVAL);
524 }
525
526 /* handle SRQs */
527 if (is_srq) {
528 parms.ext_type = EQPT_SRQ;
529 parms.srq_limit = srq_init_attr->attr.srq_limit;
530 if (init_attr->cap.max_recv_sge > 3) {
531 ehca_err(pd->device, "no more than three SGEs "
532 "supported for SRQ pd=%p max_sge=%x",
533 pd, init_attr->cap.max_recv_sge);
534 atomic_dec(&shca->num_qps);
535 return ERR_PTR(-EINVAL);
536 }
537 }
538
539 /* check QP type */
540 if (qp_type != IB_QPT_UD &&
541 qp_type != IB_QPT_UC &&
542 qp_type != IB_QPT_RC &&
543 qp_type != IB_QPT_SMI &&
544 qp_type != IB_QPT_GSI) {
545 ehca_err(pd->device, "wrong QP Type=%x", qp_type);
546 atomic_dec(&shca->num_qps);
547 return ERR_PTR(-EINVAL);
548 }
549
550 if (is_llqp) {
551 switch (qp_type) {
552 case IB_QPT_RC:
553 if ((init_attr->cap.max_send_wr > 255) ||
554 (init_attr->cap.max_recv_wr > 255)) {
555 ehca_err(pd->device,
556 "Invalid Number of max_sq_wr=%x "
557 "or max_rq_wr=%x for RC LLQP",
558 init_attr->cap.max_send_wr,
559 init_attr->cap.max_recv_wr);
560 atomic_dec(&shca->num_qps);
561 return ERR_PTR(-EINVAL);
562 }
563 break;
564 case IB_QPT_UD:
565 if (!EHCA_BMASK_GET(HCA_CAP_UD_LL_QP, shca->hca_cap)) {
566 ehca_err(pd->device, "UD LLQP not supported "
567 "by this adapter");
568 atomic_dec(&shca->num_qps);
569 return ERR_PTR(-ENOSYS);
570 }
571 if (!(init_attr->cap.max_send_sge <= 5
572 && init_attr->cap.max_send_sge >= 1
573 && init_attr->cap.max_recv_sge <= 5
574 && init_attr->cap.max_recv_sge >= 1)) {
575 ehca_err(pd->device,
576 "Invalid Number of max_send_sge=%x "
577 "or max_recv_sge=%x for UD LLQP",
578 init_attr->cap.max_send_sge,
579 init_attr->cap.max_recv_sge);
580 atomic_dec(&shca->num_qps);
581 return ERR_PTR(-EINVAL);
582 } else if (init_attr->cap.max_send_wr > 255) {
583 ehca_err(pd->device,
584 "Invalid Number of "
585 "max_send_wr=%x for UD QP_TYPE=%x",
586 init_attr->cap.max_send_wr, qp_type);
587 atomic_dec(&shca->num_qps);
588 return ERR_PTR(-EINVAL);
589 }
590 break;
591 default:
592 ehca_err(pd->device, "unsupported LL QP Type=%x",
593 qp_type);
594 atomic_dec(&shca->num_qps);
595 return ERR_PTR(-EINVAL);
596 }
597 } else {
598 int max_sge = (qp_type == IB_QPT_UD || qp_type == IB_QPT_SMI
599 || qp_type == IB_QPT_GSI) ? 250 : 252;
600
601 if (init_attr->cap.max_send_sge > max_sge
602 || init_attr->cap.max_recv_sge > max_sge) {
603 ehca_err(pd->device, "Invalid number of SGEs requested "
604 "send_sge=%x recv_sge=%x max_sge=%x",
605 init_attr->cap.max_send_sge,
606 init_attr->cap.max_recv_sge, max_sge);
607 atomic_dec(&shca->num_qps);
608 return ERR_PTR(-EINVAL);
609 }
610 }
611
612 if (pd->uobject && udata)
613 context = pd->uobject->context;
614
615 my_qp = kmem_cache_zalloc(qp_cache, GFP_KERNEL);
616 if (!my_qp) {
617 ehca_err(pd->device, "pd=%p not enough memory to alloc qp", pd);
618 atomic_dec(&shca->num_qps);
619 return ERR_PTR(-ENOMEM);
620 }
621
622 atomic_set(&my_qp->nr_events, 0);
623 init_waitqueue_head(&my_qp->wait_completion);
624 spin_lock_init(&my_qp->spinlock_s);
625 spin_lock_init(&my_qp->spinlock_r);
626 my_qp->qp_type = qp_type;
627 my_qp->ext_type = parms.ext_type;
628 my_qp->state = IB_QPS_RESET;
629
630 if (init_attr->recv_cq)
631 my_qp->recv_cq =
632 container_of(init_attr->recv_cq, struct ehca_cq, ib_cq);
633 if (init_attr->send_cq)
634 my_qp->send_cq =
635 container_of(init_attr->send_cq, struct ehca_cq, ib_cq);
636
637 do {
638 if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) {
639 ret = -ENOMEM;
640 ehca_err(pd->device, "Can't reserve idr resources.");
641 goto create_qp_exit0;
642 }
643
644 write_lock_irqsave(&ehca_qp_idr_lock, flags);
645 ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token);
646 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
647 } while (ret == -EAGAIN);
648
649 if (ret) {
650 ret = -ENOMEM;
651 ehca_err(pd->device, "Can't allocate new idr entry.");
652 goto create_qp_exit0;
653 }
654
655 if (my_qp->token > 0x1FFFFFF) {
656 ret = -EINVAL;
657 ehca_err(pd->device, "Invalid number of qp");
658 goto create_qp_exit1;
659 }
660
661 if (has_srq)
662 parms.srq_token = my_qp->token;
663
664 parms.servicetype = ibqptype2servicetype(qp_type);
665 if (parms.servicetype < 0) {
666 ret = -EINVAL;
667 ehca_err(pd->device, "Invalid qp_type=%x", qp_type);
668 goto create_qp_exit1;
669 }
670
671 /* Always signal by WQE so we can hide circ. WQEs */
672 parms.sigtype = HCALL_SIGT_BY_WQE;
673
674 /* UD_AV CIRCUMVENTION */
675 max_send_sge = init_attr->cap.max_send_sge;
676 max_recv_sge = init_attr->cap.max_recv_sge;
677 if (parms.servicetype == ST_UD && !is_llqp) {
678 max_send_sge += 2;
679 max_recv_sge += 2;
680 }
681
682 parms.token = my_qp->token;
683 parms.eq_handle = shca->eq.ipz_eq_handle;
684 parms.pd = my_pd->fw_pd;
685 if (my_qp->send_cq)
686 parms.send_cq_handle = my_qp->send_cq->ipz_cq_handle;
687 if (my_qp->recv_cq)
688 parms.recv_cq_handle = my_qp->recv_cq->ipz_cq_handle;
689
690 parms.squeue.max_wr = init_attr->cap.max_send_wr;
691 parms.rqueue.max_wr = init_attr->cap.max_recv_wr;
692 parms.squeue.max_sge = max_send_sge;
693 parms.rqueue.max_sge = max_recv_sge;
694
695 /* RC QPs need one more SWQE for unsolicited ack circumvention */
696 if (qp_type == IB_QPT_RC)
697 parms.squeue.max_wr++;
698
699 if (EHCA_BMASK_GET(HCA_CAP_MINI_QP, shca->hca_cap)) {
700 if (HAS_SQ(my_qp))
701 ehca_determine_small_queue(
702 &parms.squeue, max_send_sge, is_llqp);
703 if (HAS_RQ(my_qp))
704 ehca_determine_small_queue(
705 &parms.rqueue, max_recv_sge, is_llqp);
706 parms.qp_storage =
707 (parms.squeue.is_small || parms.rqueue.is_small);
708 }
709
710 h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, &parms);
711 if (h_ret != H_SUCCESS) {
712 ehca_err(pd->device, "h_alloc_resource_qp() failed h_ret=%lli",
713 h_ret);
714 ret = ehca2ib_return_code(h_ret);
715 goto create_qp_exit1;
716 }
717
718 ib_qp_num = my_qp->real_qp_num = parms.real_qp_num;
719 my_qp->ipz_qp_handle = parms.qp_handle;
720 my_qp->galpas = parms.galpas;
721
722 swqe_size = ehca_calc_wqe_size(parms.squeue.act_nr_sges, is_llqp);
723 rwqe_size = ehca_calc_wqe_size(parms.rqueue.act_nr_sges, is_llqp);
724
725 switch (qp_type) {
726 case IB_QPT_RC:
727 if (is_llqp) {
728 parms.squeue.act_nr_sges = 1;
729 parms.rqueue.act_nr_sges = 1;
730 }
731 /* hide the extra WQE */
732 parms.squeue.act_nr_wqes--;
733 break;
734 case IB_QPT_UD:
735 case IB_QPT_GSI:
736 case IB_QPT_SMI:
737 /* UD circumvention */
738 if (is_llqp) {
739 parms.squeue.act_nr_sges = 1;
740 parms.rqueue.act_nr_sges = 1;
741 } else {
742 parms.squeue.act_nr_sges -= 2;
743 parms.rqueue.act_nr_sges -= 2;
744 }
745
746 if (IB_QPT_GSI == qp_type || IB_QPT_SMI == qp_type) {
747 parms.squeue.act_nr_wqes = init_attr->cap.max_send_wr;
748 parms.rqueue.act_nr_wqes = init_attr->cap.max_recv_wr;
749 parms.squeue.act_nr_sges = init_attr->cap.max_send_sge;
750 parms.rqueue.act_nr_sges = init_attr->cap.max_recv_sge;
751 ib_qp_num = (qp_type == IB_QPT_SMI) ? 0 : 1;
752 }
753
754 break;
755
756 default:
757 break;
758 }
759
760 /* initialize r/squeue and register queue pages */
761 if (HAS_SQ(my_qp)) {
762 ret = init_qp_queue(
763 shca, my_pd, my_qp, &my_qp->ipz_squeue, 0,
764 HAS_RQ(my_qp) ? H_PAGE_REGISTERED : H_SUCCESS,
765 &parms.squeue, swqe_size);
766 if (ret) {
767 ehca_err(pd->device, "Couldn't initialize squeue "
768 "and pages ret=%i", ret);
769 goto create_qp_exit2;
770 }
771
772 my_qp->sq_map.entries = my_qp->ipz_squeue.queue_length /
773 my_qp->ipz_squeue.qe_size;
774 my_qp->sq_map.map = vmalloc(my_qp->sq_map.entries *
775 sizeof(struct ehca_qmap_entry));
776 if (!my_qp->sq_map.map) {
777 ehca_err(pd->device, "Couldn't allocate squeue "
778 "map ret=%i", ret);
779 goto create_qp_exit3;
780 }
781 INIT_LIST_HEAD(&my_qp->sq_err_node);
782 /* to avoid the generation of bogus flush CQEs */
783 reset_queue_map(&my_qp->sq_map);
784 }
785
786 if (HAS_RQ(my_qp)) {
787 ret = init_qp_queue(
788 shca, my_pd, my_qp, &my_qp->ipz_rqueue, 1,
789 H_SUCCESS, &parms.rqueue, rwqe_size);
790 if (ret) {
791 ehca_err(pd->device, "Couldn't initialize rqueue "
792 "and pages ret=%i", ret);
793 goto create_qp_exit4;
794 }
795
796 my_qp->rq_map.entries = my_qp->ipz_rqueue.queue_length /
797 my_qp->ipz_rqueue.qe_size;
798 my_qp->rq_map.map = vmalloc(my_qp->rq_map.entries *
799 sizeof(struct ehca_qmap_entry));
800 if (!my_qp->rq_map.map) {
801 ehca_err(pd->device, "Couldn't allocate squeue "
802 "map ret=%i", ret);
803 goto create_qp_exit5;
804 }
805 INIT_LIST_HEAD(&my_qp->rq_err_node);
806 /* to avoid the generation of bogus flush CQEs */
807 reset_queue_map(&my_qp->rq_map);
808 } else if (init_attr->srq) {
809 /* this is a base QP, use the queue map of the SRQ */
810 my_qp->rq_map = my_srq->rq_map;
811 INIT_LIST_HEAD(&my_qp->rq_err_node);
812
813 my_qp->ipz_rqueue = my_srq->ipz_rqueue;
814 }
815
816 if (is_srq) {
817 my_qp->ib_srq.pd = &my_pd->ib_pd;
818 my_qp->ib_srq.device = my_pd->ib_pd.device;
819
820 my_qp->ib_srq.srq_context = init_attr->qp_context;
821 my_qp->ib_srq.event_handler = init_attr->event_handler;
822 } else {
823 my_qp->ib_qp.qp_num = ib_qp_num;
824 my_qp->ib_qp.pd = &my_pd->ib_pd;
825 my_qp->ib_qp.device = my_pd->ib_pd.device;
826
827 my_qp->ib_qp.recv_cq = init_attr->recv_cq;
828 my_qp->ib_qp.send_cq = init_attr->send_cq;
829
830 my_qp->ib_qp.qp_type = qp_type;
831 my_qp->ib_qp.srq = init_attr->srq;
832
833 my_qp->ib_qp.qp_context = init_attr->qp_context;
834 my_qp->ib_qp.event_handler = init_attr->event_handler;
835 }
836
837 init_attr->cap.max_inline_data = 0; /* not supported yet */
838 init_attr->cap.max_recv_sge = parms.rqueue.act_nr_sges;
839 init_attr->cap.max_recv_wr = parms.rqueue.act_nr_wqes;
840 init_attr->cap.max_send_sge = parms.squeue.act_nr_sges;
841 init_attr->cap.max_send_wr = parms.squeue.act_nr_wqes;
842 my_qp->init_attr = *init_attr;
843
844 if (qp_type == IB_QPT_SMI || qp_type == IB_QPT_GSI) {
845 shca->sport[init_attr->port_num - 1].ibqp_sqp[qp_type] =
846 &my_qp->ib_qp;
847 if (ehca_nr_ports < 0) {
848 /* alloc array to cache subsequent modify qp parms
849 * for autodetect mode
850 */
851 my_qp->mod_qp_parm =
852 kzalloc(EHCA_MOD_QP_PARM_MAX *
853 sizeof(*my_qp->mod_qp_parm),
854 GFP_KERNEL);
855 if (!my_qp->mod_qp_parm) {
856 ehca_err(pd->device,
857 "Could not alloc mod_qp_parm");
858 goto create_qp_exit5;
859 }
860 }
861 }
862
863 /* NOTE: define_apq0() not supported yet */
864 if (qp_type == IB_QPT_GSI) {
865 h_ret = ehca_define_sqp(shca, my_qp, init_attr);
866 if (h_ret != H_SUCCESS) {
867 kfree(my_qp->mod_qp_parm);
868 my_qp->mod_qp_parm = NULL;
869 /* the QP pointer is no longer valid */
870 shca->sport[init_attr->port_num - 1].ibqp_sqp[qp_type] =
871 NULL;
872 ret = ehca2ib_return_code(h_ret);
873 goto create_qp_exit6;
874 }
875 }
876
877 if (my_qp->send_cq) {
878 ret = ehca_cq_assign_qp(my_qp->send_cq, my_qp);
879 if (ret) {
880 ehca_err(pd->device,
881 "Couldn't assign qp to send_cq ret=%i", ret);
882 goto create_qp_exit7;
883 }
884 }
885
886 /* copy queues, galpa data to user space */
887 if (context && udata) {
888 struct ehca_create_qp_resp resp;
889 memset(&resp, 0, sizeof(resp));
890
891 resp.qp_num = my_qp->real_qp_num;
892 resp.token = my_qp->token;
893 resp.qp_type = my_qp->qp_type;
894 resp.ext_type = my_qp->ext_type;
895 resp.qkey = my_qp->qkey;
896 resp.real_qp_num = my_qp->real_qp_num;
897
898 if (HAS_SQ(my_qp))
899 queue2resp(&resp.ipz_squeue, &my_qp->ipz_squeue);
900 if (HAS_RQ(my_qp))
901 queue2resp(&resp.ipz_rqueue, &my_qp->ipz_rqueue);
902 resp.fw_handle_ofs = (u32)
903 (my_qp->galpas.user.fw_handle & (PAGE_SIZE - 1));
904
905 if (ib_copy_to_udata(udata, &resp, sizeof resp)) {
906 ehca_err(pd->device, "Copy to udata failed");
907 ret = -EINVAL;
908 goto create_qp_exit8;
909 }
910 }
911
912 return my_qp;
913
914 create_qp_exit8:
915 ehca_cq_unassign_qp(my_qp->send_cq, my_qp->real_qp_num);
916
917 create_qp_exit7:
918 kfree(my_qp->mod_qp_parm);
919
920 create_qp_exit6:
921 if (HAS_RQ(my_qp))
922 vfree(my_qp->rq_map.map);
923
924 create_qp_exit5:
925 if (HAS_RQ(my_qp))
926 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
927
928 create_qp_exit4:
929 if (HAS_SQ(my_qp))
930 vfree(my_qp->sq_map.map);
931
932 create_qp_exit3:
933 if (HAS_SQ(my_qp))
934 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
935
936 create_qp_exit2:
937 hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
938
939 create_qp_exit1:
940 write_lock_irqsave(&ehca_qp_idr_lock, flags);
941 idr_remove(&ehca_qp_idr, my_qp->token);
942 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
943
944 create_qp_exit0:
945 kmem_cache_free(qp_cache, my_qp);
946 atomic_dec(&shca->num_qps);
947 return ERR_PTR(ret);
948 }
949
950 struct ib_qp *ehca_create_qp(struct ib_pd *pd,
951 struct ib_qp_init_attr *qp_init_attr,
952 struct ib_udata *udata)
953 {
954 struct ehca_qp *ret;
955
956 ret = internal_create_qp(pd, qp_init_attr, NULL, udata, 0);
957 return IS_ERR(ret) ? (struct ib_qp *)ret : &ret->ib_qp;
958 }
959
960 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
961 struct ib_uobject *uobject);
962
963 struct ib_srq *ehca_create_srq(struct ib_pd *pd,
964 struct ib_srq_init_attr *srq_init_attr,
965 struct ib_udata *udata)
966 {
967 struct ib_qp_init_attr qp_init_attr;
968 struct ehca_qp *my_qp;
969 struct ib_srq *ret;
970 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
971 ib_device);
972 struct hcp_modify_qp_control_block *mqpcb;
973 u64 hret, update_mask;
974
975 /* For common attributes, internal_create_qp() takes its info
976 * out of qp_init_attr, so copy all common attrs there.
977 */
978 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
979 qp_init_attr.event_handler = srq_init_attr->event_handler;
980 qp_init_attr.qp_context = srq_init_attr->srq_context;
981 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
982 qp_init_attr.qp_type = IB_QPT_RC;
983 qp_init_attr.cap.max_recv_wr = srq_init_attr->attr.max_wr;
984 qp_init_attr.cap.max_recv_sge = srq_init_attr->attr.max_sge;
985
986 my_qp = internal_create_qp(pd, &qp_init_attr, srq_init_attr, udata, 1);
987 if (IS_ERR(my_qp))
988 return (struct ib_srq *)my_qp;
989
990 /* copy back return values */
991 srq_init_attr->attr.max_wr = qp_init_attr.cap.max_recv_wr;
992 srq_init_attr->attr.max_sge = 3;
993
994 /* drive SRQ into RTR state */
995 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
996 if (!mqpcb) {
997 ehca_err(pd->device, "Could not get zeroed page for mqpcb "
998 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
999 ret = ERR_PTR(-ENOMEM);
1000 goto create_srq1;
1001 }
1002
1003 mqpcb->qp_state = EHCA_QPS_INIT;
1004 mqpcb->prim_phys_port = 1;
1005 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
1006 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
1007 my_qp->ipz_qp_handle,
1008 &my_qp->pf,
1009 update_mask,
1010 mqpcb, my_qp->galpas.kernel);
1011 if (hret != H_SUCCESS) {
1012 ehca_err(pd->device, "Could not modify SRQ to INIT "
1013 "ehca_qp=%p qp_num=%x h_ret=%lli",
1014 my_qp, my_qp->real_qp_num, hret);
1015 goto create_srq2;
1016 }
1017
1018 mqpcb->qp_enable = 1;
1019 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
1020 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
1021 my_qp->ipz_qp_handle,
1022 &my_qp->pf,
1023 update_mask,
1024 mqpcb, my_qp->galpas.kernel);
1025 if (hret != H_SUCCESS) {
1026 ehca_err(pd->device, "Could not enable SRQ "
1027 "ehca_qp=%p qp_num=%x h_ret=%lli",
1028 my_qp, my_qp->real_qp_num, hret);
1029 goto create_srq2;
1030 }
1031
1032 mqpcb->qp_state = EHCA_QPS_RTR;
1033 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
1034 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
1035 my_qp->ipz_qp_handle,
1036 &my_qp->pf,
1037 update_mask,
1038 mqpcb, my_qp->galpas.kernel);
1039 if (hret != H_SUCCESS) {
1040 ehca_err(pd->device, "Could not modify SRQ to RTR "
1041 "ehca_qp=%p qp_num=%x h_ret=%lli",
1042 my_qp, my_qp->real_qp_num, hret);
1043 goto create_srq2;
1044 }
1045
1046 ehca_free_fw_ctrlblock(mqpcb);
1047
1048 return &my_qp->ib_srq;
1049
1050 create_srq2:
1051 ret = ERR_PTR(ehca2ib_return_code(hret));
1052 ehca_free_fw_ctrlblock(mqpcb);
1053
1054 create_srq1:
1055 internal_destroy_qp(pd->device, my_qp, my_qp->ib_srq.uobject);
1056
1057 return ret;
1058 }
1059
1060 /*
1061 * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts
1062 * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe
1063 * returns total number of bad wqes in bad_wqe_cnt
1064 */
1065 static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
1066 int *bad_wqe_cnt)
1067 {
1068 u64 h_ret;
1069 struct ipz_queue *squeue;
1070 void *bad_send_wqe_p, *bad_send_wqe_v;
1071 u64 q_ofs;
1072 struct ehca_wqe *wqe;
1073 int qp_num = my_qp->ib_qp.qp_num;
1074
1075 /* get send wqe pointer */
1076 h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle,
1077 my_qp->ipz_qp_handle, &my_qp->pf,
1078 &bad_send_wqe_p, NULL, 2);
1079 if (h_ret != H_SUCCESS) {
1080 ehca_err(&shca->ib_device, "hipz_h_disable_and_get_wqe() failed"
1081 " ehca_qp=%p qp_num=%x h_ret=%lli",
1082 my_qp, qp_num, h_ret);
1083 return ehca2ib_return_code(h_ret);
1084 }
1085 bad_send_wqe_p = (void *)((u64)bad_send_wqe_p & (~(1L << 63)));
1086 ehca_dbg(&shca->ib_device, "qp_num=%x bad_send_wqe_p=%p",
1087 qp_num, bad_send_wqe_p);
1088 /* convert wqe pointer to vadr */
1089 bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p);
1090 if (ehca_debug_level >= 2)
1091 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num);
1092 squeue = &my_qp->ipz_squeue;
1093 if (ipz_queue_abs_to_offset(squeue, (u64)bad_send_wqe_p, &q_ofs)) {
1094 ehca_err(&shca->ib_device, "failed to get wqe offset qp_num=%x"
1095 " bad_send_wqe_p=%p", qp_num, bad_send_wqe_p);
1096 return -EFAULT;
1097 }
1098
1099 /* loop sets wqe's purge bit */
1100 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
1101 *bad_wqe_cnt = 0;
1102 while (wqe->optype != 0xff && wqe->wqef != 0xff) {
1103 if (ehca_debug_level >= 2)
1104 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num);
1105 wqe->nr_of_data_seg = 0; /* suppress data access */
1106 wqe->wqef = WQEF_PURGE; /* WQE to be purged */
1107 q_ofs = ipz_queue_advance_offset(squeue, q_ofs);
1108 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
1109 *bad_wqe_cnt = (*bad_wqe_cnt)+1;
1110 }
1111 /*
1112 * bad wqe will be reprocessed and ignored when pol_cq() is called,
1113 * i.e. nr of wqes with flush error status is one less
1114 */
1115 ehca_dbg(&shca->ib_device, "qp_num=%x flusherr_wqe_cnt=%x",
1116 qp_num, (*bad_wqe_cnt)-1);
1117 wqe->wqef = 0;
1118
1119 return 0;
1120 }
1121
1122 static int calc_left_cqes(u64 wqe_p, struct ipz_queue *ipz_queue,
1123 struct ehca_queue_map *qmap)
1124 {
1125 void *wqe_v;
1126 u64 q_ofs;
1127 u32 wqe_idx;
1128 unsigned int tail_idx;
1129
1130 /* convert real to abs address */
1131 wqe_p = wqe_p & (~(1UL << 63));
1132
1133 wqe_v = abs_to_virt(wqe_p);
1134
1135 if (ipz_queue_abs_to_offset(ipz_queue, wqe_p, &q_ofs)) {
1136 ehca_gen_err("Invalid offset for calculating left cqes "
1137 "wqe_p=%#llx wqe_v=%p\n", wqe_p, wqe_v);
1138 return -EFAULT;
1139 }
1140
1141 tail_idx = next_index(qmap->tail, qmap->entries);
1142 wqe_idx = q_ofs / ipz_queue->qe_size;
1143
1144 /* check all processed wqes, whether a cqe is requested or not */
1145 while (tail_idx != wqe_idx) {
1146 if (qmap->map[tail_idx].cqe_req)
1147 qmap->left_to_poll++;
1148 tail_idx = next_index(tail_idx, qmap->entries);
1149 }
1150 /* save index in queue, where we have to start flushing */
1151 qmap->next_wqe_idx = wqe_idx;
1152 return 0;
1153 }
1154
1155 static int check_for_left_cqes(struct ehca_qp *my_qp, struct ehca_shca *shca)
1156 {
1157 u64 h_ret;
1158 void *send_wqe_p, *recv_wqe_p;
1159 int ret;
1160 unsigned long flags;
1161 int qp_num = my_qp->ib_qp.qp_num;
1162
1163 /* this hcall is not supported on base QPs */
1164 if (my_qp->ext_type != EQPT_SRQBASE) {
1165 /* get send and receive wqe pointer */
1166 h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle,
1167 my_qp->ipz_qp_handle, &my_qp->pf,
1168 &send_wqe_p, &recv_wqe_p, 4);
1169 if (h_ret != H_SUCCESS) {
1170 ehca_err(&shca->ib_device, "disable_and_get_wqe() "
1171 "failed ehca_qp=%p qp_num=%x h_ret=%lli",
1172 my_qp, qp_num, h_ret);
1173 return ehca2ib_return_code(h_ret);
1174 }
1175
1176 /*
1177 * acquire lock to ensure that nobody is polling the cq which
1178 * could mean that the qmap->tail pointer is in an
1179 * inconsistent state.
1180 */
1181 spin_lock_irqsave(&my_qp->send_cq->spinlock, flags);
1182 ret = calc_left_cqes((u64)send_wqe_p, &my_qp->ipz_squeue,
1183 &my_qp->sq_map);
1184 spin_unlock_irqrestore(&my_qp->send_cq->spinlock, flags);
1185 if (ret)
1186 return ret;
1187
1188
1189 spin_lock_irqsave(&my_qp->recv_cq->spinlock, flags);
1190 ret = calc_left_cqes((u64)recv_wqe_p, &my_qp->ipz_rqueue,
1191 &my_qp->rq_map);
1192 spin_unlock_irqrestore(&my_qp->recv_cq->spinlock, flags);
1193 if (ret)
1194 return ret;
1195 } else {
1196 spin_lock_irqsave(&my_qp->send_cq->spinlock, flags);
1197 my_qp->sq_map.left_to_poll = 0;
1198 my_qp->sq_map.next_wqe_idx = next_index(my_qp->sq_map.tail,
1199 my_qp->sq_map.entries);
1200 spin_unlock_irqrestore(&my_qp->send_cq->spinlock, flags);
1201
1202 spin_lock_irqsave(&my_qp->recv_cq->spinlock, flags);
1203 my_qp->rq_map.left_to_poll = 0;
1204 my_qp->rq_map.next_wqe_idx = next_index(my_qp->rq_map.tail,
1205 my_qp->rq_map.entries);
1206 spin_unlock_irqrestore(&my_qp->recv_cq->spinlock, flags);
1207 }
1208
1209 /* this assures flush cqes being generated only for pending wqes */
1210 if ((my_qp->sq_map.left_to_poll == 0) &&
1211 (my_qp->rq_map.left_to_poll == 0)) {
1212 spin_lock_irqsave(&my_qp->send_cq->spinlock, flags);
1213 ehca_add_to_err_list(my_qp, 1);
1214 spin_unlock_irqrestore(&my_qp->send_cq->spinlock, flags);
1215
1216 if (HAS_RQ(my_qp)) {
1217 spin_lock_irqsave(&my_qp->recv_cq->spinlock, flags);
1218 ehca_add_to_err_list(my_qp, 0);
1219 spin_unlock_irqrestore(&my_qp->recv_cq->spinlock,
1220 flags);
1221 }
1222 }
1223
1224 return 0;
1225 }
1226
1227 /*
1228 * internal_modify_qp with circumvention to handle aqp0 properly
1229 * smi_reset2init indicates if this is an internal reset-to-init-call for
1230 * smi. This flag must always be zero if called from ehca_modify_qp()!
1231 * This internal func was intorduced to avoid recursion of ehca_modify_qp()!
1232 */
1233 static int internal_modify_qp(struct ib_qp *ibqp,
1234 struct ib_qp_attr *attr,
1235 int attr_mask, int smi_reset2init)
1236 {
1237 enum ib_qp_state qp_cur_state, qp_new_state;
1238 int cnt, qp_attr_idx, ret = 0;
1239 enum ib_qp_statetrans statetrans;
1240 struct hcp_modify_qp_control_block *mqpcb;
1241 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1242 struct ehca_shca *shca =
1243 container_of(ibqp->pd->device, struct ehca_shca, ib_device);
1244 u64 update_mask;
1245 u64 h_ret;
1246 int bad_wqe_cnt = 0;
1247 int squeue_locked = 0;
1248 unsigned long flags = 0;
1249
1250 /* do query_qp to obtain current attr values */
1251 mqpcb = ehca_alloc_fw_ctrlblock(GFP_ATOMIC);
1252 if (!mqpcb) {
1253 ehca_err(ibqp->device, "Could not get zeroed page for mqpcb "
1254 "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num);
1255 return -ENOMEM;
1256 }
1257
1258 h_ret = hipz_h_query_qp(shca->ipz_hca_handle,
1259 my_qp->ipz_qp_handle,
1260 &my_qp->pf,
1261 mqpcb, my_qp->galpas.kernel);
1262 if (h_ret != H_SUCCESS) {
1263 ehca_err(ibqp->device, "hipz_h_query_qp() failed "
1264 "ehca_qp=%p qp_num=%x h_ret=%lli",
1265 my_qp, ibqp->qp_num, h_ret);
1266 ret = ehca2ib_return_code(h_ret);
1267 goto modify_qp_exit1;
1268 }
1269
1270 qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state);
1271
1272 if (qp_cur_state == -EINVAL) { /* invalid qp state */
1273 ret = -EINVAL;
1274 ehca_err(ibqp->device, "Invalid current ehca_qp_state=%x "
1275 "ehca_qp=%p qp_num=%x",
1276 mqpcb->qp_state, my_qp, ibqp->qp_num);
1277 goto modify_qp_exit1;
1278 }
1279 /*
1280 * circumvention to set aqp0 initial state to init
1281 * as expected by IB spec
1282 */
1283 if (smi_reset2init == 0 &&
1284 ibqp->qp_type == IB_QPT_SMI &&
1285 qp_cur_state == IB_QPS_RESET &&
1286 (attr_mask & IB_QP_STATE) &&
1287 attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */
1288 struct ib_qp_attr smiqp_attr = {
1289 .qp_state = IB_QPS_INIT,
1290 .port_num = my_qp->init_attr.port_num,
1291 .pkey_index = 0,
1292 .qkey = 0
1293 };
1294 int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT |
1295 IB_QP_PKEY_INDEX | IB_QP_QKEY;
1296 int smirc = internal_modify_qp(
1297 ibqp, &smiqp_attr, smiqp_attr_mask, 1);
1298 if (smirc) {
1299 ehca_err(ibqp->device, "SMI RESET -> INIT failed. "
1300 "ehca_modify_qp() rc=%i", smirc);
1301 ret = H_PARAMETER;
1302 goto modify_qp_exit1;
1303 }
1304 qp_cur_state = IB_QPS_INIT;
1305 ehca_dbg(ibqp->device, "SMI RESET -> INIT succeeded");
1306 }
1307 /* is transmitted current state equal to "real" current state */
1308 if ((attr_mask & IB_QP_CUR_STATE) &&
1309 qp_cur_state != attr->cur_qp_state) {
1310 ret = -EINVAL;
1311 ehca_err(ibqp->device,
1312 "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>"
1313 " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x",
1314 attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num);
1315 goto modify_qp_exit1;
1316 }
1317
1318 ehca_dbg(ibqp->device, "ehca_qp=%p qp_num=%x current qp_state=%x "
1319 "new qp_state=%x attribute_mask=%x",
1320 my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask);
1321
1322 qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state;
1323 if (!smi_reset2init &&
1324 !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type,
1325 attr_mask)) {
1326 ret = -EINVAL;
1327 ehca_err(ibqp->device,
1328 "Invalid qp transition new_state=%x cur_state=%x "
1329 "ehca_qp=%p qp_num=%x attr_mask=%x", qp_new_state,
1330 qp_cur_state, my_qp, ibqp->qp_num, attr_mask);
1331 goto modify_qp_exit1;
1332 }
1333
1334 mqpcb->qp_state = ib2ehca_qp_state(qp_new_state);
1335 if (mqpcb->qp_state)
1336 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
1337 else {
1338 ret = -EINVAL;
1339 ehca_err(ibqp->device, "Invalid new qp state=%x "
1340 "ehca_qp=%p qp_num=%x",
1341 qp_new_state, my_qp, ibqp->qp_num);
1342 goto modify_qp_exit1;
1343 }
1344
1345 /* retrieve state transition struct to get req and opt attrs */
1346 statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state);
1347 if (statetrans < 0) {
1348 ret = -EINVAL;
1349 ehca_err(ibqp->device, "<INVALID STATE CHANGE> qp_cur_state=%x "
1350 "new_qp_state=%x State_xsition=%x ehca_qp=%p "
1351 "qp_num=%x", qp_cur_state, qp_new_state,
1352 statetrans, my_qp, ibqp->qp_num);
1353 goto modify_qp_exit1;
1354 }
1355
1356 qp_attr_idx = ib2ehcaqptype(ibqp->qp_type);
1357
1358 if (qp_attr_idx < 0) {
1359 ret = qp_attr_idx;
1360 ehca_err(ibqp->device,
1361 "Invalid QP type=%x ehca_qp=%p qp_num=%x",
1362 ibqp->qp_type, my_qp, ibqp->qp_num);
1363 goto modify_qp_exit1;
1364 }
1365
1366 ehca_dbg(ibqp->device,
1367 "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x",
1368 my_qp, ibqp->qp_num, statetrans);
1369
1370 /* eHCA2 rev2 and higher require the SEND_GRH_FLAG to be set
1371 * in non-LL UD QPs.
1372 */
1373 if ((my_qp->qp_type == IB_QPT_UD) &&
1374 (my_qp->ext_type != EQPT_LLQP) &&
1375 (statetrans == IB_QPST_INIT2RTR) &&
1376 (shca->hw_level >= 0x22)) {
1377 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1378 mqpcb->send_grh_flag = 1;
1379 }
1380
1381 /* sqe -> rts: set purge bit of bad wqe before actual trans */
1382 if ((my_qp->qp_type == IB_QPT_UD ||
1383 my_qp->qp_type == IB_QPT_GSI ||
1384 my_qp->qp_type == IB_QPT_SMI) &&
1385 statetrans == IB_QPST_SQE2RTS) {
1386 /* mark next free wqe if kernel */
1387 if (!ibqp->uobject) {
1388 struct ehca_wqe *wqe;
1389 /* lock send queue */
1390 spin_lock_irqsave(&my_qp->spinlock_s, flags);
1391 squeue_locked = 1;
1392 /* mark next free wqe */
1393 wqe = (struct ehca_wqe *)
1394 ipz_qeit_get(&my_qp->ipz_squeue);
1395 wqe->optype = wqe->wqef = 0xff;
1396 ehca_dbg(ibqp->device, "qp_num=%x next_free_wqe=%p",
1397 ibqp->qp_num, wqe);
1398 }
1399 ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt);
1400 if (ret) {
1401 ehca_err(ibqp->device, "prepare_sqe_rts() failed "
1402 "ehca_qp=%p qp_num=%x ret=%i",
1403 my_qp, ibqp->qp_num, ret);
1404 goto modify_qp_exit2;
1405 }
1406 }
1407
1408 /*
1409 * enable RDMA_Atomic_Control if reset->init und reliable con
1410 * this is necessary since gen2 does not provide that flag,
1411 * but pHyp requires it
1412 */
1413 if (statetrans == IB_QPST_RESET2INIT &&
1414 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) {
1415 mqpcb->rdma_atomic_ctrl = 3;
1416 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1);
1417 }
1418 /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */
1419 if (statetrans == IB_QPST_INIT2RTR &&
1420 (ibqp->qp_type == IB_QPT_UC) &&
1421 !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) {
1422 mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */
1423 update_mask |=
1424 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1425 }
1426
1427 if (attr_mask & IB_QP_PKEY_INDEX) {
1428 if (attr->pkey_index >= 16) {
1429 ret = -EINVAL;
1430 ehca_err(ibqp->device, "Invalid pkey_index=%x. "
1431 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1432 attr->pkey_index, my_qp, ibqp->qp_num);
1433 goto modify_qp_exit2;
1434 }
1435 mqpcb->prim_p_key_idx = attr->pkey_index;
1436 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1);
1437 }
1438 if (attr_mask & IB_QP_PORT) {
1439 struct ehca_sport *sport;
1440 struct ehca_qp *aqp1;
1441 if (attr->port_num < 1 || attr->port_num > shca->num_ports) {
1442 ret = -EINVAL;
1443 ehca_err(ibqp->device, "Invalid port=%x. "
1444 "ehca_qp=%p qp_num=%x num_ports=%x",
1445 attr->port_num, my_qp, ibqp->qp_num,
1446 shca->num_ports);
1447 goto modify_qp_exit2;
1448 }
1449 sport = &shca->sport[attr->port_num - 1];
1450 if (!sport->ibqp_sqp[IB_QPT_GSI]) {
1451 /* should not occur */
1452 ret = -EFAULT;
1453 ehca_err(ibqp->device, "AQP1 was not created for "
1454 "port=%x", attr->port_num);
1455 goto modify_qp_exit2;
1456 }
1457 aqp1 = container_of(sport->ibqp_sqp[IB_QPT_GSI],
1458 struct ehca_qp, ib_qp);
1459 if (ibqp->qp_type != IB_QPT_GSI &&
1460 ibqp->qp_type != IB_QPT_SMI &&
1461 aqp1->mod_qp_parm) {
1462 /*
1463 * firmware will reject this modify_qp() because
1464 * port is not activated/initialized fully
1465 */
1466 ret = -EFAULT;
1467 ehca_warn(ibqp->device, "Couldn't modify qp port=%x: "
1468 "either port is being activated (try again) "
1469 "or cabling issue", attr->port_num);
1470 goto modify_qp_exit2;
1471 }
1472 mqpcb->prim_phys_port = attr->port_num;
1473 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1);
1474 }
1475 if (attr_mask & IB_QP_QKEY) {
1476 mqpcb->qkey = attr->qkey;
1477 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1);
1478 }
1479 if (attr_mask & IB_QP_AV) {
1480 mqpcb->dlid = attr->ah_attr.dlid;
1481 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1);
1482 mqpcb->source_path_bits = attr->ah_attr.src_path_bits;
1483 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1);
1484 mqpcb->service_level = attr->ah_attr.sl;
1485 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1);
1486
1487 if (ehca_calc_ipd(shca, mqpcb->prim_phys_port,
1488 attr->ah_attr.static_rate,
1489 &mqpcb->max_static_rate)) {
1490 ret = -EINVAL;
1491 goto modify_qp_exit2;
1492 }
1493 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1);
1494
1495 /*
1496 * Always supply the GRH flag, even if it's zero, to give the
1497 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1498 */
1499 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1500
1501 /*
1502 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1503 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1504 */
1505 if (attr->ah_attr.ah_flags == IB_AH_GRH) {
1506 mqpcb->send_grh_flag = 1;
1507
1508 mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index;
1509 update_mask |=
1510 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1);
1511
1512 for (cnt = 0; cnt < 16; cnt++)
1513 mqpcb->dest_gid.byte[cnt] =
1514 attr->ah_attr.grh.dgid.raw[cnt];
1515
1516 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1);
1517 mqpcb->flow_label = attr->ah_attr.grh.flow_label;
1518 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1);
1519 mqpcb->hop_limit = attr->ah_attr.grh.hop_limit;
1520 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1);
1521 mqpcb->traffic_class = attr->ah_attr.grh.traffic_class;
1522 update_mask |=
1523 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1);
1524 }
1525 }
1526
1527 if (attr_mask & IB_QP_PATH_MTU) {
1528 /* store ld(MTU) */
1529 my_qp->mtu_shift = attr->path_mtu + 7;
1530 mqpcb->path_mtu = attr->path_mtu;
1531 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1);
1532 }
1533 if (attr_mask & IB_QP_TIMEOUT) {
1534 mqpcb->timeout = attr->timeout;
1535 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1);
1536 }
1537 if (attr_mask & IB_QP_RETRY_CNT) {
1538 mqpcb->retry_count = attr->retry_cnt;
1539 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1);
1540 }
1541 if (attr_mask & IB_QP_RNR_RETRY) {
1542 mqpcb->rnr_retry_count = attr->rnr_retry;
1543 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1);
1544 }
1545 if (attr_mask & IB_QP_RQ_PSN) {
1546 mqpcb->receive_psn = attr->rq_psn;
1547 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1);
1548 }
1549 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1550 mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ?
1551 attr->max_dest_rd_atomic : 2;
1552 update_mask |=
1553 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1554 }
1555 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1556 mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ?
1557 attr->max_rd_atomic : 2;
1558 update_mask |=
1559 EHCA_BMASK_SET
1560 (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1);
1561 }
1562 if (attr_mask & IB_QP_ALT_PATH) {
1563 if (attr->alt_port_num < 1
1564 || attr->alt_port_num > shca->num_ports) {
1565 ret = -EINVAL;
1566 ehca_err(ibqp->device, "Invalid alt_port=%x. "
1567 "ehca_qp=%p qp_num=%x num_ports=%x",
1568 attr->alt_port_num, my_qp, ibqp->qp_num,
1569 shca->num_ports);
1570 goto modify_qp_exit2;
1571 }
1572 mqpcb->alt_phys_port = attr->alt_port_num;
1573
1574 if (attr->alt_pkey_index >= 16) {
1575 ret = -EINVAL;
1576 ehca_err(ibqp->device, "Invalid alt_pkey_index=%x. "
1577 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1578 attr->pkey_index, my_qp, ibqp->qp_num);
1579 goto modify_qp_exit2;
1580 }
1581 mqpcb->alt_p_key_idx = attr->alt_pkey_index;
1582
1583 mqpcb->timeout_al = attr->alt_timeout;
1584 mqpcb->dlid_al = attr->alt_ah_attr.dlid;
1585 mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits;
1586 mqpcb->service_level_al = attr->alt_ah_attr.sl;
1587
1588 if (ehca_calc_ipd(shca, mqpcb->alt_phys_port,
1589 attr->alt_ah_attr.static_rate,
1590 &mqpcb->max_static_rate_al)) {
1591 ret = -EINVAL;
1592 goto modify_qp_exit2;
1593 }
1594
1595 /* OpenIB doesn't support alternate retry counts - copy them */
1596 mqpcb->retry_count_al = mqpcb->retry_count;
1597 mqpcb->rnr_retry_count_al = mqpcb->rnr_retry_count;
1598
1599 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_ALT_PHYS_PORT, 1)
1600 | EHCA_BMASK_SET(MQPCB_MASK_ALT_P_KEY_IDX, 1)
1601 | EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT_AL, 1)
1602 | EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1)
1603 | EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1)
1604 | EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1)
1605 | EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1)
1606 | EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT_AL, 1)
1607 | EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT_AL, 1);
1608
1609 /*
1610 * Always supply the GRH flag, even if it's zero, to give the
1611 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1612 */
1613 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1);
1614
1615 /*
1616 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1617 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1618 */
1619 if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) {
1620 mqpcb->send_grh_flag_al = 1;
1621
1622 for (cnt = 0; cnt < 16; cnt++)
1623 mqpcb->dest_gid_al.byte[cnt] =
1624 attr->alt_ah_attr.grh.dgid.raw[cnt];
1625 mqpcb->source_gid_idx_al =
1626 attr->alt_ah_attr.grh.sgid_index;
1627 mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label;
1628 mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit;
1629 mqpcb->traffic_class_al =
1630 attr->alt_ah_attr.grh.traffic_class;
1631
1632 update_mask |=
1633 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1)
1634 | EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1)
1635 | EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1)
1636 | EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1) |
1637 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1);
1638 }
1639 }
1640
1641 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1642 mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer;
1643 update_mask |=
1644 EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1);
1645 }
1646
1647 if (attr_mask & IB_QP_SQ_PSN) {
1648 mqpcb->send_psn = attr->sq_psn;
1649 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1);
1650 }
1651
1652 if (attr_mask & IB_QP_DEST_QPN) {
1653 mqpcb->dest_qp_nr = attr->dest_qp_num;
1654 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1);
1655 }
1656
1657 if (attr_mask & IB_QP_PATH_MIG_STATE) {
1658 if (attr->path_mig_state != IB_MIG_REARM
1659 && attr->path_mig_state != IB_MIG_MIGRATED) {
1660 ret = -EINVAL;
1661 ehca_err(ibqp->device, "Invalid mig_state=%x",
1662 attr->path_mig_state);
1663 goto modify_qp_exit2;
1664 }
1665 mqpcb->path_migration_state = attr->path_mig_state + 1;
1666 if (attr->path_mig_state == IB_MIG_REARM)
1667 my_qp->mig_armed = 1;
1668 update_mask |=
1669 EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1);
1670 }
1671
1672 if (attr_mask & IB_QP_CAP) {
1673 mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1;
1674 update_mask |=
1675 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1);
1676 mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1;
1677 update_mask |=
1678 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1);
1679 /* no support for max_send/recv_sge yet */
1680 }
1681
1682 if (ehca_debug_level >= 2)
1683 ehca_dmp(mqpcb, 4*70, "qp_num=%x", ibqp->qp_num);
1684
1685 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1686 my_qp->ipz_qp_handle,
1687 &my_qp->pf,
1688 update_mask,
1689 mqpcb, my_qp->galpas.kernel);
1690
1691 if (h_ret != H_SUCCESS) {
1692 ret = ehca2ib_return_code(h_ret);
1693 ehca_err(ibqp->device, "hipz_h_modify_qp() failed h_ret=%lli "
1694 "ehca_qp=%p qp_num=%x", h_ret, my_qp, ibqp->qp_num);
1695 goto modify_qp_exit2;
1696 }
1697
1698 if ((my_qp->qp_type == IB_QPT_UD ||
1699 my_qp->qp_type == IB_QPT_GSI ||
1700 my_qp->qp_type == IB_QPT_SMI) &&
1701 statetrans == IB_QPST_SQE2RTS) {
1702 /* doorbell to reprocessing wqes */
1703 iosync(); /* serialize GAL register access */
1704 hipz_update_sqa(my_qp, bad_wqe_cnt-1);
1705 ehca_gen_dbg("doorbell for %x wqes", bad_wqe_cnt);
1706 }
1707
1708 if (statetrans == IB_QPST_RESET2INIT ||
1709 statetrans == IB_QPST_INIT2INIT) {
1710 mqpcb->qp_enable = 1;
1711 mqpcb->qp_state = EHCA_QPS_INIT;
1712 update_mask = 0;
1713 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
1714
1715 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1716 my_qp->ipz_qp_handle,
1717 &my_qp->pf,
1718 update_mask,
1719 mqpcb,
1720 my_qp->galpas.kernel);
1721
1722 if (h_ret != H_SUCCESS) {
1723 ret = ehca2ib_return_code(h_ret);
1724 ehca_err(ibqp->device, "ENABLE in context of "
1725 "RESET_2_INIT failed! Maybe you didn't get "
1726 "a LID h_ret=%lli ehca_qp=%p qp_num=%x",
1727 h_ret, my_qp, ibqp->qp_num);
1728 goto modify_qp_exit2;
1729 }
1730 }
1731 if ((qp_new_state == IB_QPS_ERR) && (qp_cur_state != IB_QPS_ERR)) {
1732 ret = check_for_left_cqes(my_qp, shca);
1733 if (ret)
1734 goto modify_qp_exit2;
1735 }
1736
1737 if (statetrans == IB_QPST_ANY2RESET) {
1738 ipz_qeit_reset(&my_qp->ipz_rqueue);
1739 ipz_qeit_reset(&my_qp->ipz_squeue);
1740
1741 if (qp_cur_state == IB_QPS_ERR) {
1742 del_from_err_list(my_qp->send_cq, &my_qp->sq_err_node);
1743
1744 if (HAS_RQ(my_qp))
1745 del_from_err_list(my_qp->recv_cq,
1746 &my_qp->rq_err_node);
1747 }
1748 reset_queue_map(&my_qp->sq_map);
1749
1750 if (HAS_RQ(my_qp))
1751 reset_queue_map(&my_qp->rq_map);
1752 }
1753
1754 if (attr_mask & IB_QP_QKEY)
1755 my_qp->qkey = attr->qkey;
1756
1757 modify_qp_exit2:
1758 if (squeue_locked) { /* this means: sqe -> rts */
1759 spin_unlock_irqrestore(&my_qp->spinlock_s, flags);
1760 my_qp->sqerr_purgeflag = 1;
1761 }
1762
1763 modify_qp_exit1:
1764 ehca_free_fw_ctrlblock(mqpcb);
1765
1766 return ret;
1767 }
1768
1769 int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
1770 struct ib_udata *udata)
1771 {
1772 int ret = 0;
1773
1774 struct ehca_shca *shca = container_of(ibqp->device, struct ehca_shca,
1775 ib_device);
1776 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1777
1778 /* The if-block below caches qp_attr to be modified for GSI and SMI
1779 * qps during the initialization by ib_mad. When the respective port
1780 * is activated, ie we got an event PORT_ACTIVE, we'll replay the
1781 * cached modify calls sequence, see ehca_recover_sqs() below.
1782 * Why that is required:
1783 * 1) If one port is connected, older code requires that port one
1784 * to be connected and module option nr_ports=1 to be given by
1785 * user, which is very inconvenient for end user.
1786 * 2) Firmware accepts modify_qp() only if respective port has become
1787 * active. Older code had a wait loop of 30sec create_qp()/
1788 * define_aqp1(), which is not appropriate in practice. This
1789 * code now removes that wait loop, see define_aqp1(), and always
1790 * reports all ports to ib_mad resp. users. Only activated ports
1791 * will then usable for the users.
1792 */
1793 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1794 int port = my_qp->init_attr.port_num;
1795 struct ehca_sport *sport = &shca->sport[port - 1];
1796 unsigned long flags;
1797 spin_lock_irqsave(&sport->mod_sqp_lock, flags);
1798 /* cache qp_attr only during init */
1799 if (my_qp->mod_qp_parm) {
1800 struct ehca_mod_qp_parm *p;
1801 if (my_qp->mod_qp_parm_idx >= EHCA_MOD_QP_PARM_MAX) {
1802 ehca_err(&shca->ib_device,
1803 "mod_qp_parm overflow state=%x port=%x"
1804 " type=%x", attr->qp_state,
1805 my_qp->init_attr.port_num,
1806 ibqp->qp_type);
1807 spin_unlock_irqrestore(&sport->mod_sqp_lock,
1808 flags);
1809 return -EINVAL;
1810 }
1811 p = &my_qp->mod_qp_parm[my_qp->mod_qp_parm_idx];
1812 p->mask = attr_mask;
1813 p->attr = *attr;
1814 my_qp->mod_qp_parm_idx++;
1815 ehca_dbg(&shca->ib_device,
1816 "Saved qp_attr for state=%x port=%x type=%x",
1817 attr->qp_state, my_qp->init_attr.port_num,
1818 ibqp->qp_type);
1819 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1820 goto out;
1821 }
1822 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1823 }
1824
1825 ret = internal_modify_qp(ibqp, attr, attr_mask, 0);
1826
1827 out:
1828 if ((ret == 0) && (attr_mask & IB_QP_STATE))
1829 my_qp->state = attr->qp_state;
1830
1831 return ret;
1832 }
1833
1834 void ehca_recover_sqp(struct ib_qp *sqp)
1835 {
1836 struct ehca_qp *my_sqp = container_of(sqp, struct ehca_qp, ib_qp);
1837 int port = my_sqp->init_attr.port_num;
1838 struct ib_qp_attr attr;
1839 struct ehca_mod_qp_parm *qp_parm;
1840 int i, qp_parm_idx, ret;
1841 unsigned long flags, wr_cnt;
1842
1843 if (!my_sqp->mod_qp_parm)
1844 return;
1845 ehca_dbg(sqp->device, "SQP port=%x qp_num=%x", port, sqp->qp_num);
1846
1847 qp_parm = my_sqp->mod_qp_parm;
1848 qp_parm_idx = my_sqp->mod_qp_parm_idx;
1849 for (i = 0; i < qp_parm_idx; i++) {
1850 attr = qp_parm[i].attr;
1851 ret = internal_modify_qp(sqp, &attr, qp_parm[i].mask, 0);
1852 if (ret) {
1853 ehca_err(sqp->device, "Could not modify SQP port=%x "
1854 "qp_num=%x ret=%x", port, sqp->qp_num, ret);
1855 goto free_qp_parm;
1856 }
1857 ehca_dbg(sqp->device, "SQP port=%x qp_num=%x in state=%x",
1858 port, sqp->qp_num, attr.qp_state);
1859 }
1860
1861 /* re-trigger posted recv wrs */
1862 wr_cnt = my_sqp->ipz_rqueue.current_q_offset /
1863 my_sqp->ipz_rqueue.qe_size;
1864 if (wr_cnt) {
1865 spin_lock_irqsave(&my_sqp->spinlock_r, flags);
1866 hipz_update_rqa(my_sqp, wr_cnt);
1867 spin_unlock_irqrestore(&my_sqp->spinlock_r, flags);
1868 ehca_dbg(sqp->device, "doorbell port=%x qp_num=%x wr_cnt=%lx",
1869 port, sqp->qp_num, wr_cnt);
1870 }
1871
1872 free_qp_parm:
1873 kfree(qp_parm);
1874 /* this prevents subsequent calls to modify_qp() to cache qp_attr */
1875 my_sqp->mod_qp_parm = NULL;
1876 }
1877
1878 int ehca_query_qp(struct ib_qp *qp,
1879 struct ib_qp_attr *qp_attr,
1880 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1881 {
1882 struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp);
1883 struct ehca_shca *shca = container_of(qp->device, struct ehca_shca,
1884 ib_device);
1885 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1886 struct hcp_modify_qp_control_block *qpcb;
1887 int cnt, ret = 0;
1888 u64 h_ret;
1889
1890 if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) {
1891 ehca_err(qp->device, "Invalid attribute mask "
1892 "ehca_qp=%p qp_num=%x qp_attr_mask=%x ",
1893 my_qp, qp->qp_num, qp_attr_mask);
1894 return -EINVAL;
1895 }
1896
1897 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1898 if (!qpcb) {
1899 ehca_err(qp->device, "Out of memory for qpcb "
1900 "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num);
1901 return -ENOMEM;
1902 }
1903
1904 h_ret = hipz_h_query_qp(adapter_handle,
1905 my_qp->ipz_qp_handle,
1906 &my_qp->pf,
1907 qpcb, my_qp->galpas.kernel);
1908
1909 if (h_ret != H_SUCCESS) {
1910 ret = ehca2ib_return_code(h_ret);
1911 ehca_err(qp->device, "hipz_h_query_qp() failed "
1912 "ehca_qp=%p qp_num=%x h_ret=%lli",
1913 my_qp, qp->qp_num, h_ret);
1914 goto query_qp_exit1;
1915 }
1916
1917 qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state);
1918 qp_attr->qp_state = qp_attr->cur_qp_state;
1919
1920 if (qp_attr->cur_qp_state == -EINVAL) {
1921 ret = -EINVAL;
1922 ehca_err(qp->device, "Got invalid ehca_qp_state=%x "
1923 "ehca_qp=%p qp_num=%x",
1924 qpcb->qp_state, my_qp, qp->qp_num);
1925 goto query_qp_exit1;
1926 }
1927
1928 if (qp_attr->qp_state == IB_QPS_SQD)
1929 qp_attr->sq_draining = 1;
1930
1931 qp_attr->qkey = qpcb->qkey;
1932 qp_attr->path_mtu = qpcb->path_mtu;
1933 qp_attr->path_mig_state = qpcb->path_migration_state - 1;
1934 qp_attr->rq_psn = qpcb->receive_psn;
1935 qp_attr->sq_psn = qpcb->send_psn;
1936 qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field;
1937 qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1;
1938 qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1;
1939 /* UD_AV CIRCUMVENTION */
1940 if (my_qp->qp_type == IB_QPT_UD) {
1941 qp_attr->cap.max_send_sge =
1942 qpcb->actual_nr_sges_in_sq_wqe - 2;
1943 qp_attr->cap.max_recv_sge =
1944 qpcb->actual_nr_sges_in_rq_wqe - 2;
1945 } else {
1946 qp_attr->cap.max_send_sge =
1947 qpcb->actual_nr_sges_in_sq_wqe;
1948 qp_attr->cap.max_recv_sge =
1949 qpcb->actual_nr_sges_in_rq_wqe;
1950 }
1951
1952 qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size;
1953 qp_attr->dest_qp_num = qpcb->dest_qp_nr;
1954
1955 qp_attr->pkey_index =
1956 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx);
1957
1958 qp_attr->port_num =
1959 EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port);
1960
1961 qp_attr->timeout = qpcb->timeout;
1962 qp_attr->retry_cnt = qpcb->retry_count;
1963 qp_attr->rnr_retry = qpcb->rnr_retry_count;
1964
1965 qp_attr->alt_pkey_index =
1966 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx);
1967
1968 qp_attr->alt_port_num = qpcb->alt_phys_port;
1969 qp_attr->alt_timeout = qpcb->timeout_al;
1970
1971 qp_attr->max_dest_rd_atomic = qpcb->rdma_nr_atomic_resp_res;
1972 qp_attr->max_rd_atomic = qpcb->rdma_atomic_outst_dest_qp;
1973
1974 /* primary av */
1975 qp_attr->ah_attr.sl = qpcb->service_level;
1976
1977 if (qpcb->send_grh_flag) {
1978 qp_attr->ah_attr.ah_flags = IB_AH_GRH;
1979 }
1980
1981 qp_attr->ah_attr.static_rate = qpcb->max_static_rate;
1982 qp_attr->ah_attr.dlid = qpcb->dlid;
1983 qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits;
1984 qp_attr->ah_attr.port_num = qp_attr->port_num;
1985
1986 /* primary GRH */
1987 qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class;
1988 qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit;
1989 qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx;
1990 qp_attr->ah_attr.grh.flow_label = qpcb->flow_label;
1991
1992 for (cnt = 0; cnt < 16; cnt++)
1993 qp_attr->ah_attr.grh.dgid.raw[cnt] =
1994 qpcb->dest_gid.byte[cnt];
1995
1996 /* alternate AV */
1997 qp_attr->alt_ah_attr.sl = qpcb->service_level_al;
1998 if (qpcb->send_grh_flag_al) {
1999 qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH;
2000 }
2001
2002 qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al;
2003 qp_attr->alt_ah_attr.dlid = qpcb->dlid_al;
2004 qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al;
2005
2006 /* alternate GRH */
2007 qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al;
2008 qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al;
2009 qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al;
2010 qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al;
2011
2012 for (cnt = 0; cnt < 16; cnt++)
2013 qp_attr->alt_ah_attr.grh.dgid.raw[cnt] =
2014 qpcb->dest_gid_al.byte[cnt];
2015
2016 /* return init attributes given in ehca_create_qp */
2017 if (qp_init_attr)
2018 *qp_init_attr = my_qp->init_attr;
2019
2020 if (ehca_debug_level >= 2)
2021 ehca_dmp(qpcb, 4*70, "qp_num=%x", qp->qp_num);
2022
2023 query_qp_exit1:
2024 ehca_free_fw_ctrlblock(qpcb);
2025
2026 return ret;
2027 }
2028
2029 int ehca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
2030 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
2031 {
2032 struct ehca_qp *my_qp =
2033 container_of(ibsrq, struct ehca_qp, ib_srq);
2034 struct ehca_shca *shca =
2035 container_of(ibsrq->pd->device, struct ehca_shca, ib_device);
2036 struct hcp_modify_qp_control_block *mqpcb;
2037 u64 update_mask;
2038 u64 h_ret;
2039 int ret = 0;
2040
2041 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
2042 if (!mqpcb) {
2043 ehca_err(ibsrq->device, "Could not get zeroed page for mqpcb "
2044 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
2045 return -ENOMEM;
2046 }
2047
2048 update_mask = 0;
2049 if (attr_mask & IB_SRQ_LIMIT) {
2050 attr_mask &= ~IB_SRQ_LIMIT;
2051 update_mask |=
2052 EHCA_BMASK_SET(MQPCB_MASK_CURR_SRQ_LIMIT, 1)
2053 | EHCA_BMASK_SET(MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG, 1);
2054 mqpcb->curr_srq_limit =
2055 EHCA_BMASK_SET(MQPCB_CURR_SRQ_LIMIT, attr->srq_limit);
2056 mqpcb->qp_aff_asyn_ev_log_reg =
2057 EHCA_BMASK_SET(QPX_AAELOG_RESET_SRQ_LIMIT, 1);
2058 }
2059
2060 /* by now, all bits in attr_mask should have been cleared */
2061 if (attr_mask) {
2062 ehca_err(ibsrq->device, "invalid attribute mask bits set "
2063 "attr_mask=%x", attr_mask);
2064 ret = -EINVAL;
2065 goto modify_srq_exit0;
2066 }
2067
2068 if (ehca_debug_level >= 2)
2069 ehca_dmp(mqpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
2070
2071 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, my_qp->ipz_qp_handle,
2072 NULL, update_mask, mqpcb,
2073 my_qp->galpas.kernel);
2074
2075 if (h_ret != H_SUCCESS) {
2076 ret = ehca2ib_return_code(h_ret);
2077 ehca_err(ibsrq->device, "hipz_h_modify_qp() failed h_ret=%lli "
2078 "ehca_qp=%p qp_num=%x",
2079 h_ret, my_qp, my_qp->real_qp_num);
2080 }
2081
2082 modify_srq_exit0:
2083 ehca_free_fw_ctrlblock(mqpcb);
2084
2085 return ret;
2086 }
2087
2088 int ehca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr)
2089 {
2090 struct ehca_qp *my_qp = container_of(srq, struct ehca_qp, ib_srq);
2091 struct ehca_shca *shca = container_of(srq->device, struct ehca_shca,
2092 ib_device);
2093 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
2094 struct hcp_modify_qp_control_block *qpcb;
2095 int ret = 0;
2096 u64 h_ret;
2097
2098 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
2099 if (!qpcb) {
2100 ehca_err(srq->device, "Out of memory for qpcb "
2101 "ehca_qp=%p qp_num=%x", my_qp, my_qp->real_qp_num);
2102 return -ENOMEM;
2103 }
2104
2105 h_ret = hipz_h_query_qp(adapter_handle, my_qp->ipz_qp_handle,
2106 NULL, qpcb, my_qp->galpas.kernel);
2107
2108 if (h_ret != H_SUCCESS) {
2109 ret = ehca2ib_return_code(h_ret);
2110 ehca_err(srq->device, "hipz_h_query_qp() failed "
2111 "ehca_qp=%p qp_num=%x h_ret=%lli",
2112 my_qp, my_qp->real_qp_num, h_ret);
2113 goto query_srq_exit1;
2114 }
2115
2116 srq_attr->max_wr = qpcb->max_nr_outst_recv_wr - 1;
2117 srq_attr->max_sge = 3;
2118 srq_attr->srq_limit = EHCA_BMASK_GET(
2119 MQPCB_CURR_SRQ_LIMIT, qpcb->curr_srq_limit);
2120
2121 if (ehca_debug_level >= 2)
2122 ehca_dmp(qpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
2123
2124 query_srq_exit1:
2125 ehca_free_fw_ctrlblock(qpcb);
2126
2127 return ret;
2128 }
2129
2130 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
2131 struct ib_uobject *uobject)
2132 {
2133 struct ehca_shca *shca = container_of(dev, struct ehca_shca, ib_device);
2134 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
2135 ib_pd);
2136 struct ehca_sport *sport = &shca->sport[my_qp->init_attr.port_num - 1];
2137 u32 qp_num = my_qp->real_qp_num;
2138 int ret;
2139 u64 h_ret;
2140 u8 port_num;
2141 enum ib_qp_type qp_type;
2142 unsigned long flags;
2143
2144 if (uobject) {
2145 if (my_qp->mm_count_galpa ||
2146 my_qp->mm_count_rqueue || my_qp->mm_count_squeue) {
2147 ehca_err(dev, "Resources still referenced in "
2148 "user space qp_num=%x", qp_num);
2149 return -EINVAL;
2150 }
2151 }
2152
2153 if (my_qp->send_cq) {
2154 ret = ehca_cq_unassign_qp(my_qp->send_cq, qp_num);
2155 if (ret) {
2156 ehca_err(dev, "Couldn't unassign qp from "
2157 "send_cq ret=%i qp_num=%x cq_num=%x", ret,
2158 qp_num, my_qp->send_cq->cq_number);
2159 return ret;
2160 }
2161 }
2162
2163 write_lock_irqsave(&ehca_qp_idr_lock, flags);
2164 idr_remove(&ehca_qp_idr, my_qp->token);
2165 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
2166
2167 /*
2168 * SRQs will never get into an error list and do not have a recv_cq,
2169 * so we need to skip them here.
2170 */
2171 if (HAS_RQ(my_qp) && !IS_SRQ(my_qp))
2172 del_from_err_list(my_qp->recv_cq, &my_qp->rq_err_node);
2173
2174 if (HAS_SQ(my_qp))
2175 del_from_err_list(my_qp->send_cq, &my_qp->sq_err_node);
2176
2177 /* now wait until all pending events have completed */
2178 wait_event(my_qp->wait_completion, !atomic_read(&my_qp->nr_events));
2179
2180 h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
2181 if (h_ret != H_SUCCESS) {
2182 ehca_err(dev, "hipz_h_destroy_qp() failed h_ret=%lli "
2183 "ehca_qp=%p qp_num=%x", h_ret, my_qp, qp_num);
2184 return ehca2ib_return_code(h_ret);
2185 }
2186
2187 port_num = my_qp->init_attr.port_num;
2188 qp_type = my_qp->init_attr.qp_type;
2189
2190 if (qp_type == IB_QPT_SMI || qp_type == IB_QPT_GSI) {
2191 spin_lock_irqsave(&sport->mod_sqp_lock, flags);
2192 kfree(my_qp->mod_qp_parm);
2193 my_qp->mod_qp_parm = NULL;
2194 shca->sport[port_num - 1].ibqp_sqp[qp_type] = NULL;
2195 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
2196 }
2197
2198 /* no support for IB_QPT_SMI yet */
2199 if (qp_type == IB_QPT_GSI) {
2200 struct ib_event event;
2201 ehca_info(dev, "device %s: port %x is inactive.",
2202 shca->ib_device.name, port_num);
2203 event.device = &shca->ib_device;
2204 event.event = IB_EVENT_PORT_ERR;
2205 event.element.port_num = port_num;
2206 shca->sport[port_num - 1].port_state = IB_PORT_DOWN;
2207 ib_dispatch_event(&event);
2208 }
2209
2210 if (HAS_RQ(my_qp)) {
2211 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
2212
2213 vfree(my_qp->rq_map.map);
2214 }
2215 if (HAS_SQ(my_qp)) {
2216 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
2217
2218 vfree(my_qp->sq_map.map);
2219 }
2220 kmem_cache_free(qp_cache, my_qp);
2221 atomic_dec(&shca->num_qps);
2222 return 0;
2223 }
2224
2225 int ehca_destroy_qp(struct ib_qp *qp)
2226 {
2227 return internal_destroy_qp(qp->device,
2228 container_of(qp, struct ehca_qp, ib_qp),
2229 qp->uobject);
2230 }
2231
2232 int ehca_destroy_srq(struct ib_srq *srq)
2233 {
2234 return internal_destroy_qp(srq->device,
2235 container_of(srq, struct ehca_qp, ib_srq),
2236 srq->uobject);
2237 }
2238
2239 int ehca_init_qp_cache(void)
2240 {
2241 qp_cache = kmem_cache_create("ehca_cache_qp",
2242 sizeof(struct ehca_qp), 0,
2243 SLAB_HWCACHE_ALIGN,
2244 NULL);
2245 if (!qp_cache)
2246 return -ENOMEM;
2247 return 0;
2248 }
2249
2250 void ehca_cleanup_qp_cache(void)
2251 {
2252 if (qp_cache)
2253 kmem_cache_destroy(qp_cache);
2254 }
Linux with added FPC-III support