drivers/net/sfc/mdio_10g.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2006-2008 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9 /*
  10  * Useful functions for working with MDIO clause 45 PHYs
  11  */
  12 #include <linux/types.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/delay.h>
  15 #include "net_driver.h"
  16 #include "mdio_10g.h"
  17 #include "boards.h"
  18 #include "workarounds.h"
  19
  20 unsigned mdio_id_oui(u32 id)
  21 {
  22         unsigned oui = 0;
  23         int i;
  24
  25         /* The bits of the OUI are designated a..x, with a=0 and b variable.
  26          * In the id register c is the MSB but the OUI is conventionally
  27          * written as bytes h..a, p..i, x..q.  Reorder the bits accordingly. */
  28         for (i = 0; i < 22; ++i)
  29                 if (id & (1 << (i + 10)))
  30                         oui |= 1 << (i ^ 7);
  31
  32         return oui;
  33 }
  34
  35 int mdio_clause45_reset_mmd(struct efx_nic *port, int mmd,
  36                             int spins, int spintime)
  37 {
  38         u32 ctrl;
  39         int phy_id = port->mii.phy_id;
  40
  41         /* Catch callers passing values in the wrong units (or just silly) */
  42         EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
  43
  44         mdio_clause45_write(port, phy_id, mmd, MDIO_MMDREG_CTRL1,
  45                             (1 << MDIO_MMDREG_CTRL1_RESET_LBN));
  46         /* Wait for the reset bit to clear. */
  47         do {
  48                 msleep(spintime);
  49                 ctrl = mdio_clause45_read(port, phy_id, mmd, MDIO_MMDREG_CTRL1);
  50                 spins--;
  51
  52         } while (spins && (ctrl & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)));
  53
  54         return spins ? spins : -ETIMEDOUT;
  55 }
  56
  57 static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd,
  58                                    int fault_fatal)
  59 {
  60         int status;
  61         int phy_id = efx->mii.phy_id;
  62
  63         if (LOOPBACK_INTERNAL(efx))
  64                 return 0;
  65
  66         if (mmd != MDIO_MMD_AN) {
  67                 /* Read MMD STATUS2 to check it is responding. */
  68                 status = mdio_clause45_read(efx, phy_id, mmd,
  69                                             MDIO_MMDREG_STAT2);
  70                 if (((status >> MDIO_MMDREG_STAT2_PRESENT_LBN) &
  71                      ((1 << MDIO_MMDREG_STAT2_PRESENT_WIDTH) - 1)) !=
  72                     MDIO_MMDREG_STAT2_PRESENT_VAL) {
  73                         EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd);
  74                         return -EIO;
  75                 }
  76         }
  77
  78         /* Read MMD STATUS 1 to check for fault. */
  79         status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT1);
  80         if ((status & (1 << MDIO_MMDREG_STAT1_FAULT_LBN)) != 0) {
  81                 if (fault_fatal) {
  82                         EFX_ERR(efx, "PHY MMD %d reporting fatal"
  83                                 " fault: status %x\n", mmd, status);
  84                         return -EIO;
  85                 } else {
  86                         EFX_LOG(efx, "PHY MMD %d reporting status"
  87                                 " %x (expected)\n", mmd, status);
  88                 }
  89         }
  90         return 0;
  91 }
  92
  93 /* This ought to be ridiculous overkill. We expect it to fail rarely */
  94 #define MDIO45_RESET_TIME       1000 /* ms */
  95 #define MDIO45_RESET_ITERS      100
  96
  97 int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
  98                                   unsigned int mmd_mask)
  99 {
 100         const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
 101         int tries = MDIO45_RESET_ITERS;
 102         int rc = 0;
 103         int in_reset;
 104
 105         while (tries) {
 106                 int mask = mmd_mask;
 107                 int mmd = 0;
 108                 int stat;
 109                 in_reset = 0;
 110                 while (mask) {
 111                         if (mask & 1) {
 112                                 stat = mdio_clause45_read(efx,
 113                                                           efx->mii.phy_id,
 114                                                           mmd,
 115                                                           MDIO_MMDREG_CTRL1);
 116                                 if (stat < 0) {
 117                                         EFX_ERR(efx, "failed to read status of"
 118                                                 " MMD %d\n", mmd);
 119                                         return -EIO;
 120                                 }
 121                                 if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
 122                                         in_reset |= (1 << mmd);
 123                         }
 124                         mask = mask >> 1;
 125                         mmd++;
 126                 }
 127                 if (!in_reset)
 128                         break;
 129                 tries--;
 130                 msleep(spintime);
 131         }
 132         if (in_reset != 0) {
 133                 EFX_ERR(efx, "not all MMDs came out of reset in time."
 134                         " MMDs still in reset: %x\n", in_reset);
 135                 rc = -ETIMEDOUT;
 136         }
 137         return rc;
 138 }
 139
 140 int mdio_clause45_check_mmds(struct efx_nic *efx,
 141                              unsigned int mmd_mask, unsigned int fatal_mask)
 142 {
 143         int mmd = 0, probe_mmd, devs0, devs1;
 144         u32 devices;
 145
 146         /* Historically we have probed the PHYXS to find out what devices are
 147          * present,but that doesn't work so well if the PHYXS isn't expected
 148          * to exist, if so just find the first item in the list supplied. */
 149         probe_mmd = (mmd_mask & MDIO_MMDREG_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
 150             __ffs(mmd_mask);
 151
 152         /* Check all the expected MMDs are present */
 153         devs0 = mdio_clause45_read(efx, efx->mii.phy_id,
 154                                    probe_mmd, MDIO_MMDREG_DEVS0);
 155         devs1 = mdio_clause45_read(efx, efx->mii.phy_id,
 156                                    probe_mmd, MDIO_MMDREG_DEVS1);
 157         if (devs0 < 0 || devs1 < 0) {
 158                 EFX_ERR(efx, "failed to read devices present\n");
 159                 return -EIO;
 160         }
 161         devices = devs0 | (devs1 << 16);
 162         if ((devices & mmd_mask) != mmd_mask) {
 163                 EFX_ERR(efx, "required MMDs not present: got %x, "
 164                         "wanted %x\n", devices, mmd_mask);
 165                 return -ENODEV;
 166         }
 167         EFX_TRACE(efx, "Devices present: %x\n", devices);
 168
 169         /* Check all required MMDs are responding and happy. */
 170         while (mmd_mask) {
 171                 if (mmd_mask & 1) {
 172                         int fault_fatal = fatal_mask & 1;
 173                         if (mdio_clause45_check_mmd(efx, mmd, fault_fatal))
 174                                 return -EIO;
 175                 }
 176                 mmd_mask = mmd_mask >> 1;
 177                 fatal_mask = fatal_mask >> 1;
 178                 mmd++;
 179         }
 180
 181         return 0;
 182 }
 183
 184 bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
 185 {
 186         int phy_id = efx->mii.phy_id;
 187         u32 reg;
 188         bool ok = true;
 189         int mmd = 0;
 190
 191         /* If the port is in loopback, then we should only consider a subset
 192          * of mmd's */
 193         if (LOOPBACK_INTERNAL(efx))
 194                 return true;
 195         else if (efx->loopback_mode == LOOPBACK_NETWORK)
 196                 return false;
 197         else if (efx_phy_mode_disabled(efx->phy_mode))
 198                 return false;
 199         else if (efx->loopback_mode == LOOPBACK_PHYXS)
 200                 mmd_mask &= ~(MDIO_MMDREG_DEVS_PHYXS |
 201                               MDIO_MMDREG_DEVS_PCS |
 202                               MDIO_MMDREG_DEVS_PMAPMD |
 203                               MDIO_MMDREG_DEVS_AN);
 204         else if (efx->loopback_mode == LOOPBACK_PCS)
 205                 mmd_mask &= ~(MDIO_MMDREG_DEVS_PCS |
 206                               MDIO_MMDREG_DEVS_PMAPMD |
 207                               MDIO_MMDREG_DEVS_AN);
 208         else if (efx->loopback_mode == LOOPBACK_PMAPMD)
 209                 mmd_mask &= ~(MDIO_MMDREG_DEVS_PMAPMD |
 210                               MDIO_MMDREG_DEVS_AN);
 211
 212         if (!mmd_mask) {
 213                 /* Use presence of XGMII faults in leui of link state */
 214                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
 215                                          MDIO_PHYXS_STATUS2);
 216                 return !(reg & (1 << MDIO_PHYXS_STATUS2_RX_FAULT_LBN));
 217         }
 218
 219         while (mmd_mask) {
 220                 if (mmd_mask & 1) {
 221                         /* Double reads because link state is latched, and a
 222                          * read moves the current state into the register */
 223                         reg = mdio_clause45_read(efx, phy_id,
 224                                                  mmd, MDIO_MMDREG_STAT1);
 225                         reg = mdio_clause45_read(efx, phy_id,
 226                                                  mmd, MDIO_MMDREG_STAT1);
 227                         ok = ok && (reg & (1 << MDIO_MMDREG_STAT1_LINK_LBN));
 228                 }
 229                 mmd_mask = (mmd_mask >> 1);
 230                 mmd++;
 231         }
 232         return ok;
 233 }
 234
 235 void mdio_clause45_transmit_disable(struct efx_nic *efx)
 236 {
 237         mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 238                                MDIO_MMDREG_TXDIS, MDIO_MMDREG_TXDIS_GLOBAL_LBN,
 239                                efx->phy_mode & PHY_MODE_TX_DISABLED);
 240 }
 241
 242 void mdio_clause45_phy_reconfigure(struct efx_nic *efx)
 243 {
 244         int phy_id = efx->mii.phy_id;
 245
 246         mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
 247                                MDIO_MMDREG_CTRL1, MDIO_PMAPMD_CTRL1_LBACK_LBN,
 248                                efx->loopback_mode == LOOPBACK_PMAPMD);
 249         mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PCS,
 250                                MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
 251                                efx->loopback_mode == LOOPBACK_PCS);
 252         mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
 253                                MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
 254                                efx->loopback_mode == LOOPBACK_NETWORK);
 255 }
 256
 257 static void mdio_clause45_set_mmd_lpower(struct efx_nic *efx,
 258                                          int lpower, int mmd)
 259 {
 260         int phy = efx->mii.phy_id;
 261         int stat = mdio_clause45_read(efx, phy, mmd, MDIO_MMDREG_STAT1);
 262
 263         EFX_TRACE(efx, "Setting low power mode for MMD %d to %d\n",
 264                   mmd, lpower);
 265
 266         if (stat & (1 << MDIO_MMDREG_STAT1_LPABLE_LBN)) {
 267                 mdio_clause45_set_flag(efx, phy, mmd, MDIO_MMDREG_CTRL1,
 268                                        MDIO_MMDREG_CTRL1_LPOWER_LBN, lpower);
 269         }
 270 }
 271
 272 void mdio_clause45_set_mmds_lpower(struct efx_nic *efx,
 273                                    int low_power, unsigned int mmd_mask)
 274 {
 275         int mmd = 0;
 276         mmd_mask &= ~MDIO_MMDREG_DEVS_AN;
 277         while (mmd_mask) {
 278                 if (mmd_mask & 1)
 279                         mdio_clause45_set_mmd_lpower(efx, low_power, mmd);
 280                 mmd_mask = (mmd_mask >> 1);
 281                 mmd++;
 282         }
 283 }
 284
 285 static u32 mdio_clause45_get_an(struct efx_nic *efx, u16 addr)
 286 {
 287         int phy_id = efx->mii.phy_id;
 288         u32 result = 0;
 289         int reg;
 290
 291         reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, addr);
 292         if (reg & ADVERTISE_10HALF)
 293                 result |= ADVERTISED_10baseT_Half;
 294         if (reg & ADVERTISE_10FULL)
 295                 result |= ADVERTISED_10baseT_Full;
 296         if (reg & ADVERTISE_100HALF)
 297                 result |= ADVERTISED_100baseT_Half;
 298         if (reg & ADVERTISE_100FULL)
 299                 result |= ADVERTISED_100baseT_Full;
 300         return result;
 301 }
 302
 303 /**
 304  * mdio_clause45_get_settings - Read (some of) the PHY settings over MDIO.
 305  * @efx:                Efx NIC
 306  * @ecmd:               Buffer for settings
 307  *
 308  * On return the 'port', 'speed', 'supported' and 'advertising' fields of
 309  * ecmd have been filled out.
 310  */
 311 void mdio_clause45_get_settings(struct efx_nic *efx,
 312                                 struct ethtool_cmd *ecmd)
 313 {
 314         mdio_clause45_get_settings_ext(efx, ecmd, 0, 0);
 315 }
 316
 317 /**
 318  * mdio_clause45_get_settings_ext - Read (some of) the PHY settings over MDIO.
 319  * @efx:                Efx NIC
 320  * @ecmd:               Buffer for settings
 321  * @xnp:                Advertised Extended Next Page state
 322  * @xnp_lpa:            Link Partner's advertised XNP state
 323  *
 324  * On return the 'port', 'speed', 'supported' and 'advertising' fields of
 325  * ecmd have been filled out.
 326  */
 327 void mdio_clause45_get_settings_ext(struct efx_nic *efx,
 328                                     struct ethtool_cmd *ecmd,
 329                                     u32 npage_adv, u32 npage_lpa)
 330 {
 331         int phy_id = efx->mii.phy_id;
 332         int reg;
 333
 334         ecmd->transceiver = XCVR_INTERNAL;
 335         ecmd->phy_address = phy_id;
 336
 337         reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 338                                  MDIO_MMDREG_CTRL2);
 339         switch (reg & MDIO_PMAPMD_CTRL2_TYPE_MASK) {
 340         case MDIO_PMAPMD_CTRL2_10G_BT:
 341         case MDIO_PMAPMD_CTRL2_1G_BT:
 342         case MDIO_PMAPMD_CTRL2_100_BT:
 343         case MDIO_PMAPMD_CTRL2_10_BT:
 344                 ecmd->port = PORT_TP;
 345                 ecmd->supported = SUPPORTED_TP;
 346                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 347                                          MDIO_MMDREG_SPEED);
 348                 if (reg & (1 << MDIO_MMDREG_SPEED_10G_LBN))
 349                         ecmd->supported |= SUPPORTED_10000baseT_Full;
 350                 if (reg & (1 << MDIO_MMDREG_SPEED_1000M_LBN))
 351                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
 352                                             SUPPORTED_1000baseT_Half);
 353                 if (reg & (1 << MDIO_MMDREG_SPEED_100M_LBN))
 354                         ecmd->supported |= (SUPPORTED_100baseT_Full |
 355                                             SUPPORTED_100baseT_Half);
 356                 if (reg & (1 << MDIO_MMDREG_SPEED_10M_LBN))
 357                         ecmd->supported |= (SUPPORTED_10baseT_Full |
 358                                             SUPPORTED_10baseT_Half);
 359                 ecmd->advertising = ADVERTISED_TP;
 360                 break;
 361
 362         /* We represent CX4 as fibre in the absence of anything better */
 363         case MDIO_PMAPMD_CTRL2_10G_CX4:
 364         /* All the other defined modes are flavours of optical */
 365         default:
 366                 ecmd->port = PORT_FIBRE;
 367                 ecmd->supported = SUPPORTED_FIBRE;
 368                 ecmd->advertising = ADVERTISED_FIBRE;
 369                 break;
 370         }
 371
 372         if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
 373                 ecmd->supported |= SUPPORTED_Autoneg;
 374                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 375                                          MDIO_MMDREG_CTRL1);
 376                 if (reg & BMCR_ANENABLE) {
 377                         ecmd->autoneg = AUTONEG_ENABLE;
 378                         ecmd->advertising |=
 379                                 ADVERTISED_Autoneg |
 380                                 mdio_clause45_get_an(efx, MDIO_AN_ADVERTISE) |
 381                                 npage_adv;
 382                 } else
 383                         ecmd->autoneg = AUTONEG_DISABLE;
 384         } else
 385                 ecmd->autoneg = AUTONEG_DISABLE;
 386
 387         if (ecmd->autoneg) {
 388                 /* If AN is complete, report best common mode,
 389                  * otherwise report best advertised mode. */
 390                 u32 modes = 0;
 391                 if (mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 392                                        MDIO_MMDREG_STAT1) &
 393                     (1 << MDIO_AN_STATUS_AN_DONE_LBN))
 394                         modes = (ecmd->advertising &
 395                                  (mdio_clause45_get_an(efx, MDIO_AN_LPA) |
 396                                   npage_lpa));
 397                 if (modes == 0)
 398                         modes = ecmd->advertising;
 399
 400                 if (modes & ADVERTISED_10000baseT_Full) {
 401                         ecmd->speed = SPEED_10000;
 402                         ecmd->duplex = DUPLEX_FULL;
 403                 } else if (modes & (ADVERTISED_1000baseT_Full |
 404                                     ADVERTISED_1000baseT_Half)) {
 405                         ecmd->speed = SPEED_1000;
 406                         ecmd->duplex = !!(modes & ADVERTISED_1000baseT_Full);
 407                 } else if (modes & (ADVERTISED_100baseT_Full |
 408                                     ADVERTISED_100baseT_Half)) {
 409                         ecmd->speed = SPEED_100;
 410                         ecmd->duplex = !!(modes & ADVERTISED_100baseT_Full);
 411                 } else {
 412                         ecmd->speed = SPEED_10;
 413                         ecmd->duplex = !!(modes & ADVERTISED_10baseT_Full);
 414                 }
 415         } else {
 416                 /* Report forced settings */
 417                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 418                                          MDIO_MMDREG_CTRL1);
 419                 ecmd->speed = (((reg & BMCR_SPEED1000) ? 100 : 1) *
 420                                ((reg & BMCR_SPEED100) ? 100 : 10));
 421                 ecmd->duplex = (reg & BMCR_FULLDPLX ||
 422                                 ecmd->speed == SPEED_10000);
 423         }
 424 }
 425
 426 /**
 427  * mdio_clause45_set_settings - Set (some of) the PHY settings over MDIO.
 428  * @efx:                Efx NIC
 429  * @ecmd:               New settings
 430  */
 431 int mdio_clause45_set_settings(struct efx_nic *efx,
 432                                struct ethtool_cmd *ecmd)
 433 {
 434         int phy_id = efx->mii.phy_id;
 435         struct ethtool_cmd prev;
 436         u32 required;
 437         int reg;
 438
 439         efx->phy_op->get_settings(efx, &prev);
 440
 441         if (ecmd->advertising == prev.advertising &&
 442             ecmd->speed == prev.speed &&
 443             ecmd->duplex == prev.duplex &&
 444             ecmd->port == prev.port &&
 445             ecmd->autoneg == prev.autoneg)
 446                 return 0;
 447
 448         /* We can only change these settings for -T PHYs */
 449         if (prev.port != PORT_TP || ecmd->port != PORT_TP)
 450                 return -EINVAL;
 451
 452         /* Check that PHY supports these settings */
 453         if (ecmd->autoneg) {
 454                 required = SUPPORTED_Autoneg;
 455         } else if (ecmd->duplex) {
 456                 switch (ecmd->speed) {
 457                 case SPEED_10:  required = SUPPORTED_10baseT_Full;  break;
 458                 case SPEED_100: required = SUPPORTED_100baseT_Full; break;
 459                 default:        return -EINVAL;
 460                 }
 461         } else {
 462                 switch (ecmd->speed) {
 463                 case SPEED_10:  required = SUPPORTED_10baseT_Half;  break;
 464                 case SPEED_100: required = SUPPORTED_100baseT_Half; break;
 465                 default:        return -EINVAL;
 466                 }
 467         }
 468         required |= ecmd->advertising;
 469         if (required & ~prev.supported)
 470                 return -EINVAL;
 471
 472         if (ecmd->autoneg) {
 473                 bool xnp = (ecmd->advertising & ADVERTISED_10000baseT_Full
 474                             || EFX_WORKAROUND_13204(efx));
 475
 476                 /* Set up the base page */
 477                 reg = ADVERTISE_CSMA;
 478                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
 479                         reg |= ADVERTISE_10HALF;
 480                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
 481                         reg |= ADVERTISE_10FULL;
 482                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
 483                         reg |= ADVERTISE_100HALF;
 484                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
 485                         reg |= ADVERTISE_100FULL;
 486                 if (xnp)
 487                         reg |= ADVERTISE_RESV;
 488                 else if (ecmd->advertising & (ADVERTISED_1000baseT_Half |
 489                                               ADVERTISED_1000baseT_Full))
 490                         reg |= ADVERTISE_NPAGE;
 491                 reg |= efx_fc_advertise(efx->wanted_fc);
 492                 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
 493                                     MDIO_AN_ADVERTISE, reg);
 494
 495                 /* Set up the (extended) next page if necessary */
 496                 if (efx->phy_op->set_npage_adv)
 497                         efx->phy_op->set_npage_adv(efx, ecmd->advertising);
 498
 499                 /* Enable and restart AN */
 500                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 501                                          MDIO_MMDREG_CTRL1);
 502                 reg |= BMCR_ANENABLE;
 503                 if (!(EFX_WORKAROUND_15195(efx) &&
 504                       LOOPBACK_MASK(efx) & efx->phy_op->loopbacks))
 505                         reg |= BMCR_ANRESTART;
 506                 if (xnp)
 507                         reg |= 1 << MDIO_AN_CTRL_XNP_LBN;
 508                 else
 509                         reg &= ~(1 << MDIO_AN_CTRL_XNP_LBN);
 510                 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
 511                                     MDIO_MMDREG_CTRL1, reg);
 512         } else {
 513                 /* Disable AN */
 514                 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN,
 515                                        MDIO_MMDREG_CTRL1,
 516                                        __ffs(BMCR_ANENABLE), false);
 517
 518                 /* Set the basic control bits */
 519                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 520                                          MDIO_MMDREG_CTRL1);
 521                 reg &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX |
 522                          0x003c);
 523                 if (ecmd->speed == SPEED_100)
 524                         reg |= BMCR_SPEED100;
 525                 if (ecmd->duplex)
 526                         reg |= BMCR_FULLDPLX;
 527                 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
 528                                     MDIO_MMDREG_CTRL1, reg);
 529         }
 530
 531         return 0;
 532 }
 533
 534 void mdio_clause45_set_pause(struct efx_nic *efx)
 535 {
 536         int phy_id = efx->mii.phy_id;
 537         int reg;
 538
 539         if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
 540                 /* Set pause capability advertising */
 541                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 542                                          MDIO_AN_ADVERTISE);
 543                 reg &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 544                 reg |= efx_fc_advertise(efx->wanted_fc);
 545                 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
 546                                     MDIO_AN_ADVERTISE, reg);
 547
 548                 /* Restart auto-negotiation */
 549                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 550                                          MDIO_MMDREG_CTRL1);
 551                 if (reg & BMCR_ANENABLE) {
 552                         reg |= BMCR_ANRESTART;
 553                         mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
 554                                             MDIO_MMDREG_CTRL1, reg);
 555                 }
 556         }
 557 }
 558
 559 enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx)
 560 {
 561         int phy_id = efx->mii.phy_id;
 562         int lpa;
 563
 564         if (!(efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)))
 565                 return efx->wanted_fc;
 566         lpa = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_AN_LPA);
 567         return efx_fc_resolve(efx->wanted_fc, lpa);
 568 }
 569
 570 void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev,
 571                             u16 addr, int bit, bool sense)
 572 {
 573         int old_val = mdio_clause45_read(efx, prt, dev, addr);
 574         int new_val;
 575
 576         if (sense)
 577                 new_val = old_val | (1 << bit);
 578         else
 579                 new_val = old_val & ~(1 << bit);
 580         if (old_val != new_val)
 581                 mdio_clause45_write(efx, prt, dev, addr, new_val);
 582 }