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x86, UV: Fix for nodes with memory and no cpus
[linux/fpc-iii.git] / drivers / net / ucc_geth.c
blobd3f39e86eb95a14cb8cad1b1120377fa5a3b80dc
1 /*
2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_platform.h>
31
32 #include <asm/uaccess.h>
33 #include <asm/irq.h>
34 #include <asm/io.h>
35 #include <asm/immap_qe.h>
36 #include <asm/qe.h>
37 #include <asm/ucc.h>
38 #include <asm/ucc_fast.h>
39
40 #include "ucc_geth.h"
41 #include "fsl_pq_mdio.h"
42
43 #undef DEBUG
44
45 #define ugeth_printk(level, format, arg...) \
46 printk(level format "\n", ## arg)
47
48 #define ugeth_dbg(format, arg...) \
49 ugeth_printk(KERN_DEBUG , format , ## arg)
50 #define ugeth_err(format, arg...) \
51 ugeth_printk(KERN_ERR , format , ## arg)
52 #define ugeth_info(format, arg...) \
53 ugeth_printk(KERN_INFO , format , ## arg)
54 #define ugeth_warn(format, arg...) \
55 ugeth_printk(KERN_WARNING , format , ## arg)
56
57 #ifdef UGETH_VERBOSE_DEBUG
58 #define ugeth_vdbg ugeth_dbg
59 #else
60 #define ugeth_vdbg(fmt, args...) do { } while (0)
61 #endif /* UGETH_VERBOSE_DEBUG */
62 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
63
64
65 static DEFINE_SPINLOCK(ugeth_lock);
66
67 static struct {
68 u32 msg_enable;
69 } debug = { -1 };
70
71 module_param_named(debug, debug.msg_enable, int, 0);
72 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
73
74 static struct ucc_geth_info ugeth_primary_info = {
75 .uf_info = {
76 .bd_mem_part = MEM_PART_SYSTEM,
77 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
78 .max_rx_buf_length = 1536,
79 /* adjusted at startup if max-speed 1000 */
80 .urfs = UCC_GETH_URFS_INIT,
81 .urfet = UCC_GETH_URFET_INIT,
82 .urfset = UCC_GETH_URFSET_INIT,
83 .utfs = UCC_GETH_UTFS_INIT,
84 .utfet = UCC_GETH_UTFET_INIT,
85 .utftt = UCC_GETH_UTFTT_INIT,
86 .ufpt = 256,
87 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
88 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
89 .tenc = UCC_FAST_TX_ENCODING_NRZ,
90 .renc = UCC_FAST_RX_ENCODING_NRZ,
91 .tcrc = UCC_FAST_16_BIT_CRC,
92 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
93 },
94 .numQueuesTx = 1,
95 .numQueuesRx = 1,
96 .extendedFilteringChainPointer = ((uint32_t) NULL),
97 .typeorlen = 3072 /*1536 */ ,
98 .nonBackToBackIfgPart1 = 0x40,
99 .nonBackToBackIfgPart2 = 0x60,
100 .miminumInterFrameGapEnforcement = 0x50,
101 .backToBackInterFrameGap = 0x60,
102 .mblinterval = 128,
103 .nortsrbytetime = 5,
104 .fracsiz = 1,
105 .strictpriorityq = 0xff,
106 .altBebTruncation = 0xa,
107 .excessDefer = 1,
108 .maxRetransmission = 0xf,
109 .collisionWindow = 0x37,
110 .receiveFlowControl = 1,
111 .transmitFlowControl = 1,
112 .maxGroupAddrInHash = 4,
113 .maxIndAddrInHash = 4,
114 .prel = 7,
115 .maxFrameLength = 1518,
116 .minFrameLength = 64,
117 .maxD1Length = 1520,
118 .maxD2Length = 1520,
119 .vlantype = 0x8100,
120 .ecamptr = ((uint32_t) NULL),
121 .eventRegMask = UCCE_OTHER,
122 .pausePeriod = 0xf000,
123 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
124 .bdRingLenTx = {
125 TX_BD_RING_LEN,
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN},
133
134 .bdRingLenRx = {
135 RX_BD_RING_LEN,
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN},
143
144 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
145 .largestexternallookupkeysize =
146 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
147 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
148 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
150 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
151 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
152 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
153 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
154 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
155 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
156 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
157 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
158 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 };
160
161 static struct ucc_geth_info ugeth_info[8];
162
163 #ifdef DEBUG
164 static void mem_disp(u8 *addr, int size)
165 {
166 u8 *i;
167 int size16Aling = (size >> 4) << 4;
168 int size4Aling = (size >> 2) << 2;
169 int notAlign = 0;
170 if (size % 16)
171 notAlign = 1;
172
173 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
174 printk("0x%08x: %08x %08x %08x %08x\r\n",
175 (u32) i,
176 *((u32 *) (i)),
177 *((u32 *) (i + 4)),
178 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
179 if (notAlign == 1)
180 printk("0x%08x: ", (u32) i);
181 for (; (u32) i < (u32) addr + size4Aling; i += 4)
182 printk("%08x ", *((u32 *) (i)));
183 for (; (u32) i < (u32) addr + size; i++)
184 printk("%02x", *((u8 *) (i)));
185 if (notAlign == 1)
186 printk("\r\n");
187 }
188 #endif /* DEBUG */
189
190 static struct list_head *dequeue(struct list_head *lh)
191 {
192 unsigned long flags;
193
194 spin_lock_irqsave(&ugeth_lock, flags);
195 if (!list_empty(lh)) {
196 struct list_head *node = lh->next;
197 list_del(node);
198 spin_unlock_irqrestore(&ugeth_lock, flags);
199 return node;
200 } else {
201 spin_unlock_irqrestore(&ugeth_lock, flags);
202 return NULL;
203 }
204 }
205
206 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
207 u8 __iomem *bd)
208 {
209 struct sk_buff *skb = NULL;
210
211 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
212 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
213
214 if (skb == NULL)
215 return NULL;
216
217 /* We need the data buffer to be aligned properly. We will reserve
218 * as many bytes as needed to align the data properly
219 */
220 skb_reserve(skb,
221 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
222 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
223 1)));
224
225 skb->dev = ugeth->ndev;
226
227 out_be32(&((struct qe_bd __iomem *)bd)->buf,
228 dma_map_single(ugeth->dev,
229 skb->data,
230 ugeth->ug_info->uf_info.max_rx_buf_length +
231 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
232 DMA_FROM_DEVICE));
233
234 out_be32((u32 __iomem *)bd,
235 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
236
237 return skb;
238 }
239
240 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
241 {
242 u8 __iomem *bd;
243 u32 bd_status;
244 struct sk_buff *skb;
245 int i;
246
247 bd = ugeth->p_rx_bd_ring[rxQ];
248 i = 0;
249
250 do {
251 bd_status = in_be32((u32 __iomem *)bd);
252 skb = get_new_skb(ugeth, bd);
253
254 if (!skb) /* If can not allocate data buffer,
255 abort. Cleanup will be elsewhere */
256 return -ENOMEM;
257
258 ugeth->rx_skbuff[rxQ][i] = skb;
259
260 /* advance the BD pointer */
261 bd += sizeof(struct qe_bd);
262 i++;
263 } while (!(bd_status & R_W));
264
265 return 0;
266 }
267
268 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
269 u32 *p_start,
270 u8 num_entries,
271 u32 thread_size,
272 u32 thread_alignment,
273 enum qe_risc_allocation risc,
274 int skip_page_for_first_entry)
275 {
276 u32 init_enet_offset;
277 u8 i;
278 int snum;
279
280 for (i = 0; i < num_entries; i++) {
281 if ((snum = qe_get_snum()) < 0) {
282 if (netif_msg_ifup(ugeth))
283 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
284 return snum;
285 }
286 if ((i == 0) && skip_page_for_first_entry)
287 /* First entry of Rx does not have page */
288 init_enet_offset = 0;
289 else {
290 init_enet_offset =
291 qe_muram_alloc(thread_size, thread_alignment);
292 if (IS_ERR_VALUE(init_enet_offset)) {
293 if (netif_msg_ifup(ugeth))
294 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
295 qe_put_snum((u8) snum);
296 return -ENOMEM;
297 }
298 }
299 *(p_start++) =
300 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
301 | risc;
302 }
303
304 return 0;
305 }
306
307 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
308 u32 *p_start,
309 u8 num_entries,
310 enum qe_risc_allocation risc,
311 int skip_page_for_first_entry)
312 {
313 u32 init_enet_offset;
314 u8 i;
315 int snum;
316
317 for (i = 0; i < num_entries; i++) {
318 u32 val = *p_start;
319
320 /* Check that this entry was actually valid --
321 needed in case failed in allocations */
322 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
323 snum =
324 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
325 ENET_INIT_PARAM_SNUM_SHIFT;
326 qe_put_snum((u8) snum);
327 if (!((i == 0) && skip_page_for_first_entry)) {
328 /* First entry of Rx does not have page */
329 init_enet_offset =
330 (val & ENET_INIT_PARAM_PTR_MASK);
331 qe_muram_free(init_enet_offset);
332 }
333 *p_start++ = 0;
334 }
335 }
336
337 return 0;
338 }
339
340 #ifdef DEBUG
341 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
342 u32 __iomem *p_start,
343 u8 num_entries,
344 u32 thread_size,
345 enum qe_risc_allocation risc,
346 int skip_page_for_first_entry)
347 {
348 u32 init_enet_offset;
349 u8 i;
350 int snum;
351
352 for (i = 0; i < num_entries; i++) {
353 u32 val = in_be32(p_start);
354
355 /* Check that this entry was actually valid --
356 needed in case failed in allocations */
357 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
358 snum =
359 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
360 ENET_INIT_PARAM_SNUM_SHIFT;
361 qe_put_snum((u8) snum);
362 if (!((i == 0) && skip_page_for_first_entry)) {
363 /* First entry of Rx does not have page */
364 init_enet_offset =
365 (in_be32(p_start) &
366 ENET_INIT_PARAM_PTR_MASK);
367 ugeth_info("Init enet entry %d:", i);
368 ugeth_info("Base address: 0x%08x",
369 (u32)
370 qe_muram_addr(init_enet_offset));
371 mem_disp(qe_muram_addr(init_enet_offset),
372 thread_size);
373 }
374 p_start++;
375 }
376 }
377
378 return 0;
379 }
380 #endif
381
382 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
383 {
384 kfree(enet_addr_cont);
385 }
386
387 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
388 {
389 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
390 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
391 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
392 }
393
394 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
395 {
396 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
397
398 if (!(paddr_num < NUM_OF_PADDRS)) {
399 ugeth_warn("%s: Illagel paddr_num.", __func__);
400 return -EINVAL;
401 }
402
403 p_82xx_addr_filt =
404 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
405 addressfiltering;
406
407 /* Writing address ff.ff.ff.ff.ff.ff disables address
408 recognition for this register */
409 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
412
413 return 0;
414 }
415
416 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
417 u8 *p_enet_addr)
418 {
419 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
420 u32 cecr_subblock;
421
422 p_82xx_addr_filt =
423 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
424 addressfiltering;
425
426 cecr_subblock =
427 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
428
429 /* Ethernet frames are defined in Little Endian mode,
430 therefor to insert */
431 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
432
433 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
434
435 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
436 QE_CR_PROTOCOL_ETHERNET, 0);
437 }
438
439 #ifdef CONFIG_UGETH_MAGIC_PACKET
440 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
441 {
442 struct ucc_fast_private *uccf;
443 struct ucc_geth __iomem *ug_regs;
444
445 uccf = ugeth->uccf;
446 ug_regs = ugeth->ug_regs;
447
448 /* Enable interrupts for magic packet detection */
449 setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
450
451 /* Enable magic packet detection */
452 setbits32(&ug_regs->maccfg2, MACCFG2_MPE);
453 }
454
455 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
456 {
457 struct ucc_fast_private *uccf;
458 struct ucc_geth __iomem *ug_regs;
459
460 uccf = ugeth->uccf;
461 ug_regs = ugeth->ug_regs;
462
463 /* Disable interrupts for magic packet detection */
464 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
465
466 /* Disable magic packet detection */
467 clrbits32(&ug_regs->maccfg2, MACCFG2_MPE);
468 }
469 #endif /* MAGIC_PACKET */
470
471 static inline int compare_addr(u8 **addr1, u8 **addr2)
472 {
473 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
474 }
475
476 #ifdef DEBUG
477 static void get_statistics(struct ucc_geth_private *ugeth,
478 struct ucc_geth_tx_firmware_statistics *
479 tx_firmware_statistics,
480 struct ucc_geth_rx_firmware_statistics *
481 rx_firmware_statistics,
482 struct ucc_geth_hardware_statistics *hardware_statistics)
483 {
484 struct ucc_fast __iomem *uf_regs;
485 struct ucc_geth __iomem *ug_regs;
486 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
487 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
488
489 ug_regs = ugeth->ug_regs;
490 uf_regs = (struct ucc_fast __iomem *) ug_regs;
491 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
492 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
493
494 /* Tx firmware only if user handed pointer and driver actually
495 gathers Tx firmware statistics */
496 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
497 tx_firmware_statistics->sicoltx =
498 in_be32(&p_tx_fw_statistics_pram->sicoltx);
499 tx_firmware_statistics->mulcoltx =
500 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
501 tx_firmware_statistics->latecoltxfr =
502 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
503 tx_firmware_statistics->frabortduecol =
504 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
505 tx_firmware_statistics->frlostinmactxer =
506 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
507 tx_firmware_statistics->carriersenseertx =
508 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
509 tx_firmware_statistics->frtxok =
510 in_be32(&p_tx_fw_statistics_pram->frtxok);
511 tx_firmware_statistics->txfrexcessivedefer =
512 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
513 tx_firmware_statistics->txpkts256 =
514 in_be32(&p_tx_fw_statistics_pram->txpkts256);
515 tx_firmware_statistics->txpkts512 =
516 in_be32(&p_tx_fw_statistics_pram->txpkts512);
517 tx_firmware_statistics->txpkts1024 =
518 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
519 tx_firmware_statistics->txpktsjumbo =
520 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
521 }
522
523 /* Rx firmware only if user handed pointer and driver actually
524 * gathers Rx firmware statistics */
525 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
526 int i;
527 rx_firmware_statistics->frrxfcser =
528 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
529 rx_firmware_statistics->fraligner =
530 in_be32(&p_rx_fw_statistics_pram->fraligner);
531 rx_firmware_statistics->inrangelenrxer =
532 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
533 rx_firmware_statistics->outrangelenrxer =
534 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
535 rx_firmware_statistics->frtoolong =
536 in_be32(&p_rx_fw_statistics_pram->frtoolong);
537 rx_firmware_statistics->runt =
538 in_be32(&p_rx_fw_statistics_pram->runt);
539 rx_firmware_statistics->verylongevent =
540 in_be32(&p_rx_fw_statistics_pram->verylongevent);
541 rx_firmware_statistics->symbolerror =
542 in_be32(&p_rx_fw_statistics_pram->symbolerror);
543 rx_firmware_statistics->dropbsy =
544 in_be32(&p_rx_fw_statistics_pram->dropbsy);
545 for (i = 0; i < 0x8; i++)
546 rx_firmware_statistics->res0[i] =
547 p_rx_fw_statistics_pram->res0[i];
548 rx_firmware_statistics->mismatchdrop =
549 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
550 rx_firmware_statistics->underpkts =
551 in_be32(&p_rx_fw_statistics_pram->underpkts);
552 rx_firmware_statistics->pkts256 =
553 in_be32(&p_rx_fw_statistics_pram->pkts256);
554 rx_firmware_statistics->pkts512 =
555 in_be32(&p_rx_fw_statistics_pram->pkts512);
556 rx_firmware_statistics->pkts1024 =
557 in_be32(&p_rx_fw_statistics_pram->pkts1024);
558 rx_firmware_statistics->pktsjumbo =
559 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
560 rx_firmware_statistics->frlossinmacer =
561 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
562 rx_firmware_statistics->pausefr =
563 in_be32(&p_rx_fw_statistics_pram->pausefr);
564 for (i = 0; i < 0x4; i++)
565 rx_firmware_statistics->res1[i] =
566 p_rx_fw_statistics_pram->res1[i];
567 rx_firmware_statistics->removevlan =
568 in_be32(&p_rx_fw_statistics_pram->removevlan);
569 rx_firmware_statistics->replacevlan =
570 in_be32(&p_rx_fw_statistics_pram->replacevlan);
571 rx_firmware_statistics->insertvlan =
572 in_be32(&p_rx_fw_statistics_pram->insertvlan);
573 }
574
575 /* Hardware only if user handed pointer and driver actually
576 gathers hardware statistics */
577 if (hardware_statistics &&
578 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
579 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
580 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
581 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
582 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
583 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
584 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
585 hardware_statistics->txok = in_be32(&ug_regs->txok);
586 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
587 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
588 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
589 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
590 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
591 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
592 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
593 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
594 }
595 }
596
597 static void dump_bds(struct ucc_geth_private *ugeth)
598 {
599 int i;
600 int length;
601
602 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
603 if (ugeth->p_tx_bd_ring[i]) {
604 length =
605 (ugeth->ug_info->bdRingLenTx[i] *
606 sizeof(struct qe_bd));
607 ugeth_info("TX BDs[%d]", i);
608 mem_disp(ugeth->p_tx_bd_ring[i], length);
609 }
610 }
611 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
612 if (ugeth->p_rx_bd_ring[i]) {
613 length =
614 (ugeth->ug_info->bdRingLenRx[i] *
615 sizeof(struct qe_bd));
616 ugeth_info("RX BDs[%d]", i);
617 mem_disp(ugeth->p_rx_bd_ring[i], length);
618 }
619 }
620 }
621
622 static void dump_regs(struct ucc_geth_private *ugeth)
623 {
624 int i;
625
626 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
627 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
628
629 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
630 (u32) & ugeth->ug_regs->maccfg1,
631 in_be32(&ugeth->ug_regs->maccfg1));
632 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
633 (u32) & ugeth->ug_regs->maccfg2,
634 in_be32(&ugeth->ug_regs->maccfg2));
635 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
636 (u32) & ugeth->ug_regs->ipgifg,
637 in_be32(&ugeth->ug_regs->ipgifg));
638 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
639 (u32) & ugeth->ug_regs->hafdup,
640 in_be32(&ugeth->ug_regs->hafdup));
641 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
642 (u32) & ugeth->ug_regs->ifctl,
643 in_be32(&ugeth->ug_regs->ifctl));
644 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
645 (u32) & ugeth->ug_regs->ifstat,
646 in_be32(&ugeth->ug_regs->ifstat));
647 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
648 (u32) & ugeth->ug_regs->macstnaddr1,
649 in_be32(&ugeth->ug_regs->macstnaddr1));
650 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
651 (u32) & ugeth->ug_regs->macstnaddr2,
652 in_be32(&ugeth->ug_regs->macstnaddr2));
653 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
654 (u32) & ugeth->ug_regs->uempr,
655 in_be32(&ugeth->ug_regs->uempr));
656 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
657 (u32) & ugeth->ug_regs->utbipar,
658 in_be32(&ugeth->ug_regs->utbipar));
659 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
660 (u32) & ugeth->ug_regs->uescr,
661 in_be16(&ugeth->ug_regs->uescr));
662 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
663 (u32) & ugeth->ug_regs->tx64,
664 in_be32(&ugeth->ug_regs->tx64));
665 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
666 (u32) & ugeth->ug_regs->tx127,
667 in_be32(&ugeth->ug_regs->tx127));
668 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
669 (u32) & ugeth->ug_regs->tx255,
670 in_be32(&ugeth->ug_regs->tx255));
671 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
672 (u32) & ugeth->ug_regs->rx64,
673 in_be32(&ugeth->ug_regs->rx64));
674 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
675 (u32) & ugeth->ug_regs->rx127,
676 in_be32(&ugeth->ug_regs->rx127));
677 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
678 (u32) & ugeth->ug_regs->rx255,
679 in_be32(&ugeth->ug_regs->rx255));
680 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
681 (u32) & ugeth->ug_regs->txok,
682 in_be32(&ugeth->ug_regs->txok));
683 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
684 (u32) & ugeth->ug_regs->txcf,
685 in_be16(&ugeth->ug_regs->txcf));
686 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
687 (u32) & ugeth->ug_regs->tmca,
688 in_be32(&ugeth->ug_regs->tmca));
689 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
690 (u32) & ugeth->ug_regs->tbca,
691 in_be32(&ugeth->ug_regs->tbca));
692 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
693 (u32) & ugeth->ug_regs->rxfok,
694 in_be32(&ugeth->ug_regs->rxfok));
695 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
696 (u32) & ugeth->ug_regs->rxbok,
697 in_be32(&ugeth->ug_regs->rxbok));
698 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
699 (u32) & ugeth->ug_regs->rbyt,
700 in_be32(&ugeth->ug_regs->rbyt));
701 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
702 (u32) & ugeth->ug_regs->rmca,
703 in_be32(&ugeth->ug_regs->rmca));
704 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
705 (u32) & ugeth->ug_regs->rbca,
706 in_be32(&ugeth->ug_regs->rbca));
707 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
708 (u32) & ugeth->ug_regs->scar,
709 in_be32(&ugeth->ug_regs->scar));
710 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
711 (u32) & ugeth->ug_regs->scam,
712 in_be32(&ugeth->ug_regs->scam));
713
714 if (ugeth->p_thread_data_tx) {
715 int numThreadsTxNumerical;
716 switch (ugeth->ug_info->numThreadsTx) {
717 case UCC_GETH_NUM_OF_THREADS_1:
718 numThreadsTxNumerical = 1;
719 break;
720 case UCC_GETH_NUM_OF_THREADS_2:
721 numThreadsTxNumerical = 2;
722 break;
723 case UCC_GETH_NUM_OF_THREADS_4:
724 numThreadsTxNumerical = 4;
725 break;
726 case UCC_GETH_NUM_OF_THREADS_6:
727 numThreadsTxNumerical = 6;
728 break;
729 case UCC_GETH_NUM_OF_THREADS_8:
730 numThreadsTxNumerical = 8;
731 break;
732 default:
733 numThreadsTxNumerical = 0;
734 break;
735 }
736
737 ugeth_info("Thread data TXs:");
738 ugeth_info("Base address: 0x%08x",
739 (u32) ugeth->p_thread_data_tx);
740 for (i = 0; i < numThreadsTxNumerical; i++) {
741 ugeth_info("Thread data TX[%d]:", i);
742 ugeth_info("Base address: 0x%08x",
743 (u32) & ugeth->p_thread_data_tx[i]);
744 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
745 sizeof(struct ucc_geth_thread_data_tx));
746 }
747 }
748 if (ugeth->p_thread_data_rx) {
749 int numThreadsRxNumerical;
750 switch (ugeth->ug_info->numThreadsRx) {
751 case UCC_GETH_NUM_OF_THREADS_1:
752 numThreadsRxNumerical = 1;
753 break;
754 case UCC_GETH_NUM_OF_THREADS_2:
755 numThreadsRxNumerical = 2;
756 break;
757 case UCC_GETH_NUM_OF_THREADS_4:
758 numThreadsRxNumerical = 4;
759 break;
760 case UCC_GETH_NUM_OF_THREADS_6:
761 numThreadsRxNumerical = 6;
762 break;
763 case UCC_GETH_NUM_OF_THREADS_8:
764 numThreadsRxNumerical = 8;
765 break;
766 default:
767 numThreadsRxNumerical = 0;
768 break;
769 }
770
771 ugeth_info("Thread data RX:");
772 ugeth_info("Base address: 0x%08x",
773 (u32) ugeth->p_thread_data_rx);
774 for (i = 0; i < numThreadsRxNumerical; i++) {
775 ugeth_info("Thread data RX[%d]:", i);
776 ugeth_info("Base address: 0x%08x",
777 (u32) & ugeth->p_thread_data_rx[i]);
778 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
779 sizeof(struct ucc_geth_thread_data_rx));
780 }
781 }
782 if (ugeth->p_exf_glbl_param) {
783 ugeth_info("EXF global param:");
784 ugeth_info("Base address: 0x%08x",
785 (u32) ugeth->p_exf_glbl_param);
786 mem_disp((u8 *) ugeth->p_exf_glbl_param,
787 sizeof(*ugeth->p_exf_glbl_param));
788 }
789 if (ugeth->p_tx_glbl_pram) {
790 ugeth_info("TX global param:");
791 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
792 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
793 (u32) & ugeth->p_tx_glbl_pram->temoder,
794 in_be16(&ugeth->p_tx_glbl_pram->temoder));
795 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
796 (u32) & ugeth->p_tx_glbl_pram->sqptr,
797 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
798 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
799 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
800 in_be32(&ugeth->p_tx_glbl_pram->
801 schedulerbasepointer));
802 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
803 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
804 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
805 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
806 (u32) & ugeth->p_tx_glbl_pram->tstate,
807 in_be32(&ugeth->p_tx_glbl_pram->tstate));
808 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
809 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
810 ugeth->p_tx_glbl_pram->iphoffset[0]);
811 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
812 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
813 ugeth->p_tx_glbl_pram->iphoffset[1]);
814 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
815 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
816 ugeth->p_tx_glbl_pram->iphoffset[2]);
817 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
818 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
819 ugeth->p_tx_glbl_pram->iphoffset[3]);
820 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
821 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
822 ugeth->p_tx_glbl_pram->iphoffset[4]);
823 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
824 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
825 ugeth->p_tx_glbl_pram->iphoffset[5]);
826 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
827 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
828 ugeth->p_tx_glbl_pram->iphoffset[6]);
829 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
830 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
831 ugeth->p_tx_glbl_pram->iphoffset[7]);
832 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
833 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
834 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
835 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
836 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
837 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
838 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
839 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
840 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
841 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
842 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
843 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
844 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
845 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
846 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
847 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
848 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
849 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
850 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
851 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
852 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
853 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
854 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
855 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
856 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
857 (u32) & ugeth->p_tx_glbl_pram->tqptr,
858 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
859 }
860 if (ugeth->p_rx_glbl_pram) {
861 ugeth_info("RX global param:");
862 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
863 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
864 (u32) & ugeth->p_rx_glbl_pram->remoder,
865 in_be32(&ugeth->p_rx_glbl_pram->remoder));
866 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
867 (u32) & ugeth->p_rx_glbl_pram->rqptr,
868 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
869 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
870 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
871 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
872 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
873 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
874 ugeth->p_rx_glbl_pram->rxgstpack);
875 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
876 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
877 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
878 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
879 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
880 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
881 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
882 (u32) & ugeth->p_rx_glbl_pram->rstate,
883 ugeth->p_rx_glbl_pram->rstate);
884 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
885 (u32) & ugeth->p_rx_glbl_pram->mrblr,
886 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
887 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
888 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
889 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
890 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
891 (u32) & ugeth->p_rx_glbl_pram->mflr,
892 in_be16(&ugeth->p_rx_glbl_pram->mflr));
893 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
894 (u32) & ugeth->p_rx_glbl_pram->minflr,
895 in_be16(&ugeth->p_rx_glbl_pram->minflr));
896 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
897 (u32) & ugeth->p_rx_glbl_pram->maxd1,
898 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
899 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
900 (u32) & ugeth->p_rx_glbl_pram->maxd2,
901 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
902 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
903 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
904 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
905 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
906 (u32) & ugeth->p_rx_glbl_pram->l2qt,
907 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
908 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
909 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
910 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
911 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
912 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
913 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
914 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
915 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
916 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
917 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
918 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
919 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
920 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
921 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
922 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
923 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
924 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
925 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
926 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
927 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
928 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
929 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
930 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
931 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
932 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
933 (u32) & ugeth->p_rx_glbl_pram->vlantype,
934 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
935 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
936 (u32) & ugeth->p_rx_glbl_pram->vlantci,
937 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
938 for (i = 0; i < 64; i++)
939 ugeth_info
940 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
941 i,
942 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
943 ugeth->p_rx_glbl_pram->addressfiltering[i]);
944 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
945 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
946 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
947 }
948 if (ugeth->p_send_q_mem_reg) {
949 ugeth_info("Send Q memory registers:");
950 ugeth_info("Base address: 0x%08x",
951 (u32) ugeth->p_send_q_mem_reg);
952 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
953 ugeth_info("SQQD[%d]:", i);
954 ugeth_info("Base address: 0x%08x",
955 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
956 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
957 sizeof(struct ucc_geth_send_queue_qd));
958 }
959 }
960 if (ugeth->p_scheduler) {
961 ugeth_info("Scheduler:");
962 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
963 mem_disp((u8 *) ugeth->p_scheduler,
964 sizeof(*ugeth->p_scheduler));
965 }
966 if (ugeth->p_tx_fw_statistics_pram) {
967 ugeth_info("TX FW statistics pram:");
968 ugeth_info("Base address: 0x%08x",
969 (u32) ugeth->p_tx_fw_statistics_pram);
970 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
971 sizeof(*ugeth->p_tx_fw_statistics_pram));
972 }
973 if (ugeth->p_rx_fw_statistics_pram) {
974 ugeth_info("RX FW statistics pram:");
975 ugeth_info("Base address: 0x%08x",
976 (u32) ugeth->p_rx_fw_statistics_pram);
977 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
978 sizeof(*ugeth->p_rx_fw_statistics_pram));
979 }
980 if (ugeth->p_rx_irq_coalescing_tbl) {
981 ugeth_info("RX IRQ coalescing tables:");
982 ugeth_info("Base address: 0x%08x",
983 (u32) ugeth->p_rx_irq_coalescing_tbl);
984 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
985 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
986 ugeth_info("Base address: 0x%08x",
987 (u32) & ugeth->p_rx_irq_coalescing_tbl->
988 coalescingentry[i]);
989 ugeth_info
990 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
991 (u32) & ugeth->p_rx_irq_coalescing_tbl->
992 coalescingentry[i].interruptcoalescingmaxvalue,
993 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
994 coalescingentry[i].
995 interruptcoalescingmaxvalue));
996 ugeth_info
997 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
998 (u32) & ugeth->p_rx_irq_coalescing_tbl->
999 coalescingentry[i].interruptcoalescingcounter,
1000 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1001 coalescingentry[i].
1002 interruptcoalescingcounter));
1003 }
1004 }
1005 if (ugeth->p_rx_bd_qs_tbl) {
1006 ugeth_info("RX BD QS tables:");
1007 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1008 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1009 ugeth_info("RX BD QS table[%d]:", i);
1010 ugeth_info("Base address: 0x%08x",
1011 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1012 ugeth_info
1013 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1014 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1015 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1016 ugeth_info
1017 ("bdptr : addr - 0x%08x, val - 0x%08x",
1018 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1019 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1020 ugeth_info
1021 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1022 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1023 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1024 externalbdbaseptr));
1025 ugeth_info
1026 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1027 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1028 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1029 ugeth_info("ucode RX Prefetched BDs:");
1030 ugeth_info("Base address: 0x%08x",
1031 (u32)
1032 qe_muram_addr(in_be32
1033 (&ugeth->p_rx_bd_qs_tbl[i].
1034 bdbaseptr)));
1035 mem_disp((u8 *)
1036 qe_muram_addr(in_be32
1037 (&ugeth->p_rx_bd_qs_tbl[i].
1038 bdbaseptr)),
1039 sizeof(struct ucc_geth_rx_prefetched_bds));
1040 }
1041 }
1042 if (ugeth->p_init_enet_param_shadow) {
1043 int size;
1044 ugeth_info("Init enet param shadow:");
1045 ugeth_info("Base address: 0x%08x",
1046 (u32) ugeth->p_init_enet_param_shadow);
1047 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1048 sizeof(*ugeth->p_init_enet_param_shadow));
1049
1050 size = sizeof(struct ucc_geth_thread_rx_pram);
1051 if (ugeth->ug_info->rxExtendedFiltering) {
1052 size +=
1053 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1054 if (ugeth->ug_info->largestexternallookupkeysize ==
1055 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1056 size +=
1057 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1058 if (ugeth->ug_info->largestexternallookupkeysize ==
1059 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1060 size +=
1061 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1062 }
1063
1064 dump_init_enet_entries(ugeth,
1065 &(ugeth->p_init_enet_param_shadow->
1066 txthread[0]),
1067 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1068 sizeof(struct ucc_geth_thread_tx_pram),
1069 ugeth->ug_info->riscTx, 0);
1070 dump_init_enet_entries(ugeth,
1071 &(ugeth->p_init_enet_param_shadow->
1072 rxthread[0]),
1073 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1074 ugeth->ug_info->riscRx, 1);
1075 }
1076 }
1077 #endif /* DEBUG */
1078
1079 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1080 u32 __iomem *maccfg1_register,
1081 u32 __iomem *maccfg2_register)
1082 {
1083 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1084 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1085 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1086 }
1087
1088 static int init_half_duplex_params(int alt_beb,
1089 int back_pressure_no_backoff,
1090 int no_backoff,
1091 int excess_defer,
1092 u8 alt_beb_truncation,
1093 u8 max_retransmissions,
1094 u8 collision_window,
1095 u32 __iomem *hafdup_register)
1096 {
1097 u32 value = 0;
1098
1099 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1100 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1101 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1102 return -EINVAL;
1103
1104 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1105
1106 if (alt_beb)
1107 value |= HALFDUP_ALT_BEB;
1108 if (back_pressure_no_backoff)
1109 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1110 if (no_backoff)
1111 value |= HALFDUP_NO_BACKOFF;
1112 if (excess_defer)
1113 value |= HALFDUP_EXCESSIVE_DEFER;
1114
1115 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1116
1117 value |= collision_window;
1118
1119 out_be32(hafdup_register, value);
1120 return 0;
1121 }
1122
1123 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1124 u8 non_btb_ipg,
1125 u8 min_ifg,
1126 u8 btb_ipg,
1127 u32 __iomem *ipgifg_register)
1128 {
1129 u32 value = 0;
1130
1131 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1132 IPG part 2 */
1133 if (non_btb_cs_ipg > non_btb_ipg)
1134 return -EINVAL;
1135
1136 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1137 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1138 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1139 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1140 return -EINVAL;
1141
1142 value |=
1143 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1144 IPGIFG_NBTB_CS_IPG_MASK);
1145 value |=
1146 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1147 IPGIFG_NBTB_IPG_MASK);
1148 value |=
1149 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1150 IPGIFG_MIN_IFG_MASK);
1151 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1152
1153 out_be32(ipgifg_register, value);
1154 return 0;
1155 }
1156
1157 int init_flow_control_params(u32 automatic_flow_control_mode,
1158 int rx_flow_control_enable,
1159 int tx_flow_control_enable,
1160 u16 pause_period,
1161 u16 extension_field,
1162 u32 __iomem *upsmr_register,
1163 u32 __iomem *uempr_register,
1164 u32 __iomem *maccfg1_register)
1165 {
1166 u32 value = 0;
1167
1168 /* Set UEMPR register */
1169 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1170 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1171 out_be32(uempr_register, value);
1172
1173 /* Set UPSMR register */
1174 setbits32(upsmr_register, automatic_flow_control_mode);
1175
1176 value = in_be32(maccfg1_register);
1177 if (rx_flow_control_enable)
1178 value |= MACCFG1_FLOW_RX;
1179 if (tx_flow_control_enable)
1180 value |= MACCFG1_FLOW_TX;
1181 out_be32(maccfg1_register, value);
1182
1183 return 0;
1184 }
1185
1186 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1187 int auto_zero_hardware_statistics,
1188 u32 __iomem *upsmr_register,
1189 u16 __iomem *uescr_register)
1190 {
1191 u16 uescr_value = 0;
1192
1193 /* Enable hardware statistics gathering if requested */
1194 if (enable_hardware_statistics)
1195 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1196
1197 /* Clear hardware statistics counters */
1198 uescr_value = in_be16(uescr_register);
1199 uescr_value |= UESCR_CLRCNT;
1200 /* Automatically zero hardware statistics counters on read,
1201 if requested */
1202 if (auto_zero_hardware_statistics)
1203 uescr_value |= UESCR_AUTOZ;
1204 out_be16(uescr_register, uescr_value);
1205
1206 return 0;
1207 }
1208
1209 static int init_firmware_statistics_gathering_mode(int
1210 enable_tx_firmware_statistics,
1211 int enable_rx_firmware_statistics,
1212 u32 __iomem *tx_rmon_base_ptr,
1213 u32 tx_firmware_statistics_structure_address,
1214 u32 __iomem *rx_rmon_base_ptr,
1215 u32 rx_firmware_statistics_structure_address,
1216 u16 __iomem *temoder_register,
1217 u32 __iomem *remoder_register)
1218 {
1219 /* Note: this function does not check if */
1220 /* the parameters it receives are NULL */
1221
1222 if (enable_tx_firmware_statistics) {
1223 out_be32(tx_rmon_base_ptr,
1224 tx_firmware_statistics_structure_address);
1225 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1226 }
1227
1228 if (enable_rx_firmware_statistics) {
1229 out_be32(rx_rmon_base_ptr,
1230 rx_firmware_statistics_structure_address);
1231 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int init_mac_station_addr_regs(u8 address_byte_0,
1238 u8 address_byte_1,
1239 u8 address_byte_2,
1240 u8 address_byte_3,
1241 u8 address_byte_4,
1242 u8 address_byte_5,
1243 u32 __iomem *macstnaddr1_register,
1244 u32 __iomem *macstnaddr2_register)
1245 {
1246 u32 value = 0;
1247
1248 /* Example: for a station address of 0x12345678ABCD, */
1249 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1250
1251 /* MACSTNADDR1 Register: */
1252
1253 /* 0 7 8 15 */
1254 /* station address byte 5 station address byte 4 */
1255 /* 16 23 24 31 */
1256 /* station address byte 3 station address byte 2 */
1257 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1258 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1259 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1260 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1261
1262 out_be32(macstnaddr1_register, value);
1263
1264 /* MACSTNADDR2 Register: */
1265
1266 /* 0 7 8 15 */
1267 /* station address byte 1 station address byte 0 */
1268 /* 16 23 24 31 */
1269 /* reserved reserved */
1270 value = 0;
1271 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1272 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1273
1274 out_be32(macstnaddr2_register, value);
1275
1276 return 0;
1277 }
1278
1279 static int init_check_frame_length_mode(int length_check,
1280 u32 __iomem *maccfg2_register)
1281 {
1282 u32 value = 0;
1283
1284 value = in_be32(maccfg2_register);
1285
1286 if (length_check)
1287 value |= MACCFG2_LC;
1288 else
1289 value &= ~MACCFG2_LC;
1290
1291 out_be32(maccfg2_register, value);
1292 return 0;
1293 }
1294
1295 static int init_preamble_length(u8 preamble_length,
1296 u32 __iomem *maccfg2_register)
1297 {
1298 if ((preamble_length < 3) || (preamble_length > 7))
1299 return -EINVAL;
1300
1301 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1302 preamble_length << MACCFG2_PREL_SHIFT);
1303
1304 return 0;
1305 }
1306
1307 static int init_rx_parameters(int reject_broadcast,
1308 int receive_short_frames,
1309 int promiscuous, u32 __iomem *upsmr_register)
1310 {
1311 u32 value = 0;
1312
1313 value = in_be32(upsmr_register);
1314
1315 if (reject_broadcast)
1316 value |= UCC_GETH_UPSMR_BRO;
1317 else
1318 value &= ~UCC_GETH_UPSMR_BRO;
1319
1320 if (receive_short_frames)
1321 value |= UCC_GETH_UPSMR_RSH;
1322 else
1323 value &= ~UCC_GETH_UPSMR_RSH;
1324
1325 if (promiscuous)
1326 value |= UCC_GETH_UPSMR_PRO;
1327 else
1328 value &= ~UCC_GETH_UPSMR_PRO;
1329
1330 out_be32(upsmr_register, value);
1331
1332 return 0;
1333 }
1334
1335 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1336 u16 __iomem *mrblr_register)
1337 {
1338 /* max_rx_buf_len value must be a multiple of 128 */
1339 if ((max_rx_buf_len == 0)
1340 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1341 return -EINVAL;
1342
1343 out_be16(mrblr_register, max_rx_buf_len);
1344 return 0;
1345 }
1346
1347 static int init_min_frame_len(u16 min_frame_length,
1348 u16 __iomem *minflr_register,
1349 u16 __iomem *mrblr_register)
1350 {
1351 u16 mrblr_value = 0;
1352
1353 mrblr_value = in_be16(mrblr_register);
1354 if (min_frame_length >= (mrblr_value - 4))
1355 return -EINVAL;
1356
1357 out_be16(minflr_register, min_frame_length);
1358 return 0;
1359 }
1360
1361 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1362 {
1363 struct ucc_geth_info *ug_info;
1364 struct ucc_geth __iomem *ug_regs;
1365 struct ucc_fast __iomem *uf_regs;
1366 int ret_val;
1367 u32 upsmr, maccfg2, tbiBaseAddress;
1368 u16 value;
1369
1370 ugeth_vdbg("%s: IN", __func__);
1371
1372 ug_info = ugeth->ug_info;
1373 ug_regs = ugeth->ug_regs;
1374 uf_regs = ugeth->uccf->uf_regs;
1375
1376 /* Set MACCFG2 */
1377 maccfg2 = in_be32(&ug_regs->maccfg2);
1378 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1379 if ((ugeth->max_speed == SPEED_10) ||
1380 (ugeth->max_speed == SPEED_100))
1381 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1382 else if (ugeth->max_speed == SPEED_1000)
1383 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1384 maccfg2 |= ug_info->padAndCrc;
1385 out_be32(&ug_regs->maccfg2, maccfg2);
1386
1387 /* Set UPSMR */
1388 upsmr = in_be32(&uf_regs->upsmr);
1389 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1390 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1391 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1392 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1393 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1394 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1395 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1396 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1397 upsmr |= UCC_GETH_UPSMR_RPM;
1398 switch (ugeth->max_speed) {
1399 case SPEED_10:
1400 upsmr |= UCC_GETH_UPSMR_R10M;
1401 /* FALLTHROUGH */
1402 case SPEED_100:
1403 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1404 upsmr |= UCC_GETH_UPSMR_RMM;
1405 }
1406 }
1407 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1408 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1409 upsmr |= UCC_GETH_UPSMR_TBIM;
1410 }
1411 out_be32(&uf_regs->upsmr, upsmr);
1412
1413 /* Disable autonegotiation in tbi mode, because by default it
1414 comes up in autonegotiation mode. */
1415 /* Note that this depends on proper setting in utbipar register. */
1416 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1417 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1418 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1419 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1420 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1421 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1422 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1423 value &= ~0x1000; /* Turn off autonegotiation */
1424 ugeth->phydev->bus->write(ugeth->phydev->bus,
1425 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1426 }
1427
1428 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1429
1430 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1431 if (ret_val != 0) {
1432 if (netif_msg_probe(ugeth))
1433 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1434 __func__);
1435 return ret_val;
1436 }
1437
1438 return 0;
1439 }
1440
1441 /* Called every time the controller might need to be made
1442 * aware of new link state. The PHY code conveys this
1443 * information through variables in the ugeth structure, and this
1444 * function converts those variables into the appropriate
1445 * register values, and can bring down the device if needed.
1446 */
1447
1448 static void adjust_link(struct net_device *dev)
1449 {
1450 struct ucc_geth_private *ugeth = netdev_priv(dev);
1451 struct ucc_geth __iomem *ug_regs;
1452 struct ucc_fast __iomem *uf_regs;
1453 struct phy_device *phydev = ugeth->phydev;
1454 unsigned long flags;
1455 int new_state = 0;
1456
1457 ug_regs = ugeth->ug_regs;
1458 uf_regs = ugeth->uccf->uf_regs;
1459
1460 spin_lock_irqsave(&ugeth->lock, flags);
1461
1462 if (phydev->link) {
1463 u32 tempval = in_be32(&ug_regs->maccfg2);
1464 u32 upsmr = in_be32(&uf_regs->upsmr);
1465 /* Now we make sure that we can be in full duplex mode.
1466 * If not, we operate in half-duplex mode. */
1467 if (phydev->duplex != ugeth->oldduplex) {
1468 new_state = 1;
1469 if (!(phydev->duplex))
1470 tempval &= ~(MACCFG2_FDX);
1471 else
1472 tempval |= MACCFG2_FDX;
1473 ugeth->oldduplex = phydev->duplex;
1474 }
1475
1476 if (phydev->speed != ugeth->oldspeed) {
1477 new_state = 1;
1478 switch (phydev->speed) {
1479 case SPEED_1000:
1480 tempval = ((tempval &
1481 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1482 MACCFG2_INTERFACE_MODE_BYTE);
1483 break;
1484 case SPEED_100:
1485 case SPEED_10:
1486 tempval = ((tempval &
1487 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1488 MACCFG2_INTERFACE_MODE_NIBBLE);
1489 /* if reduced mode, re-set UPSMR.R10M */
1490 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1491 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1492 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1493 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1494 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1495 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1496 if (phydev->speed == SPEED_10)
1497 upsmr |= UCC_GETH_UPSMR_R10M;
1498 else
1499 upsmr &= ~UCC_GETH_UPSMR_R10M;
1500 }
1501 break;
1502 default:
1503 if (netif_msg_link(ugeth))
1504 ugeth_warn(
1505 "%s: Ack! Speed (%d) is not 10/100/1000!",
1506 dev->name, phydev->speed);
1507 break;
1508 }
1509 ugeth->oldspeed = phydev->speed;
1510 }
1511
1512 out_be32(&ug_regs->maccfg2, tempval);
1513 out_be32(&uf_regs->upsmr, upsmr);
1514
1515 if (!ugeth->oldlink) {
1516 new_state = 1;
1517 ugeth->oldlink = 1;
1518 }
1519 } else if (ugeth->oldlink) {
1520 new_state = 1;
1521 ugeth->oldlink = 0;
1522 ugeth->oldspeed = 0;
1523 ugeth->oldduplex = -1;
1524 }
1525
1526 if (new_state && netif_msg_link(ugeth))
1527 phy_print_status(phydev);
1528
1529 spin_unlock_irqrestore(&ugeth->lock, flags);
1530 }
1531
1532 /* Configure the PHY for dev.
1533 * returns 0 if success. -1 if failure
1534 */
1535 static int init_phy(struct net_device *dev)
1536 {
1537 struct ucc_geth_private *priv = netdev_priv(dev);
1538 struct ucc_geth_info *ug_info = priv->ug_info;
1539 struct phy_device *phydev;
1540
1541 priv->oldlink = 0;
1542 priv->oldspeed = 0;
1543 priv->oldduplex = -1;
1544
1545 phydev = phy_connect(dev, ug_info->phy_bus_id, &adjust_link, 0,
1546 priv->phy_interface);
1547
1548 if (IS_ERR(phydev)) {
1549 printk("%s: Could not attach to PHY\n", dev->name);
1550 return PTR_ERR(phydev);
1551 }
1552
1553 phydev->supported &= (ADVERTISED_10baseT_Half |
1554 ADVERTISED_10baseT_Full |
1555 ADVERTISED_100baseT_Half |
1556 ADVERTISED_100baseT_Full);
1557
1558 if (priv->max_speed == SPEED_1000)
1559 phydev->supported |= ADVERTISED_1000baseT_Full;
1560
1561 phydev->advertising = phydev->supported;
1562
1563 priv->phydev = phydev;
1564
1565 return 0;
1566 }
1567
1568
1569
1570 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1571 {
1572 struct ucc_fast_private *uccf;
1573 u32 cecr_subblock;
1574 u32 temp;
1575 int i = 10;
1576
1577 uccf = ugeth->uccf;
1578
1579 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1580 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1581 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1582
1583 /* Issue host command */
1584 cecr_subblock =
1585 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1586 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1587 QE_CR_PROTOCOL_ETHERNET, 0);
1588
1589 /* Wait for command to complete */
1590 do {
1591 msleep(10);
1592 temp = in_be32(uccf->p_ucce);
1593 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1594
1595 uccf->stopped_tx = 1;
1596
1597 return 0;
1598 }
1599
1600 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1601 {
1602 struct ucc_fast_private *uccf;
1603 u32 cecr_subblock;
1604 u8 temp;
1605 int i = 10;
1606
1607 uccf = ugeth->uccf;
1608
1609 /* Clear acknowledge bit */
1610 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1611 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1612 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1613
1614 /* Keep issuing command and checking acknowledge bit until
1615 it is asserted, according to spec */
1616 do {
1617 /* Issue host command */
1618 cecr_subblock =
1619 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1620 ucc_num);
1621 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1622 QE_CR_PROTOCOL_ETHERNET, 0);
1623 msleep(10);
1624 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1625 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1626
1627 uccf->stopped_rx = 1;
1628
1629 return 0;
1630 }
1631
1632 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1633 {
1634 struct ucc_fast_private *uccf;
1635 u32 cecr_subblock;
1636
1637 uccf = ugeth->uccf;
1638
1639 cecr_subblock =
1640 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1641 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1642 uccf->stopped_tx = 0;
1643
1644 return 0;
1645 }
1646
1647 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1648 {
1649 struct ucc_fast_private *uccf;
1650 u32 cecr_subblock;
1651
1652 uccf = ugeth->uccf;
1653
1654 cecr_subblock =
1655 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1656 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1657 0);
1658 uccf->stopped_rx = 0;
1659
1660 return 0;
1661 }
1662
1663 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1664 {
1665 struct ucc_fast_private *uccf;
1666 int enabled_tx, enabled_rx;
1667
1668 uccf = ugeth->uccf;
1669
1670 /* check if the UCC number is in range. */
1671 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1672 if (netif_msg_probe(ugeth))
1673 ugeth_err("%s: ucc_num out of range.", __func__);
1674 return -EINVAL;
1675 }
1676
1677 enabled_tx = uccf->enabled_tx;
1678 enabled_rx = uccf->enabled_rx;
1679
1680 /* Get Tx and Rx going again, in case this channel was actively
1681 disabled. */
1682 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1683 ugeth_restart_tx(ugeth);
1684 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1685 ugeth_restart_rx(ugeth);
1686
1687 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1688
1689 return 0;
1690
1691 }
1692
1693 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1694 {
1695 struct ucc_fast_private *uccf;
1696
1697 uccf = ugeth->uccf;
1698
1699 /* check if the UCC number is in range. */
1700 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1701 if (netif_msg_probe(ugeth))
1702 ugeth_err("%s: ucc_num out of range.", __func__);
1703 return -EINVAL;
1704 }
1705
1706 /* Stop any transmissions */
1707 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1708 ugeth_graceful_stop_tx(ugeth);
1709
1710 /* Stop any receptions */
1711 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1712 ugeth_graceful_stop_rx(ugeth);
1713
1714 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1715
1716 return 0;
1717 }
1718
1719 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1720 {
1721 #ifdef DEBUG
1722 ucc_fast_dump_regs(ugeth->uccf);
1723 dump_regs(ugeth);
1724 dump_bds(ugeth);
1725 #endif
1726 }
1727
1728 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1729 ugeth,
1730 enum enet_addr_type
1731 enet_addr_type)
1732 {
1733 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1734 struct ucc_fast_private *uccf;
1735 enum comm_dir comm_dir;
1736 struct list_head *p_lh;
1737 u16 i, num;
1738 u32 __iomem *addr_h;
1739 u32 __iomem *addr_l;
1740 u8 *p_counter;
1741
1742 uccf = ugeth->uccf;
1743
1744 p_82xx_addr_filt =
1745 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1746 ugeth->p_rx_glbl_pram->addressfiltering;
1747
1748 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1749 addr_h = &(p_82xx_addr_filt->gaddr_h);
1750 addr_l = &(p_82xx_addr_filt->gaddr_l);
1751 p_lh = &ugeth->group_hash_q;
1752 p_counter = &(ugeth->numGroupAddrInHash);
1753 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1754 addr_h = &(p_82xx_addr_filt->iaddr_h);
1755 addr_l = &(p_82xx_addr_filt->iaddr_l);
1756 p_lh = &ugeth->ind_hash_q;
1757 p_counter = &(ugeth->numIndAddrInHash);
1758 } else
1759 return -EINVAL;
1760
1761 comm_dir = 0;
1762 if (uccf->enabled_tx)
1763 comm_dir |= COMM_DIR_TX;
1764 if (uccf->enabled_rx)
1765 comm_dir |= COMM_DIR_RX;
1766 if (comm_dir)
1767 ugeth_disable(ugeth, comm_dir);
1768
1769 /* Clear the hash table. */
1770 out_be32(addr_h, 0x00000000);
1771 out_be32(addr_l, 0x00000000);
1772
1773 if (!p_lh)
1774 return 0;
1775
1776 num = *p_counter;
1777
1778 /* Delete all remaining CQ elements */
1779 for (i = 0; i < num; i++)
1780 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1781
1782 *p_counter = 0;
1783
1784 if (comm_dir)
1785 ugeth_enable(ugeth, comm_dir);
1786
1787 return 0;
1788 }
1789
1790 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1791 u8 paddr_num)
1792 {
1793 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1794 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1795 }
1796
1797 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1798 {
1799 u16 i, j;
1800 u8 __iomem *bd;
1801
1802 if (!ugeth)
1803 return;
1804
1805 if (ugeth->uccf) {
1806 ucc_fast_free(ugeth->uccf);
1807 ugeth->uccf = NULL;
1808 }
1809
1810 if (ugeth->p_thread_data_tx) {
1811 qe_muram_free(ugeth->thread_dat_tx_offset);
1812 ugeth->p_thread_data_tx = NULL;
1813 }
1814 if (ugeth->p_thread_data_rx) {
1815 qe_muram_free(ugeth->thread_dat_rx_offset);
1816 ugeth->p_thread_data_rx = NULL;
1817 }
1818 if (ugeth->p_exf_glbl_param) {
1819 qe_muram_free(ugeth->exf_glbl_param_offset);
1820 ugeth->p_exf_glbl_param = NULL;
1821 }
1822 if (ugeth->p_rx_glbl_pram) {
1823 qe_muram_free(ugeth->rx_glbl_pram_offset);
1824 ugeth->p_rx_glbl_pram = NULL;
1825 }
1826 if (ugeth->p_tx_glbl_pram) {
1827 qe_muram_free(ugeth->tx_glbl_pram_offset);
1828 ugeth->p_tx_glbl_pram = NULL;
1829 }
1830 if (ugeth->p_send_q_mem_reg) {
1831 qe_muram_free(ugeth->send_q_mem_reg_offset);
1832 ugeth->p_send_q_mem_reg = NULL;
1833 }
1834 if (ugeth->p_scheduler) {
1835 qe_muram_free(ugeth->scheduler_offset);
1836 ugeth->p_scheduler = NULL;
1837 }
1838 if (ugeth->p_tx_fw_statistics_pram) {
1839 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1840 ugeth->p_tx_fw_statistics_pram = NULL;
1841 }
1842 if (ugeth->p_rx_fw_statistics_pram) {
1843 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1844 ugeth->p_rx_fw_statistics_pram = NULL;
1845 }
1846 if (ugeth->p_rx_irq_coalescing_tbl) {
1847 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1848 ugeth->p_rx_irq_coalescing_tbl = NULL;
1849 }
1850 if (ugeth->p_rx_bd_qs_tbl) {
1851 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1852 ugeth->p_rx_bd_qs_tbl = NULL;
1853 }
1854 if (ugeth->p_init_enet_param_shadow) {
1855 return_init_enet_entries(ugeth,
1856 &(ugeth->p_init_enet_param_shadow->
1857 rxthread[0]),
1858 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1859 ugeth->ug_info->riscRx, 1);
1860 return_init_enet_entries(ugeth,
1861 &(ugeth->p_init_enet_param_shadow->
1862 txthread[0]),
1863 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1864 ugeth->ug_info->riscTx, 0);
1865 kfree(ugeth->p_init_enet_param_shadow);
1866 ugeth->p_init_enet_param_shadow = NULL;
1867 }
1868 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1869 bd = ugeth->p_tx_bd_ring[i];
1870 if (!bd)
1871 continue;
1872 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1873 if (ugeth->tx_skbuff[i][j]) {
1874 dma_unmap_single(ugeth->dev,
1875 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1876 (in_be32((u32 __iomem *)bd) &
1877 BD_LENGTH_MASK),
1878 DMA_TO_DEVICE);
1879 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1880 ugeth->tx_skbuff[i][j] = NULL;
1881 }
1882 }
1883
1884 kfree(ugeth->tx_skbuff[i]);
1885
1886 if (ugeth->p_tx_bd_ring[i]) {
1887 if (ugeth->ug_info->uf_info.bd_mem_part ==
1888 MEM_PART_SYSTEM)
1889 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1890 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1891 MEM_PART_MURAM)
1892 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1893 ugeth->p_tx_bd_ring[i] = NULL;
1894 }
1895 }
1896 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1897 if (ugeth->p_rx_bd_ring[i]) {
1898 /* Return existing data buffers in ring */
1899 bd = ugeth->p_rx_bd_ring[i];
1900 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1901 if (ugeth->rx_skbuff[i][j]) {
1902 dma_unmap_single(ugeth->dev,
1903 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1904 ugeth->ug_info->
1905 uf_info.max_rx_buf_length +
1906 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1907 DMA_FROM_DEVICE);
1908 dev_kfree_skb_any(
1909 ugeth->rx_skbuff[i][j]);
1910 ugeth->rx_skbuff[i][j] = NULL;
1911 }
1912 bd += sizeof(struct qe_bd);
1913 }
1914
1915 kfree(ugeth->rx_skbuff[i]);
1916
1917 if (ugeth->ug_info->uf_info.bd_mem_part ==
1918 MEM_PART_SYSTEM)
1919 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1920 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1921 MEM_PART_MURAM)
1922 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1923 ugeth->p_rx_bd_ring[i] = NULL;
1924 }
1925 }
1926 while (!list_empty(&ugeth->group_hash_q))
1927 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1928 (dequeue(&ugeth->group_hash_q)));
1929 while (!list_empty(&ugeth->ind_hash_q))
1930 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1931 (dequeue(&ugeth->ind_hash_q)));
1932 if (ugeth->ug_regs) {
1933 iounmap(ugeth->ug_regs);
1934 ugeth->ug_regs = NULL;
1935 }
1936 }
1937
1938 static void ucc_geth_set_multi(struct net_device *dev)
1939 {
1940 struct ucc_geth_private *ugeth;
1941 struct dev_mc_list *dmi;
1942 struct ucc_fast __iomem *uf_regs;
1943 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1944 int i;
1945
1946 ugeth = netdev_priv(dev);
1947
1948 uf_regs = ugeth->uccf->uf_regs;
1949
1950 if (dev->flags & IFF_PROMISC) {
1951 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1952 } else {
1953 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1954
1955 p_82xx_addr_filt =
1956 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
1957 p_rx_glbl_pram->addressfiltering;
1958
1959 if (dev->flags & IFF_ALLMULTI) {
1960 /* Catch all multicast addresses, so set the
1961 * filter to all 1's.
1962 */
1963 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
1964 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
1965 } else {
1966 /* Clear filter and add the addresses in the list.
1967 */
1968 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
1969 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
1970
1971 dmi = dev->mc_list;
1972
1973 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
1974
1975 /* Only support group multicast for now.
1976 */
1977 if (!(dmi->dmi_addr[0] & 1))
1978 continue;
1979
1980 /* Ask CPM to run CRC and set bit in
1981 * filter mask.
1982 */
1983 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
1984 }
1985 }
1986 }
1987 }
1988
1989 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
1990 {
1991 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
1992 struct phy_device *phydev = ugeth->phydev;
1993
1994 ugeth_vdbg("%s: IN", __func__);
1995
1996 /* Disable the controller */
1997 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1998
1999 /* Tell the kernel the link is down */
2000 phy_stop(phydev);
2001
2002 /* Mask all interrupts */
2003 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2004
2005 /* Clear all interrupts */
2006 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2007
2008 /* Disable Rx and Tx */
2009 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2010
2011 phy_disconnect(ugeth->phydev);
2012 ugeth->phydev = NULL;
2013
2014 ucc_geth_memclean(ugeth);
2015 }
2016
2017 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2018 {
2019 struct ucc_geth_info *ug_info;
2020 struct ucc_fast_info *uf_info;
2021 int i;
2022
2023 ug_info = ugeth->ug_info;
2024 uf_info = &ug_info->uf_info;
2025
2026 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2027 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2028 if (netif_msg_probe(ugeth))
2029 ugeth_err("%s: Bad memory partition value.",
2030 __func__);
2031 return -EINVAL;
2032 }
2033
2034 /* Rx BD lengths */
2035 for (i = 0; i < ug_info->numQueuesRx; i++) {
2036 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2037 (ug_info->bdRingLenRx[i] %
2038 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2039 if (netif_msg_probe(ugeth))
2040 ugeth_err
2041 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2042 __func__);
2043 return -EINVAL;
2044 }
2045 }
2046
2047 /* Tx BD lengths */
2048 for (i = 0; i < ug_info->numQueuesTx; i++) {
2049 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2050 if (netif_msg_probe(ugeth))
2051 ugeth_err
2052 ("%s: Tx BD ring length must be no smaller than 2.",
2053 __func__);
2054 return -EINVAL;
2055 }
2056 }
2057
2058 /* mrblr */
2059 if ((uf_info->max_rx_buf_length == 0) ||
2060 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2061 if (netif_msg_probe(ugeth))
2062 ugeth_err
2063 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2064 __func__);
2065 return -EINVAL;
2066 }
2067
2068 /* num Tx queues */
2069 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2070 if (netif_msg_probe(ugeth))
2071 ugeth_err("%s: number of tx queues too large.", __func__);
2072 return -EINVAL;
2073 }
2074
2075 /* num Rx queues */
2076 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2077 if (netif_msg_probe(ugeth))
2078 ugeth_err("%s: number of rx queues too large.", __func__);
2079 return -EINVAL;
2080 }
2081
2082 /* l2qt */
2083 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2084 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2085 if (netif_msg_probe(ugeth))
2086 ugeth_err
2087 ("%s: VLAN priority table entry must not be"
2088 " larger than number of Rx queues.",
2089 __func__);
2090 return -EINVAL;
2091 }
2092 }
2093
2094 /* l3qt */
2095 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2096 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2097 if (netif_msg_probe(ugeth))
2098 ugeth_err
2099 ("%s: IP priority table entry must not be"
2100 " larger than number of Rx queues.",
2101 __func__);
2102 return -EINVAL;
2103 }
2104 }
2105
2106 if (ug_info->cam && !ug_info->ecamptr) {
2107 if (netif_msg_probe(ugeth))
2108 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2109 __func__);
2110 return -EINVAL;
2111 }
2112
2113 if ((ug_info->numStationAddresses !=
2114 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2115 && ug_info->rxExtendedFiltering) {
2116 if (netif_msg_probe(ugeth))
2117 ugeth_err("%s: Number of station addresses greater than 1 "
2118 "not allowed in extended parsing mode.",
2119 __func__);
2120 return -EINVAL;
2121 }
2122
2123 /* Generate uccm_mask for receive */
2124 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2125 for (i = 0; i < ug_info->numQueuesRx; i++)
2126 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2127
2128 for (i = 0; i < ug_info->numQueuesTx; i++)
2129 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2130 /* Initialize the general fast UCC block. */
2131 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2132 if (netif_msg_probe(ugeth))
2133 ugeth_err("%s: Failed to init uccf.", __func__);
2134 return -ENOMEM;
2135 }
2136
2137 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2138 if (!ugeth->ug_regs) {
2139 if (netif_msg_probe(ugeth))
2140 ugeth_err("%s: Failed to ioremap regs.", __func__);
2141 return -ENOMEM;
2142 }
2143
2144 return 0;
2145 }
2146
2147 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2148 {
2149 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2150 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2151 struct ucc_fast_private *uccf;
2152 struct ucc_geth_info *ug_info;
2153 struct ucc_fast_info *uf_info;
2154 struct ucc_fast __iomem *uf_regs;
2155 struct ucc_geth __iomem *ug_regs;
2156 int ret_val = -EINVAL;
2157 u32 remoder = UCC_GETH_REMODER_INIT;
2158 u32 init_enet_pram_offset, cecr_subblock, command;
2159 u32 ifstat, i, j, size, l2qt, l3qt, length;
2160 u16 temoder = UCC_GETH_TEMODER_INIT;
2161 u16 test;
2162 u8 function_code = 0;
2163 u8 __iomem *bd;
2164 u8 __iomem *endOfRing;
2165 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2166
2167 ugeth_vdbg("%s: IN", __func__);
2168 uccf = ugeth->uccf;
2169 ug_info = ugeth->ug_info;
2170 uf_info = &ug_info->uf_info;
2171 uf_regs = uccf->uf_regs;
2172 ug_regs = ugeth->ug_regs;
2173
2174 switch (ug_info->numThreadsRx) {
2175 case UCC_GETH_NUM_OF_THREADS_1:
2176 numThreadsRxNumerical = 1;
2177 break;
2178 case UCC_GETH_NUM_OF_THREADS_2:
2179 numThreadsRxNumerical = 2;
2180 break;
2181 case UCC_GETH_NUM_OF_THREADS_4:
2182 numThreadsRxNumerical = 4;
2183 break;
2184 case UCC_GETH_NUM_OF_THREADS_6:
2185 numThreadsRxNumerical = 6;
2186 break;
2187 case UCC_GETH_NUM_OF_THREADS_8:
2188 numThreadsRxNumerical = 8;
2189 break;
2190 default:
2191 if (netif_msg_ifup(ugeth))
2192 ugeth_err("%s: Bad number of Rx threads value.",
2193 __func__);
2194 return -EINVAL;
2195 break;
2196 }
2197
2198 switch (ug_info->numThreadsTx) {
2199 case UCC_GETH_NUM_OF_THREADS_1:
2200 numThreadsTxNumerical = 1;
2201 break;
2202 case UCC_GETH_NUM_OF_THREADS_2:
2203 numThreadsTxNumerical = 2;
2204 break;
2205 case UCC_GETH_NUM_OF_THREADS_4:
2206 numThreadsTxNumerical = 4;
2207 break;
2208 case UCC_GETH_NUM_OF_THREADS_6:
2209 numThreadsTxNumerical = 6;
2210 break;
2211 case UCC_GETH_NUM_OF_THREADS_8:
2212 numThreadsTxNumerical = 8;
2213 break;
2214 default:
2215 if (netif_msg_ifup(ugeth))
2216 ugeth_err("%s: Bad number of Tx threads value.",
2217 __func__);
2218 return -EINVAL;
2219 break;
2220 }
2221
2222 /* Calculate rx_extended_features */
2223 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2224 ug_info->ipAddressAlignment ||
2225 (ug_info->numStationAddresses !=
2226 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2227
2228 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2229 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2230 || (ug_info->vlanOperationNonTagged !=
2231 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2232
2233 init_default_reg_vals(&uf_regs->upsmr,
2234 &ug_regs->maccfg1, &ug_regs->maccfg2);
2235
2236 /* Set UPSMR */
2237 /* For more details see the hardware spec. */
2238 init_rx_parameters(ug_info->bro,
2239 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2240
2241 /* We're going to ignore other registers for now, */
2242 /* except as needed to get up and running */
2243
2244 /* Set MACCFG1 */
2245 /* For more details see the hardware spec. */
2246 init_flow_control_params(ug_info->aufc,
2247 ug_info->receiveFlowControl,
2248 ug_info->transmitFlowControl,
2249 ug_info->pausePeriod,
2250 ug_info->extensionField,
2251 &uf_regs->upsmr,
2252 &ug_regs->uempr, &ug_regs->maccfg1);
2253
2254 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2255
2256 /* Set IPGIFG */
2257 /* For more details see the hardware spec. */
2258 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2259 ug_info->nonBackToBackIfgPart2,
2260 ug_info->
2261 miminumInterFrameGapEnforcement,
2262 ug_info->backToBackInterFrameGap,
2263 &ug_regs->ipgifg);
2264 if (ret_val != 0) {
2265 if (netif_msg_ifup(ugeth))
2266 ugeth_err("%s: IPGIFG initialization parameter too large.",
2267 __func__);
2268 return ret_val;
2269 }
2270
2271 /* Set HAFDUP */
2272 /* For more details see the hardware spec. */
2273 ret_val = init_half_duplex_params(ug_info->altBeb,
2274 ug_info->backPressureNoBackoff,
2275 ug_info->noBackoff,
2276 ug_info->excessDefer,
2277 ug_info->altBebTruncation,
2278 ug_info->maxRetransmission,
2279 ug_info->collisionWindow,
2280 &ug_regs->hafdup);
2281 if (ret_val != 0) {
2282 if (netif_msg_ifup(ugeth))
2283 ugeth_err("%s: Half Duplex initialization parameter too large.",
2284 __func__);
2285 return ret_val;
2286 }
2287
2288 /* Set IFSTAT */
2289 /* For more details see the hardware spec. */
2290 /* Read only - resets upon read */
2291 ifstat = in_be32(&ug_regs->ifstat);
2292
2293 /* Clear UEMPR */
2294 /* For more details see the hardware spec. */
2295 out_be32(&ug_regs->uempr, 0);
2296
2297 /* Set UESCR */
2298 /* For more details see the hardware spec. */
2299 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2300 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2301 0, &uf_regs->upsmr, &ug_regs->uescr);
2302
2303 /* Allocate Tx bds */
2304 for (j = 0; j < ug_info->numQueuesTx; j++) {
2305 /* Allocate in multiple of
2306 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2307 according to spec */
2308 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2309 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2310 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2311 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2312 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2313 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2314 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2315 u32 align = 4;
2316 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2317 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2318 ugeth->tx_bd_ring_offset[j] =
2319 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2320
2321 if (ugeth->tx_bd_ring_offset[j] != 0)
2322 ugeth->p_tx_bd_ring[j] =
2323 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2324 align) & ~(align - 1));
2325 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2326 ugeth->tx_bd_ring_offset[j] =
2327 qe_muram_alloc(length,
2328 UCC_GETH_TX_BD_RING_ALIGNMENT);
2329 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2330 ugeth->p_tx_bd_ring[j] =
2331 (u8 __iomem *) qe_muram_addr(ugeth->
2332 tx_bd_ring_offset[j]);
2333 }
2334 if (!ugeth->p_tx_bd_ring[j]) {
2335 if (netif_msg_ifup(ugeth))
2336 ugeth_err
2337 ("%s: Can not allocate memory for Tx bd rings.",
2338 __func__);
2339 return -ENOMEM;
2340 }
2341 /* Zero unused end of bd ring, according to spec */
2342 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2343 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2344 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2345 }
2346
2347 /* Allocate Rx bds */
2348 for (j = 0; j < ug_info->numQueuesRx; j++) {
2349 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2350 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2351 u32 align = 4;
2352 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2353 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2354 ugeth->rx_bd_ring_offset[j] =
2355 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2356 if (ugeth->rx_bd_ring_offset[j] != 0)
2357 ugeth->p_rx_bd_ring[j] =
2358 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2359 align) & ~(align - 1));
2360 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2361 ugeth->rx_bd_ring_offset[j] =
2362 qe_muram_alloc(length,
2363 UCC_GETH_RX_BD_RING_ALIGNMENT);
2364 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2365 ugeth->p_rx_bd_ring[j] =
2366 (u8 __iomem *) qe_muram_addr(ugeth->
2367 rx_bd_ring_offset[j]);
2368 }
2369 if (!ugeth->p_rx_bd_ring[j]) {
2370 if (netif_msg_ifup(ugeth))
2371 ugeth_err
2372 ("%s: Can not allocate memory for Rx bd rings.",
2373 __func__);
2374 return -ENOMEM;
2375 }
2376 }
2377
2378 /* Init Tx bds */
2379 for (j = 0; j < ug_info->numQueuesTx; j++) {
2380 /* Setup the skbuff rings */
2381 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2382 ugeth->ug_info->bdRingLenTx[j],
2383 GFP_KERNEL);
2384
2385 if (ugeth->tx_skbuff[j] == NULL) {
2386 if (netif_msg_ifup(ugeth))
2387 ugeth_err("%s: Could not allocate tx_skbuff",
2388 __func__);
2389 return -ENOMEM;
2390 }
2391
2392 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2393 ugeth->tx_skbuff[j][i] = NULL;
2394
2395 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2396 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2397 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2398 /* clear bd buffer */
2399 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2400 /* set bd status and length */
2401 out_be32((u32 __iomem *)bd, 0);
2402 bd += sizeof(struct qe_bd);
2403 }
2404 bd -= sizeof(struct qe_bd);
2405 /* set bd status and length */
2406 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2407 }
2408
2409 /* Init Rx bds */
2410 for (j = 0; j < ug_info->numQueuesRx; j++) {
2411 /* Setup the skbuff rings */
2412 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2413 ugeth->ug_info->bdRingLenRx[j],
2414 GFP_KERNEL);
2415
2416 if (ugeth->rx_skbuff[j] == NULL) {
2417 if (netif_msg_ifup(ugeth))
2418 ugeth_err("%s: Could not allocate rx_skbuff",
2419 __func__);
2420 return -ENOMEM;
2421 }
2422
2423 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2424 ugeth->rx_skbuff[j][i] = NULL;
2425
2426 ugeth->skb_currx[j] = 0;
2427 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2428 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2429 /* set bd status and length */
2430 out_be32((u32 __iomem *)bd, R_I);
2431 /* clear bd buffer */
2432 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2433 bd += sizeof(struct qe_bd);
2434 }
2435 bd -= sizeof(struct qe_bd);
2436 /* set bd status and length */
2437 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2438 }
2439
2440 /*
2441 * Global PRAM
2442 */
2443 /* Tx global PRAM */
2444 /* Allocate global tx parameter RAM page */
2445 ugeth->tx_glbl_pram_offset =
2446 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2447 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2448 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2449 if (netif_msg_ifup(ugeth))
2450 ugeth_err
2451 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2452 __func__);
2453 return -ENOMEM;
2454 }
2455 ugeth->p_tx_glbl_pram =
2456 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2457 tx_glbl_pram_offset);
2458 /* Zero out p_tx_glbl_pram */
2459 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2460
2461 /* Fill global PRAM */
2462
2463 /* TQPTR */
2464 /* Size varies with number of Tx threads */
2465 ugeth->thread_dat_tx_offset =
2466 qe_muram_alloc(numThreadsTxNumerical *
2467 sizeof(struct ucc_geth_thread_data_tx) +
2468 32 * (numThreadsTxNumerical == 1),
2469 UCC_GETH_THREAD_DATA_ALIGNMENT);
2470 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2471 if (netif_msg_ifup(ugeth))
2472 ugeth_err
2473 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2474 __func__);
2475 return -ENOMEM;
2476 }
2477
2478 ugeth->p_thread_data_tx =
2479 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2480 thread_dat_tx_offset);
2481 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2482
2483 /* vtagtable */
2484 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2485 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2486 ug_info->vtagtable[i]);
2487
2488 /* iphoffset */
2489 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2490 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2491 ug_info->iphoffset[i]);
2492
2493 /* SQPTR */
2494 /* Size varies with number of Tx queues */
2495 ugeth->send_q_mem_reg_offset =
2496 qe_muram_alloc(ug_info->numQueuesTx *
2497 sizeof(struct ucc_geth_send_queue_qd),
2498 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2499 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2500 if (netif_msg_ifup(ugeth))
2501 ugeth_err
2502 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2503 __func__);
2504 return -ENOMEM;
2505 }
2506
2507 ugeth->p_send_q_mem_reg =
2508 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2509 send_q_mem_reg_offset);
2510 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2511
2512 /* Setup the table */
2513 /* Assume BD rings are already established */
2514 for (i = 0; i < ug_info->numQueuesTx; i++) {
2515 endOfRing =
2516 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2517 1) * sizeof(struct qe_bd);
2518 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2519 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2520 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2521 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2522 last_bd_completed_address,
2523 (u32) virt_to_phys(endOfRing));
2524 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2525 MEM_PART_MURAM) {
2526 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2527 (u32) immrbar_virt_to_phys(ugeth->
2528 p_tx_bd_ring[i]));
2529 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2530 last_bd_completed_address,
2531 (u32) immrbar_virt_to_phys(endOfRing));
2532 }
2533 }
2534
2535 /* schedulerbasepointer */
2536
2537 if (ug_info->numQueuesTx > 1) {
2538 /* scheduler exists only if more than 1 tx queue */
2539 ugeth->scheduler_offset =
2540 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2541 UCC_GETH_SCHEDULER_ALIGNMENT);
2542 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2543 if (netif_msg_ifup(ugeth))
2544 ugeth_err
2545 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2546 __func__);
2547 return -ENOMEM;
2548 }
2549
2550 ugeth->p_scheduler =
2551 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2552 scheduler_offset);
2553 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2554 ugeth->scheduler_offset);
2555 /* Zero out p_scheduler */
2556 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2557
2558 /* Set values in scheduler */
2559 out_be32(&ugeth->p_scheduler->mblinterval,
2560 ug_info->mblinterval);
2561 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2562 ug_info->nortsrbytetime);
2563 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2564 out_8(&ugeth->p_scheduler->strictpriorityq,
2565 ug_info->strictpriorityq);
2566 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2567 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2568 for (i = 0; i < NUM_TX_QUEUES; i++)
2569 out_8(&ugeth->p_scheduler->weightfactor[i],
2570 ug_info->weightfactor[i]);
2571
2572 /* Set pointers to cpucount registers in scheduler */
2573 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2574 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2575 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2576 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2577 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2578 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2579 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2580 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2581 }
2582
2583 /* schedulerbasepointer */
2584 /* TxRMON_PTR (statistics) */
2585 if (ug_info->
2586 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2587 ugeth->tx_fw_statistics_pram_offset =
2588 qe_muram_alloc(sizeof
2589 (struct ucc_geth_tx_firmware_statistics_pram),
2590 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2591 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2592 if (netif_msg_ifup(ugeth))
2593 ugeth_err
2594 ("%s: Can not allocate DPRAM memory for"
2595 " p_tx_fw_statistics_pram.",
2596 __func__);
2597 return -ENOMEM;
2598 }
2599 ugeth->p_tx_fw_statistics_pram =
2600 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2601 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2602 /* Zero out p_tx_fw_statistics_pram */
2603 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2604 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2605 }
2606
2607 /* temoder */
2608 /* Already has speed set */
2609
2610 if (ug_info->numQueuesTx > 1)
2611 temoder |= TEMODER_SCHEDULER_ENABLE;
2612 if (ug_info->ipCheckSumGenerate)
2613 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2614 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2615 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2616
2617 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2618
2619 /* Function code register value to be used later */
2620 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2621 /* Required for QE */
2622
2623 /* function code register */
2624 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2625
2626 /* Rx global PRAM */
2627 /* Allocate global rx parameter RAM page */
2628 ugeth->rx_glbl_pram_offset =
2629 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2630 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2631 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2632 if (netif_msg_ifup(ugeth))
2633 ugeth_err
2634 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2635 __func__);
2636 return -ENOMEM;
2637 }
2638 ugeth->p_rx_glbl_pram =
2639 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2640 rx_glbl_pram_offset);
2641 /* Zero out p_rx_glbl_pram */
2642 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2643
2644 /* Fill global PRAM */
2645
2646 /* RQPTR */
2647 /* Size varies with number of Rx threads */
2648 ugeth->thread_dat_rx_offset =
2649 qe_muram_alloc(numThreadsRxNumerical *
2650 sizeof(struct ucc_geth_thread_data_rx),
2651 UCC_GETH_THREAD_DATA_ALIGNMENT);
2652 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2653 if (netif_msg_ifup(ugeth))
2654 ugeth_err
2655 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2656 __func__);
2657 return -ENOMEM;
2658 }
2659
2660 ugeth->p_thread_data_rx =
2661 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2662 thread_dat_rx_offset);
2663 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2664
2665 /* typeorlen */
2666 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2667
2668 /* rxrmonbaseptr (statistics) */
2669 if (ug_info->
2670 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2671 ugeth->rx_fw_statistics_pram_offset =
2672 qe_muram_alloc(sizeof
2673 (struct ucc_geth_rx_firmware_statistics_pram),
2674 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2675 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2676 if (netif_msg_ifup(ugeth))
2677 ugeth_err
2678 ("%s: Can not allocate DPRAM memory for"
2679 " p_rx_fw_statistics_pram.", __func__);
2680 return -ENOMEM;
2681 }
2682 ugeth->p_rx_fw_statistics_pram =
2683 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2684 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2685 /* Zero out p_rx_fw_statistics_pram */
2686 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2687 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2688 }
2689
2690 /* intCoalescingPtr */
2691
2692 /* Size varies with number of Rx queues */
2693 ugeth->rx_irq_coalescing_tbl_offset =
2694 qe_muram_alloc(ug_info->numQueuesRx *
2695 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2696 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2697 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2698 if (netif_msg_ifup(ugeth))
2699 ugeth_err
2700 ("%s: Can not allocate DPRAM memory for"
2701 " p_rx_irq_coalescing_tbl.", __func__);
2702 return -ENOMEM;
2703 }
2704
2705 ugeth->p_rx_irq_coalescing_tbl =
2706 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2707 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2708 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2709 ugeth->rx_irq_coalescing_tbl_offset);
2710
2711 /* Fill interrupt coalescing table */
2712 for (i = 0; i < ug_info->numQueuesRx; i++) {
2713 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2714 interruptcoalescingmaxvalue,
2715 ug_info->interruptcoalescingmaxvalue[i]);
2716 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2717 interruptcoalescingcounter,
2718 ug_info->interruptcoalescingmaxvalue[i]);
2719 }
2720
2721 /* MRBLR */
2722 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2723 &ugeth->p_rx_glbl_pram->mrblr);
2724 /* MFLR */
2725 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2726 /* MINFLR */
2727 init_min_frame_len(ug_info->minFrameLength,
2728 &ugeth->p_rx_glbl_pram->minflr,
2729 &ugeth->p_rx_glbl_pram->mrblr);
2730 /* MAXD1 */
2731 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2732 /* MAXD2 */
2733 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2734
2735 /* l2qt */
2736 l2qt = 0;
2737 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2738 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2739 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2740
2741 /* l3qt */
2742 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2743 l3qt = 0;
2744 for (i = 0; i < 8; i++)
2745 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2746 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2747 }
2748
2749 /* vlantype */
2750 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2751
2752 /* vlantci */
2753 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2754
2755 /* ecamptr */
2756 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2757
2758 /* RBDQPTR */
2759 /* Size varies with number of Rx queues */
2760 ugeth->rx_bd_qs_tbl_offset =
2761 qe_muram_alloc(ug_info->numQueuesRx *
2762 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2763 sizeof(struct ucc_geth_rx_prefetched_bds)),
2764 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2765 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2766 if (netif_msg_ifup(ugeth))
2767 ugeth_err
2768 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2769 __func__);
2770 return -ENOMEM;
2771 }
2772
2773 ugeth->p_rx_bd_qs_tbl =
2774 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2775 rx_bd_qs_tbl_offset);
2776 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2777 /* Zero out p_rx_bd_qs_tbl */
2778 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2779 0,
2780 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2781 sizeof(struct ucc_geth_rx_prefetched_bds)));
2782
2783 /* Setup the table */
2784 /* Assume BD rings are already established */
2785 for (i = 0; i < ug_info->numQueuesRx; i++) {
2786 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2787 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2788 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2789 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2790 MEM_PART_MURAM) {
2791 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2792 (u32) immrbar_virt_to_phys(ugeth->
2793 p_rx_bd_ring[i]));
2794 }
2795 /* rest of fields handled by QE */
2796 }
2797
2798 /* remoder */
2799 /* Already has speed set */
2800
2801 if (ugeth->rx_extended_features)
2802 remoder |= REMODER_RX_EXTENDED_FEATURES;
2803 if (ug_info->rxExtendedFiltering)
2804 remoder |= REMODER_RX_EXTENDED_FILTERING;
2805 if (ug_info->dynamicMaxFrameLength)
2806 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2807 if (ug_info->dynamicMinFrameLength)
2808 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2809 remoder |=
2810 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2811 remoder |=
2812 ug_info->
2813 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2814 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2815 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2816 if (ug_info->ipCheckSumCheck)
2817 remoder |= REMODER_IP_CHECKSUM_CHECK;
2818 if (ug_info->ipAddressAlignment)
2819 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2820 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2821
2822 /* Note that this function must be called */
2823 /* ONLY AFTER p_tx_fw_statistics_pram */
2824 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2825 init_firmware_statistics_gathering_mode((ug_info->
2826 statisticsMode &
2827 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2828 (ug_info->statisticsMode &
2829 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2830 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2831 ugeth->tx_fw_statistics_pram_offset,
2832 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2833 ugeth->rx_fw_statistics_pram_offset,
2834 &ugeth->p_tx_glbl_pram->temoder,
2835 &ugeth->p_rx_glbl_pram->remoder);
2836
2837 /* function code register */
2838 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2839
2840 /* initialize extended filtering */
2841 if (ug_info->rxExtendedFiltering) {
2842 if (!ug_info->extendedFilteringChainPointer) {
2843 if (netif_msg_ifup(ugeth))
2844 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2845 __func__);
2846 return -EINVAL;
2847 }
2848
2849 /* Allocate memory for extended filtering Mode Global
2850 Parameters */
2851 ugeth->exf_glbl_param_offset =
2852 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2853 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2854 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2855 if (netif_msg_ifup(ugeth))
2856 ugeth_err
2857 ("%s: Can not allocate DPRAM memory for"
2858 " p_exf_glbl_param.", __func__);
2859 return -ENOMEM;
2860 }
2861
2862 ugeth->p_exf_glbl_param =
2863 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2864 exf_glbl_param_offset);
2865 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2866 ugeth->exf_glbl_param_offset);
2867 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2868 (u32) ug_info->extendedFilteringChainPointer);
2869
2870 } else { /* initialize 82xx style address filtering */
2871
2872 /* Init individual address recognition registers to disabled */
2873
2874 for (j = 0; j < NUM_OF_PADDRS; j++)
2875 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2876
2877 p_82xx_addr_filt =
2878 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2879 p_rx_glbl_pram->addressfiltering;
2880
2881 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2882 ENET_ADDR_TYPE_GROUP);
2883 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2884 ENET_ADDR_TYPE_INDIVIDUAL);
2885 }
2886
2887 /*
2888 * Initialize UCC at QE level
2889 */
2890
2891 command = QE_INIT_TX_RX;
2892
2893 /* Allocate shadow InitEnet command parameter structure.
2894 * This is needed because after the InitEnet command is executed,
2895 * the structure in DPRAM is released, because DPRAM is a premium
2896 * resource.
2897 * This shadow structure keeps a copy of what was done so that the
2898 * allocated resources can be released when the channel is freed.
2899 */
2900 if (!(ugeth->p_init_enet_param_shadow =
2901 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2902 if (netif_msg_ifup(ugeth))
2903 ugeth_err
2904 ("%s: Can not allocate memory for"
2905 " p_UccInitEnetParamShadows.", __func__);
2906 return -ENOMEM;
2907 }
2908 /* Zero out *p_init_enet_param_shadow */
2909 memset((char *)ugeth->p_init_enet_param_shadow,
2910 0, sizeof(struct ucc_geth_init_pram));
2911
2912 /* Fill shadow InitEnet command parameter structure */
2913
2914 ugeth->p_init_enet_param_shadow->resinit1 =
2915 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2916 ugeth->p_init_enet_param_shadow->resinit2 =
2917 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2918 ugeth->p_init_enet_param_shadow->resinit3 =
2919 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2920 ugeth->p_init_enet_param_shadow->resinit4 =
2921 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2922 ugeth->p_init_enet_param_shadow->resinit5 =
2923 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2924 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2925 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2926 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2927 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2928
2929 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2930 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2931 if ((ug_info->largestexternallookupkeysize !=
2932 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2933 && (ug_info->largestexternallookupkeysize !=
2934 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2935 && (ug_info->largestexternallookupkeysize !=
2936 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2937 if (netif_msg_ifup(ugeth))
2938 ugeth_err("%s: Invalid largest External Lookup Key Size.",
2939 __func__);
2940 return -EINVAL;
2941 }
2942 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2943 ug_info->largestexternallookupkeysize;
2944 size = sizeof(struct ucc_geth_thread_rx_pram);
2945 if (ug_info->rxExtendedFiltering) {
2946 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2947 if (ug_info->largestexternallookupkeysize ==
2948 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2949 size +=
2950 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2951 if (ug_info->largestexternallookupkeysize ==
2952 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2953 size +=
2954 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2955 }
2956
2957 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2958 p_init_enet_param_shadow->rxthread[0]),
2959 (u8) (numThreadsRxNumerical + 1)
2960 /* Rx needs one extra for terminator */
2961 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2962 ug_info->riscRx, 1)) != 0) {
2963 if (netif_msg_ifup(ugeth))
2964 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2965 __func__);
2966 return ret_val;
2967 }
2968
2969 ugeth->p_init_enet_param_shadow->txglobal =
2970 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
2971 if ((ret_val =
2972 fill_init_enet_entries(ugeth,
2973 &(ugeth->p_init_enet_param_shadow->
2974 txthread[0]), numThreadsTxNumerical,
2975 sizeof(struct ucc_geth_thread_tx_pram),
2976 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
2977 ug_info->riscTx, 0)) != 0) {
2978 if (netif_msg_ifup(ugeth))
2979 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2980 __func__);
2981 return ret_val;
2982 }
2983
2984 /* Load Rx bds with buffers */
2985 for (i = 0; i < ug_info->numQueuesRx; i++) {
2986 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
2987 if (netif_msg_ifup(ugeth))
2988 ugeth_err("%s: Can not fill Rx bds with buffers.",
2989 __func__);
2990 return ret_val;
2991 }
2992 }
2993
2994 /* Allocate InitEnet command parameter structure */
2995 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
2996 if (IS_ERR_VALUE(init_enet_pram_offset)) {
2997 if (netif_msg_ifup(ugeth))
2998 ugeth_err
2999 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3000 __func__);
3001 return -ENOMEM;
3002 }
3003 p_init_enet_pram =
3004 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3005
3006 /* Copy shadow InitEnet command parameter structure into PRAM */
3007 out_8(&p_init_enet_pram->resinit1,
3008 ugeth->p_init_enet_param_shadow->resinit1);
3009 out_8(&p_init_enet_pram->resinit2,
3010 ugeth->p_init_enet_param_shadow->resinit2);
3011 out_8(&p_init_enet_pram->resinit3,
3012 ugeth->p_init_enet_param_shadow->resinit3);
3013 out_8(&p_init_enet_pram->resinit4,
3014 ugeth->p_init_enet_param_shadow->resinit4);
3015 out_be16(&p_init_enet_pram->resinit5,
3016 ugeth->p_init_enet_param_shadow->resinit5);
3017 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3018 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3019 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3020 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3021 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3022 out_be32(&p_init_enet_pram->rxthread[i],
3023 ugeth->p_init_enet_param_shadow->rxthread[i]);
3024 out_be32(&p_init_enet_pram->txglobal,
3025 ugeth->p_init_enet_param_shadow->txglobal);
3026 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3027 out_be32(&p_init_enet_pram->txthread[i],
3028 ugeth->p_init_enet_param_shadow->txthread[i]);
3029
3030 /* Issue QE command */
3031 cecr_subblock =
3032 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3033 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3034 init_enet_pram_offset);
3035
3036 /* Free InitEnet command parameter */
3037 qe_muram_free(init_enet_pram_offset);
3038
3039 return 0;
3040 }
3041
3042 /* This is called by the kernel when a frame is ready for transmission. */
3043 /* It is pointed to by the dev->hard_start_xmit function pointer */
3044 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3045 {
3046 struct ucc_geth_private *ugeth = netdev_priv(dev);
3047 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3048 struct ucc_fast_private *uccf;
3049 #endif
3050 u8 __iomem *bd; /* BD pointer */
3051 u32 bd_status;
3052 u8 txQ = 0;
3053
3054 ugeth_vdbg("%s: IN", __func__);
3055
3056 spin_lock_irq(&ugeth->lock);
3057
3058 dev->stats.tx_bytes += skb->len;
3059
3060 /* Start from the next BD that should be filled */
3061 bd = ugeth->txBd[txQ];
3062 bd_status = in_be32((u32 __iomem *)bd);
3063 /* Save the skb pointer so we can free it later */
3064 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3065
3066 /* Update the current skb pointer (wrapping if this was the last) */
3067 ugeth->skb_curtx[txQ] =
3068 (ugeth->skb_curtx[txQ] +
3069 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3070
3071 /* set up the buffer descriptor */
3072 out_be32(&((struct qe_bd __iomem *)bd)->buf,
3073 dma_map_single(ugeth->dev, skb->data,
3074 skb->len, DMA_TO_DEVICE));
3075
3076 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3077
3078 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3079
3080 /* set bd status and length */
3081 out_be32((u32 __iomem *)bd, bd_status);
3082
3083 dev->trans_start = jiffies;
3084
3085 /* Move to next BD in the ring */
3086 if (!(bd_status & T_W))
3087 bd += sizeof(struct qe_bd);
3088 else
3089 bd = ugeth->p_tx_bd_ring[txQ];
3090
3091 /* If the next BD still needs to be cleaned up, then the bds
3092 are full. We need to tell the kernel to stop sending us stuff. */
3093 if (bd == ugeth->confBd[txQ]) {
3094 if (!netif_queue_stopped(dev))
3095 netif_stop_queue(dev);
3096 }
3097
3098 ugeth->txBd[txQ] = bd;
3099
3100 if (ugeth->p_scheduler) {
3101 ugeth->cpucount[txQ]++;
3102 /* Indicate to QE that there are more Tx bds ready for
3103 transmission */
3104 /* This is done by writing a running counter of the bd
3105 count to the scheduler PRAM. */
3106 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3107 }
3108
3109 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3110 uccf = ugeth->uccf;
3111 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3112 #endif
3113 spin_unlock_irq(&ugeth->lock);
3114
3115 return 0;
3116 }
3117
3118 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3119 {
3120 struct sk_buff *skb;
3121 u8 __iomem *bd;
3122 u16 length, howmany = 0;
3123 u32 bd_status;
3124 u8 *bdBuffer;
3125 struct net_device *dev;
3126
3127 ugeth_vdbg("%s: IN", __func__);
3128
3129 dev = ugeth->ndev;
3130
3131 /* collect received buffers */
3132 bd = ugeth->rxBd[rxQ];
3133
3134 bd_status = in_be32((u32 __iomem *)bd);
3135
3136 /* while there are received buffers and BD is full (~R_E) */
3137 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3138 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3139 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3140 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3141
3142 /* determine whether buffer is first, last, first and last
3143 (single buffer frame) or middle (not first and not last) */
3144 if (!skb ||
3145 (!(bd_status & (R_F | R_L))) ||
3146 (bd_status & R_ERRORS_FATAL)) {
3147 if (netif_msg_rx_err(ugeth))
3148 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3149 __func__, __LINE__, (u32) skb);
3150 if (skb)
3151 dev_kfree_skb_any(skb);
3152
3153 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3154 dev->stats.rx_dropped++;
3155 } else {
3156 dev->stats.rx_packets++;
3157 howmany++;
3158
3159 /* Prep the skb for the packet */
3160 skb_put(skb, length);
3161
3162 /* Tell the skb what kind of packet this is */
3163 skb->protocol = eth_type_trans(skb, ugeth->ndev);
3164
3165 dev->stats.rx_bytes += length;
3166 /* Send the packet up the stack */
3167 netif_receive_skb(skb);
3168 }
3169
3170 skb = get_new_skb(ugeth, bd);
3171 if (!skb) {
3172 if (netif_msg_rx_err(ugeth))
3173 ugeth_warn("%s: No Rx Data Buffer", __func__);
3174 dev->stats.rx_dropped++;
3175 break;
3176 }
3177
3178 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3179
3180 /* update to point at the next skb */
3181 ugeth->skb_currx[rxQ] =
3182 (ugeth->skb_currx[rxQ] +
3183 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3184
3185 if (bd_status & R_W)
3186 bd = ugeth->p_rx_bd_ring[rxQ];
3187 else
3188 bd += sizeof(struct qe_bd);
3189
3190 bd_status = in_be32((u32 __iomem *)bd);
3191 }
3192
3193 ugeth->rxBd[rxQ] = bd;
3194 return howmany;
3195 }
3196
3197 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3198 {
3199 /* Start from the next BD that should be filled */
3200 struct ucc_geth_private *ugeth = netdev_priv(dev);
3201 u8 __iomem *bd; /* BD pointer */
3202 u32 bd_status;
3203
3204 bd = ugeth->confBd[txQ];
3205 bd_status = in_be32((u32 __iomem *)bd);
3206
3207 /* Normal processing. */
3208 while ((bd_status & T_R) == 0) {
3209 /* BD contains already transmitted buffer. */
3210 /* Handle the transmitted buffer and release */
3211 /* the BD to be used with the current frame */
3212
3213 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3214 break;
3215
3216 dev->stats.tx_packets++;
3217
3218 /* Free the sk buffer associated with this TxBD */
3219 dev_kfree_skb_irq(ugeth->
3220 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3221 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3222 ugeth->skb_dirtytx[txQ] =
3223 (ugeth->skb_dirtytx[txQ] +
3224 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3225
3226 /* We freed a buffer, so now we can restart transmission */
3227 if (netif_queue_stopped(dev))
3228 netif_wake_queue(dev);
3229
3230 /* Advance the confirmation BD pointer */
3231 if (!(bd_status & T_W))
3232 bd += sizeof(struct qe_bd);
3233 else
3234 bd = ugeth->p_tx_bd_ring[txQ];
3235 bd_status = in_be32((u32 __iomem *)bd);
3236 }
3237 ugeth->confBd[txQ] = bd;
3238 return 0;
3239 }
3240
3241 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3242 {
3243 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3244 struct ucc_geth_info *ug_info;
3245 int howmany, i;
3246
3247 ug_info = ugeth->ug_info;
3248
3249 howmany = 0;
3250 for (i = 0; i < ug_info->numQueuesRx; i++)
3251 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3252
3253 if (howmany < budget) {
3254 napi_complete(napi);
3255 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS);
3256 }
3257
3258 return howmany;
3259 }
3260
3261 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3262 {
3263 struct net_device *dev = info;
3264 struct ucc_geth_private *ugeth = netdev_priv(dev);
3265 struct ucc_fast_private *uccf;
3266 struct ucc_geth_info *ug_info;
3267 register u32 ucce;
3268 register u32 uccm;
3269 register u32 tx_mask;
3270 u8 i;
3271
3272 ugeth_vdbg("%s: IN", __func__);
3273
3274 uccf = ugeth->uccf;
3275 ug_info = ugeth->ug_info;
3276
3277 /* read and clear events */
3278 ucce = (u32) in_be32(uccf->p_ucce);
3279 uccm = (u32) in_be32(uccf->p_uccm);
3280 ucce &= uccm;
3281 out_be32(uccf->p_ucce, ucce);
3282
3283 /* check for receive events that require processing */
3284 if (ucce & UCCE_RX_EVENTS) {
3285 if (napi_schedule_prep(&ugeth->napi)) {
3286 uccm &= ~UCCE_RX_EVENTS;
3287 out_be32(uccf->p_uccm, uccm);
3288 __napi_schedule(&ugeth->napi);
3289 }
3290 }
3291
3292 /* Tx event processing */
3293 if (ucce & UCCE_TX_EVENTS) {
3294 spin_lock(&ugeth->lock);
3295 tx_mask = UCC_GETH_UCCE_TXB0;
3296 for (i = 0; i < ug_info->numQueuesTx; i++) {
3297 if (ucce & tx_mask)
3298 ucc_geth_tx(dev, i);
3299 ucce &= ~tx_mask;
3300 tx_mask <<= 1;
3301 }
3302 spin_unlock(&ugeth->lock);
3303 }
3304
3305 /* Errors and other events */
3306 if (ucce & UCCE_OTHER) {
3307 if (ucce & UCC_GETH_UCCE_BSY)
3308 dev->stats.rx_errors++;
3309 if (ucce & UCC_GETH_UCCE_TXE)
3310 dev->stats.tx_errors++;
3311 }
3312
3313 return IRQ_HANDLED;
3314 }
3315
3316 #ifdef CONFIG_NET_POLL_CONTROLLER
3317 /*
3318 * Polling 'interrupt' - used by things like netconsole to send skbs
3319 * without having to re-enable interrupts. It's not called while
3320 * the interrupt routine is executing.
3321 */
3322 static void ucc_netpoll(struct net_device *dev)
3323 {
3324 struct ucc_geth_private *ugeth = netdev_priv(dev);
3325 int irq = ugeth->ug_info->uf_info.irq;
3326
3327 disable_irq(irq);
3328 ucc_geth_irq_handler(irq, dev);
3329 enable_irq(irq);
3330 }
3331 #endif /* CONFIG_NET_POLL_CONTROLLER */
3332
3333 /* Called when something needs to use the ethernet device */
3334 /* Returns 0 for success. */
3335 static int ucc_geth_open(struct net_device *dev)
3336 {
3337 struct ucc_geth_private *ugeth = netdev_priv(dev);
3338 int err;
3339
3340 ugeth_vdbg("%s: IN", __func__);
3341
3342 /* Test station address */
3343 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3344 if (netif_msg_ifup(ugeth))
3345 ugeth_err("%s: Multicast address used for station address"
3346 " - is this what you wanted?", __func__);
3347 return -EINVAL;
3348 }
3349
3350 err = init_phy(dev);
3351 if (err) {
3352 if (netif_msg_ifup(ugeth))
3353 ugeth_err("%s: Cannot initialize PHY, aborting.",
3354 dev->name);
3355 return err;
3356 }
3357
3358 err = ucc_struct_init(ugeth);
3359 if (err) {
3360 if (netif_msg_ifup(ugeth))
3361 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3362 goto out_err_stop;
3363 }
3364
3365 napi_enable(&ugeth->napi);
3366
3367 err = ucc_geth_startup(ugeth);
3368 if (err) {
3369 if (netif_msg_ifup(ugeth))
3370 ugeth_err("%s: Cannot configure net device, aborting.",
3371 dev->name);
3372 goto out_err;
3373 }
3374
3375 err = adjust_enet_interface(ugeth);
3376 if (err) {
3377 if (netif_msg_ifup(ugeth))
3378 ugeth_err("%s: Cannot configure net device, aborting.",
3379 dev->name);
3380 goto out_err;
3381 }
3382
3383 /* Set MACSTNADDR1, MACSTNADDR2 */
3384 /* For more details see the hardware spec. */
3385 init_mac_station_addr_regs(dev->dev_addr[0],
3386 dev->dev_addr[1],
3387 dev->dev_addr[2],
3388 dev->dev_addr[3],
3389 dev->dev_addr[4],
3390 dev->dev_addr[5],
3391 &ugeth->ug_regs->macstnaddr1,
3392 &ugeth->ug_regs->macstnaddr2);
3393
3394 phy_start(ugeth->phydev);
3395
3396 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3397 if (err) {
3398 if (netif_msg_ifup(ugeth))
3399 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3400 goto out_err;
3401 }
3402
3403 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3404 0, "UCC Geth", dev);
3405 if (err) {
3406 if (netif_msg_ifup(ugeth))
3407 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3408 dev->name);
3409 goto out_err;
3410 }
3411
3412 netif_start_queue(dev);
3413
3414 return err;
3415
3416 out_err:
3417 napi_disable(&ugeth->napi);
3418 out_err_stop:
3419 ucc_geth_stop(ugeth);
3420 return err;
3421 }
3422
3423 /* Stops the kernel queue, and halts the controller */
3424 static int ucc_geth_close(struct net_device *dev)
3425 {
3426 struct ucc_geth_private *ugeth = netdev_priv(dev);
3427
3428 ugeth_vdbg("%s: IN", __func__);
3429
3430 napi_disable(&ugeth->napi);
3431
3432 ucc_geth_stop(ugeth);
3433
3434 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3435
3436 netif_stop_queue(dev);
3437
3438 return 0;
3439 }
3440
3441 /* Reopen device. This will reset the MAC and PHY. */
3442 static void ucc_geth_timeout_work(struct work_struct *work)
3443 {
3444 struct ucc_geth_private *ugeth;
3445 struct net_device *dev;
3446
3447 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3448 dev = ugeth->ndev;
3449
3450 ugeth_vdbg("%s: IN", __func__);
3451
3452 dev->stats.tx_errors++;
3453
3454 ugeth_dump_regs(ugeth);
3455
3456 if (dev->flags & IFF_UP) {
3457 /*
3458 * Must reset MAC *and* PHY. This is done by reopening
3459 * the device.
3460 */
3461 ucc_geth_close(dev);
3462 ucc_geth_open(dev);
3463 }
3464
3465 netif_tx_schedule_all(dev);
3466 }
3467
3468 /*
3469 * ucc_geth_timeout gets called when a packet has not been
3470 * transmitted after a set amount of time.
3471 */
3472 static void ucc_geth_timeout(struct net_device *dev)
3473 {
3474 struct ucc_geth_private *ugeth = netdev_priv(dev);
3475
3476 netif_carrier_off(dev);
3477 schedule_work(&ugeth->timeout_work);
3478 }
3479
3480 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3481 {
3482 if (strcasecmp(phy_connection_type, "mii") == 0)
3483 return PHY_INTERFACE_MODE_MII;
3484 if (strcasecmp(phy_connection_type, "gmii") == 0)
3485 return PHY_INTERFACE_MODE_GMII;
3486 if (strcasecmp(phy_connection_type, "tbi") == 0)
3487 return PHY_INTERFACE_MODE_TBI;
3488 if (strcasecmp(phy_connection_type, "rmii") == 0)
3489 return PHY_INTERFACE_MODE_RMII;
3490 if (strcasecmp(phy_connection_type, "rgmii") == 0)
3491 return PHY_INTERFACE_MODE_RGMII;
3492 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3493 return PHY_INTERFACE_MODE_RGMII_ID;
3494 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3495 return PHY_INTERFACE_MODE_RGMII_TXID;
3496 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3497 return PHY_INTERFACE_MODE_RGMII_RXID;
3498 if (strcasecmp(phy_connection_type, "rtbi") == 0)
3499 return PHY_INTERFACE_MODE_RTBI;
3500
3501 return PHY_INTERFACE_MODE_MII;
3502 }
3503
3504 static const struct net_device_ops ucc_geth_netdev_ops = {
3505 .ndo_open = ucc_geth_open,
3506 .ndo_stop = ucc_geth_close,
3507 .ndo_start_xmit = ucc_geth_start_xmit,
3508 .ndo_validate_addr = eth_validate_addr,
3509 .ndo_set_mac_address = eth_mac_addr,
3510 .ndo_change_mtu = eth_change_mtu,
3511 .ndo_set_multicast_list = ucc_geth_set_multi,
3512 .ndo_tx_timeout = ucc_geth_timeout,
3513 #ifdef CONFIG_NET_POLL_CONTROLLER
3514 .ndo_poll_controller = ucc_netpoll,
3515 #endif
3516 };
3517
3518 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3519 {
3520 struct device *device = &ofdev->dev;
3521 struct device_node *np = ofdev->node;
3522 struct device_node *mdio;
3523 struct net_device *dev = NULL;
3524 struct ucc_geth_private *ugeth = NULL;
3525 struct ucc_geth_info *ug_info;
3526 struct resource res;
3527 struct device_node *phy;
3528 int err, ucc_num, max_speed = 0;
3529 const phandle *ph;
3530 const u32 *fixed_link;
3531 const unsigned int *prop;
3532 const char *sprop;
3533 const void *mac_addr;
3534 phy_interface_t phy_interface;
3535 static const int enet_to_speed[] = {
3536 SPEED_10, SPEED_10, SPEED_10,
3537 SPEED_100, SPEED_100, SPEED_100,
3538 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3539 };
3540 static const phy_interface_t enet_to_phy_interface[] = {
3541 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3542 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3543 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3544 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3545 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3546 };
3547
3548 ugeth_vdbg("%s: IN", __func__);
3549
3550 prop = of_get_property(np, "cell-index", NULL);
3551 if (!prop) {
3552 prop = of_get_property(np, "device-id", NULL);
3553 if (!prop)
3554 return -ENODEV;
3555 }
3556
3557 ucc_num = *prop - 1;
3558 if ((ucc_num < 0) || (ucc_num > 7))
3559 return -ENODEV;
3560
3561 ug_info = &ugeth_info[ucc_num];
3562 if (ug_info == NULL) {
3563 if (netif_msg_probe(&debug))
3564 ugeth_err("%s: [%d] Missing additional data!",
3565 __func__, ucc_num);
3566 return -ENODEV;
3567 }
3568
3569 ug_info->uf_info.ucc_num = ucc_num;
3570
3571 sprop = of_get_property(np, "rx-clock-name", NULL);
3572 if (sprop) {
3573 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3574 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3575 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3576 printk(KERN_ERR
3577 "ucc_geth: invalid rx-clock-name property\n");
3578 return -EINVAL;
3579 }
3580 } else {
3581 prop = of_get_property(np, "rx-clock", NULL);
3582 if (!prop) {
3583 /* If both rx-clock-name and rx-clock are missing,
3584 we want to tell people to use rx-clock-name. */
3585 printk(KERN_ERR
3586 "ucc_geth: missing rx-clock-name property\n");
3587 return -EINVAL;
3588 }
3589 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3590 printk(KERN_ERR
3591 "ucc_geth: invalid rx-clock propperty\n");
3592 return -EINVAL;
3593 }
3594 ug_info->uf_info.rx_clock = *prop;
3595 }
3596
3597 sprop = of_get_property(np, "tx-clock-name", NULL);
3598 if (sprop) {
3599 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3600 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3601 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3602 printk(KERN_ERR
3603 "ucc_geth: invalid tx-clock-name property\n");
3604 return -EINVAL;
3605 }
3606 } else {
3607 prop = of_get_property(np, "tx-clock", NULL);
3608 if (!prop) {
3609 printk(KERN_ERR
3610 "ucc_geth: mising tx-clock-name property\n");
3611 return -EINVAL;
3612 }
3613 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3614 printk(KERN_ERR
3615 "ucc_geth: invalid tx-clock property\n");
3616 return -EINVAL;
3617 }
3618 ug_info->uf_info.tx_clock = *prop;
3619 }
3620
3621 err = of_address_to_resource(np, 0, &res);
3622 if (err)
3623 return -EINVAL;
3624
3625 ug_info->uf_info.regs = res.start;
3626 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3627 fixed_link = of_get_property(np, "fixed-link", NULL);
3628 if (fixed_link) {
3629 snprintf(ug_info->phy_bus_id, sizeof(ug_info->phy_bus_id),
3630 PHY_ID_FMT, "0", fixed_link[0]);
3631 phy = NULL;
3632 } else {
3633 char bus_name[MII_BUS_ID_SIZE];
3634
3635 ph = of_get_property(np, "phy-handle", NULL);
3636 phy = of_find_node_by_phandle(*ph);
3637
3638 if (phy == NULL)
3639 return -ENODEV;
3640
3641 /* set the PHY address */
3642 prop = of_get_property(phy, "reg", NULL);
3643 if (prop == NULL)
3644 return -1;
3645
3646 /* Set the bus id */
3647 mdio = of_get_parent(phy);
3648
3649 if (mdio == NULL)
3650 return -ENODEV;
3651
3652 err = of_address_to_resource(mdio, 0, &res);
3653
3654 if (err) {
3655 of_node_put(mdio);
3656 return err;
3657 }
3658 fsl_pq_mdio_bus_name(bus_name, mdio);
3659 of_node_put(mdio);
3660 snprintf(ug_info->phy_bus_id, sizeof(ug_info->phy_bus_id),
3661 "%s:%02x", bus_name, *prop);
3662 }
3663
3664 /* get the phy interface type, or default to MII */
3665 prop = of_get_property(np, "phy-connection-type", NULL);
3666 if (!prop) {
3667 /* handle interface property present in old trees */
3668 prop = of_get_property(phy, "interface", NULL);
3669 if (prop != NULL) {
3670 phy_interface = enet_to_phy_interface[*prop];
3671 max_speed = enet_to_speed[*prop];
3672 } else
3673 phy_interface = PHY_INTERFACE_MODE_MII;
3674 } else {
3675 phy_interface = to_phy_interface((const char *)prop);
3676 }
3677
3678 /* get speed, or derive from PHY interface */
3679 if (max_speed == 0)
3680 switch (phy_interface) {
3681 case PHY_INTERFACE_MODE_GMII:
3682 case PHY_INTERFACE_MODE_RGMII:
3683 case PHY_INTERFACE_MODE_RGMII_ID:
3684 case PHY_INTERFACE_MODE_RGMII_RXID:
3685 case PHY_INTERFACE_MODE_RGMII_TXID:
3686 case PHY_INTERFACE_MODE_TBI:
3687 case PHY_INTERFACE_MODE_RTBI:
3688 max_speed = SPEED_1000;
3689 break;
3690 default:
3691 max_speed = SPEED_100;
3692 break;
3693 }
3694
3695 if (max_speed == SPEED_1000) {
3696 /* configure muram FIFOs for gigabit operation */
3697 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3698 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3699 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3700 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3701 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3702 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3703 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3704 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3705 }
3706
3707 if (netif_msg_probe(&debug))
3708 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3709 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3710 ug_info->uf_info.irq);
3711
3712 /* Create an ethernet device instance */
3713 dev = alloc_etherdev(sizeof(*ugeth));
3714
3715 if (dev == NULL)
3716 return -ENOMEM;
3717
3718 ugeth = netdev_priv(dev);
3719 spin_lock_init(&ugeth->lock);
3720
3721 /* Create CQs for hash tables */
3722 INIT_LIST_HEAD(&ugeth->group_hash_q);
3723 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3724
3725 dev_set_drvdata(device, dev);
3726
3727 /* Set the dev->base_addr to the gfar reg region */
3728 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3729
3730 SET_NETDEV_DEV(dev, device);
3731
3732 /* Fill in the dev structure */
3733 uec_set_ethtool_ops(dev);
3734 dev->netdev_ops = &ucc_geth_netdev_ops;
3735 dev->watchdog_timeo = TX_TIMEOUT;
3736 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3737 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
3738 dev->mtu = 1500;
3739
3740 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3741 ugeth->phy_interface = phy_interface;
3742 ugeth->max_speed = max_speed;
3743
3744 err = register_netdev(dev);
3745 if (err) {
3746 if (netif_msg_probe(ugeth))
3747 ugeth_err("%s: Cannot register net device, aborting.",
3748 dev->name);
3749 free_netdev(dev);
3750 return err;
3751 }
3752
3753 mac_addr = of_get_mac_address(np);
3754 if (mac_addr)
3755 memcpy(dev->dev_addr, mac_addr, 6);
3756
3757 ugeth->ug_info = ug_info;
3758 ugeth->dev = device;
3759 ugeth->ndev = dev;
3760 ugeth->node = np;
3761
3762 return 0;
3763 }
3764
3765 static int ucc_geth_remove(struct of_device* ofdev)
3766 {
3767 struct device *device = &ofdev->dev;
3768 struct net_device *dev = dev_get_drvdata(device);
3769 struct ucc_geth_private *ugeth = netdev_priv(dev);
3770
3771 unregister_netdev(dev);
3772 free_netdev(dev);
3773 ucc_geth_memclean(ugeth);
3774 dev_set_drvdata(device, NULL);
3775
3776 return 0;
3777 }
3778
3779 static struct of_device_id ucc_geth_match[] = {
3780 {
3781 .type = "network",
3782 .compatible = "ucc_geth",
3783 },
3784 {},
3785 };
3786
3787 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3788
3789 static struct of_platform_driver ucc_geth_driver = {
3790 .name = DRV_NAME,
3791 .match_table = ucc_geth_match,
3792 .probe = ucc_geth_probe,
3793 .remove = ucc_geth_remove,
3794 };
3795
3796 static int __init ucc_geth_init(void)
3797 {
3798 int i, ret;
3799
3800 if (netif_msg_drv(&debug))
3801 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3802 for (i = 0; i < 8; i++)
3803 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3804 sizeof(ugeth_primary_info));
3805
3806 ret = of_register_platform_driver(&ucc_geth_driver);
3807
3808 return ret;
3809 }
3810
3811 static void __exit ucc_geth_exit(void)
3812 {
3813 of_unregister_platform_driver(&ucc_geth_driver);
3814 }
3815
3816 module_init(ucc_geth_init);
3817 module_exit(ucc_geth_exit);
3818
3819 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3820 MODULE_DESCRIPTION(DRV_DESC);
3821 MODULE_VERSION(DRV_VERSION);
3822 MODULE_LICENSE("GPL");
Linux with added FPC-III support