include/sound/sof/topology.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
   2 /*
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * Copyright(c) 2018 Intel Corporation. All rights reserved.
   7  */
   8
   9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
  10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
  11
  12 #include <sound/sof/header.h>
  13
  14 /*
  15  * Component
  16  */
  17
  18 /* types of component */
  19 enum sof_comp_type {
  20         SOF_COMP_NONE = 0,
  21         SOF_COMP_HOST,
  22         SOF_COMP_DAI,
  23         SOF_COMP_SG_HOST,       /**< scatter gather variant */
  24         SOF_COMP_SG_DAI,        /**< scatter gather variant */
  25         SOF_COMP_VOLUME,
  26         SOF_COMP_MIXER,
  27         SOF_COMP_MUX,
  28         SOF_COMP_SRC,
  29         SOF_COMP_SPLITTER,
  30         SOF_COMP_TONE,
  31         SOF_COMP_SWITCH,
  32         SOF_COMP_BUFFER,
  33         SOF_COMP_EQ_IIR,
  34         SOF_COMP_EQ_FIR,
  35         SOF_COMP_KEYWORD_DETECT,
  36         SOF_COMP_KPB,                   /* A key phrase buffer component */
  37         SOF_COMP_SELECTOR,              /**< channel selector component */
  38         SOF_COMP_DEMUX,
  39         SOF_COMP_ASRC,          /**< Asynchronous sample rate converter */
  40         /* keep FILEREAD/FILEWRITE as the last ones */
  41         SOF_COMP_FILEREAD = 10000,      /**< host test based file IO */
  42         SOF_COMP_FILEWRITE = 10001,     /**< host test based file IO */
  43 };
  44
  45 /* XRUN action for component */
  46 #define SOF_XRUN_STOP           1       /**< stop stream */
  47 #define SOF_XRUN_UNDER_ZERO     2       /**< send 0s to sink */
  48 #define SOF_XRUN_OVER_NULL      4       /**< send data to NULL */
  49
  50 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
  51 struct sof_ipc_comp {
  52         struct sof_ipc_cmd_hdr hdr;
  53         uint32_t id;
  54         enum sof_comp_type type;
  55         uint32_t pipeline_id;
  56         uint32_t core;
  57
  58         /* reserved for future use */
  59         uint32_t reserved[1];
  60 } __packed;
  61
  62 /*
  63  * Component Buffers
  64  */
  65
  66 /*
  67  * SOF memory capabilities, add new ones at the end
  68  */
  69 #define SOF_MEM_CAPS_RAM                        (1 << 0)
  70 #define SOF_MEM_CAPS_ROM                        (1 << 1)
  71 #define SOF_MEM_CAPS_EXT                        (1 << 2) /**< external */
  72 #define SOF_MEM_CAPS_LP                 (1 << 3) /**< low power */
  73 #define SOF_MEM_CAPS_HP                 (1 << 4) /**< high performance */
  74 #define SOF_MEM_CAPS_DMA                        (1 << 5) /**< DMA'able */
  75 #define SOF_MEM_CAPS_CACHE                      (1 << 6) /**< cacheable */
  76 #define SOF_MEM_CAPS_EXEC                       (1 << 7) /**< executable */
  77
  78 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
  79 struct sof_ipc_buffer {
  80         struct sof_ipc_comp comp;
  81         uint32_t size;          /**< buffer size in bytes */
  82         uint32_t caps;          /**< SOF_MEM_CAPS_ */
  83 } __packed;
  84
  85 /* generic component config data - must always be after struct sof_ipc_comp */
  86 struct sof_ipc_comp_config {
  87         struct sof_ipc_cmd_hdr hdr;
  88         uint32_t periods_sink;  /**< 0 means variable */
  89         uint32_t periods_source;/**< 0 means variable */
  90         uint32_t reserved1;     /**< reserved */
  91         uint32_t frame_fmt;     /**< SOF_IPC_FRAME_ */
  92         uint32_t xrun_action;
  93
  94         /* reserved for future use */
  95         uint32_t reserved[2];
  96 } __packed;
  97
  98 /* generic host component */
  99 struct sof_ipc_comp_host {
 100         struct sof_ipc_comp comp;
 101         struct sof_ipc_comp_config config;
 102         uint32_t direction;     /**< SOF_IPC_STREAM_ */
 103         uint32_t no_irq;        /**< don't send periodic IRQ to host/DSP */
 104         uint32_t dmac_config; /**< DMA engine specific */
 105 }  __packed;
 106
 107 /* generic DAI component */
 108 struct sof_ipc_comp_dai {
 109         struct sof_ipc_comp comp;
 110         struct sof_ipc_comp_config config;
 111         uint32_t direction;     /**< SOF_IPC_STREAM_ */
 112         uint32_t dai_index;     /**< index of this type dai */
 113         uint32_t type;          /**< DAI type - SOF_DAI_ */
 114         uint32_t reserved;      /**< reserved */
 115 }  __packed;
 116
 117 /* generic mixer component */
 118 struct sof_ipc_comp_mixer {
 119         struct sof_ipc_comp comp;
 120         struct sof_ipc_comp_config config;
 121 }  __packed;
 122
 123 /* volume ramping types */
 124 enum sof_volume_ramp {
 125         SOF_VOLUME_LINEAR       = 0,
 126         SOF_VOLUME_LOG,
 127         SOF_VOLUME_LINEAR_ZC,
 128         SOF_VOLUME_LOG_ZC,
 129 };
 130
 131 /* generic volume component */
 132 struct sof_ipc_comp_volume {
 133         struct sof_ipc_comp comp;
 134         struct sof_ipc_comp_config config;
 135         uint32_t channels;
 136         uint32_t min_value;
 137         uint32_t max_value;
 138         uint32_t ramp;          /**< SOF_VOLUME_ */
 139         uint32_t initial_ramp;  /**< ramp space in ms */
 140 }  __packed;
 141
 142 /* generic SRC component */
 143 struct sof_ipc_comp_src {
 144         struct sof_ipc_comp comp;
 145         struct sof_ipc_comp_config config;
 146         /* either source or sink rate must be non zero */
 147         uint32_t source_rate;   /**< source rate or 0 for variable */
 148         uint32_t sink_rate;     /**< sink rate or 0 for variable */
 149         uint32_t rate_mask;     /**< SOF_RATE_ supported rates */
 150 } __packed;
 151
 152 /* generic ASRC component */
 153 struct sof_ipc_comp_asrc {
 154         struct sof_ipc_comp comp;
 155         struct sof_ipc_comp_config config;
 156         /* either source or sink rate must be non zero */
 157         uint32_t source_rate;           /**< Define fixed source rate or */
 158                                         /**< use 0 to indicate need to get */
 159                                         /**< the rate from stream */
 160         uint32_t sink_rate;             /**< Define fixed sink rate or */
 161                                         /**< use 0 to indicate need to get */
 162                                         /**< the rate from stream */
 163         uint32_t asynchronous_mode;     /**< synchronous 0, asynchronous 1 */
 164                                         /**< When 1 the ASRC tracks and */
 165                                         /**< compensates for drift. */
 166         uint32_t operation_mode;        /**< push 0, pull 1, In push mode the */
 167                                         /**< ASRC consumes a defined number */
 168                                         /**< of frames at input, with varying */
 169                                         /**< number of frames at output. */
 170                                         /**< In pull mode the ASRC outputs */
 171                                         /**< a defined number of frames while */
 172                                         /**< number of input frames varies. */
 173
 174         /* reserved for future use */
 175         uint32_t reserved[4];
 176 } __attribute__((packed));
 177
 178 /* generic MUX component */
 179 struct sof_ipc_comp_mux {
 180         struct sof_ipc_comp comp;
 181         struct sof_ipc_comp_config config;
 182 } __packed;
 183
 184 /* generic tone generator component */
 185 struct sof_ipc_comp_tone {
 186         struct sof_ipc_comp comp;
 187         struct sof_ipc_comp_config config;
 188         int32_t sample_rate;
 189         int32_t frequency;
 190         int32_t amplitude;
 191         int32_t freq_mult;
 192         int32_t ampl_mult;
 193         int32_t length;
 194         int32_t period;
 195         int32_t repeats;
 196         int32_t ramp_step;
 197 } __packed;
 198
 199 /** \brief Types of processing components */
 200 enum sof_ipc_process_type {
 201         SOF_PROCESS_NONE = 0,           /**< None */
 202         SOF_PROCESS_EQFIR,              /**< Intel FIR */
 203         SOF_PROCESS_EQIIR,              /**< Intel IIR */
 204         SOF_PROCESS_KEYWORD_DETECT,     /**< Keyword Detection */
 205         SOF_PROCESS_KPB,                /**< KeyPhrase Buffer Manager */
 206         SOF_PROCESS_CHAN_SELECTOR,      /**< Channel Selector */
 207         SOF_PROCESS_MUX,
 208         SOF_PROCESS_DEMUX,
 209 };
 210
 211 /* generic "effect", "codec" or proprietary processing component */
 212 struct sof_ipc_comp_process {
 213         struct sof_ipc_comp comp;
 214         struct sof_ipc_comp_config config;
 215         uint32_t size;  /**< size of bespoke data section in bytes */
 216         uint32_t type;  /**< sof_ipc_process_type */
 217
 218         /* reserved for future use */
 219         uint32_t reserved[7];
 220
 221         unsigned char data[0];
 222 } __packed;
 223
 224 /* frees components, buffers and pipelines
 225  * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
 226  */
 227 struct sof_ipc_free {
 228         struct sof_ipc_cmd_hdr hdr;
 229         uint32_t id;
 230 } __packed;
 231
 232 struct sof_ipc_comp_reply {
 233         struct sof_ipc_reply rhdr;
 234         uint32_t id;
 235         uint32_t offset;
 236 } __packed;
 237
 238 /*
 239  * Pipeline
 240  */
 241
 242 /** \brief Types of pipeline scheduling time domains */
 243 enum sof_ipc_pipe_sched_time_domain {
 244         SOF_TIME_DOMAIN_DMA = 0,        /**< DMA interrupt */
 245         SOF_TIME_DOMAIN_TIMER,          /**< Timer interrupt */
 246 };
 247
 248 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
 249 struct sof_ipc_pipe_new {
 250         struct sof_ipc_cmd_hdr hdr;
 251         uint32_t comp_id;       /**< component id for pipeline */
 252         uint32_t pipeline_id;   /**< pipeline id */
 253         uint32_t sched_id;      /**< Scheduling component id */
 254         uint32_t core;          /**< core we run on */
 255         uint32_t period;        /**< execution period in us*/
 256         uint32_t priority;      /**< priority level 0 (low) to 10 (max) */
 257         uint32_t period_mips;   /**< worst case instruction count per period */
 258         uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
 259         uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
 260         uint32_t time_domain;   /**< scheduling time domain */
 261 }  __packed;
 262
 263 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
 264 struct sof_ipc_pipe_ready {
 265         struct sof_ipc_cmd_hdr hdr;
 266         uint32_t comp_id;
 267 }  __packed;
 268
 269 struct sof_ipc_pipe_free {
 270         struct sof_ipc_cmd_hdr hdr;
 271         uint32_t comp_id;
 272 }  __packed;
 273
 274 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
 275 struct sof_ipc_pipe_comp_connect {
 276         struct sof_ipc_cmd_hdr hdr;
 277         uint32_t source_id;
 278         uint32_t sink_id;
 279 }  __packed;
 280
 281 /* external events */
 282 enum sof_event_types {
 283         SOF_EVENT_NONE = 0,
 284         SOF_KEYWORD_DETECT_DAPM_EVENT,
 285 };
 286
 287 #endif