2 * Permission is hereby granted, free of charge, to any person obtaining a copy
3 * of this software and associated documentation files (the "Software"), to
4 * deal in the Software without restriction, including without limitation the
5 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
6 * sell copies of the Software, and to permit persons to whom the Software is
7 * furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
15 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
16 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
17 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
18 * DEALINGS IN THE SOFTWARE.
20 * Copyright (c) 2015, Roger Pau Monne <roger.pau@citrix.com>
23 #ifndef __XEN_PUBLIC_HVM_HVM_VCPU_H__
24 #define __XEN_PUBLIC_HVM_HVM_VCPU_H__
28 struct vcpu_hvm_x86_32
{
47 * EFER should only be used to set the NXE bit (if required)
48 * when starting a vCPU in 32bit mode with paging enabled or
49 * to set the LME/LMA bits in order to start the vCPU in
74 * The layout of the _ar fields of the segment registers is the
77 * Bits [0,3]: type (bits 40-43).
78 * Bit 4: s (descriptor type, bit 44).
79 * Bit [5,6]: dpl (descriptor privilege level, bits 45-46).
80 * Bit 7: p (segment-present, bit 47).
81 * Bit 8: avl (available for system software, bit 52).
82 * Bit 9: l (64-bit code segment, bit 53).
83 * Bit 10: db (meaning depends on the segment, bit 54).
84 * Bit 11: g (granularity, bit 55)
85 * Bits [12,15]: unused, must be blank.
87 * A more complete description of the meaning of this fields can be
88 * obtained from the Intel SDM, Volume 3, section 3.4.5.
91 struct vcpu_hvm_x86_64
{
109 * Using VCPU_HVM_MODE_64B implies that the vCPU is launched
110 * directly in long mode, so the cached parts of the segment
111 * registers get set to match that environment.
113 * If the user wants to launch the vCPU in compatibility mode
114 * the 32-bit structure should be used instead.
118 struct vcpu_hvm_context
{
119 #define VCPU_HVM_MODE_32B 0 /* 32bit fields of the structure will be used. */
120 #define VCPU_HVM_MODE_64B 1 /* 64bit fields of the structure will be used. */
127 struct vcpu_hvm_x86_32 x86_32
;
128 struct vcpu_hvm_x86_64 x86_64
;
131 typedef struct vcpu_hvm_context vcpu_hvm_context_t
;
133 #endif /* __XEN_PUBLIC_HVM_HVM_VCPU_H__ */
138 * c-file-style: "BSD"
141 * indent-tabs-mode: nil