RDMA/rtrs: server: Fix some error return code
[linux/fpc-iii.git] / include / xen / interface / physdev.h
blob610dba9b620acdad3f5f9410c01a6d992bb5385b
1 /*
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3 * of this software and associated documentation files (the "Software"), to
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6 * sell copies of the Software, and to permit persons to whom the Software is
7 * furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
15 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
16 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
17 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
18 * DEALINGS IN THE SOFTWARE.
21 #ifndef __XEN_PUBLIC_PHYSDEV_H__
22 #define __XEN_PUBLIC_PHYSDEV_H__
25 * Prototype for this hypercall is:
26 * int physdev_op(int cmd, void *args)
27 * @cmd == PHYSDEVOP_??? (physdev operation).
28 * @args == Operation-specific extra arguments (NULL if none).
32 * Notify end-of-interrupt (EOI) for the specified IRQ.
33 * @arg == pointer to physdev_eoi structure.
35 #define PHYSDEVOP_eoi 12
36 struct physdev_eoi {
37 /* IN */
38 uint32_t irq;
42 * Register a shared page for the hypervisor to indicate whether the guest
43 * must issue PHYSDEVOP_eoi. The semantics of PHYSDEVOP_eoi change slightly
44 * once the guest used this function in that the associated event channel
45 * will automatically get unmasked. The page registered is used as a bit
46 * array indexed by Xen's PIRQ value.
48 #define PHYSDEVOP_pirq_eoi_gmfn_v1 17
50 * Register a shared page for the hypervisor to indicate whether the
51 * guest must issue PHYSDEVOP_eoi. This hypercall is very similar to
52 * PHYSDEVOP_pirq_eoi_gmfn_v1 but it doesn't change the semantics of
53 * PHYSDEVOP_eoi. The page registered is used as a bit array indexed by
54 * Xen's PIRQ value.
56 #define PHYSDEVOP_pirq_eoi_gmfn_v2 28
57 struct physdev_pirq_eoi_gmfn {
58 /* IN */
59 xen_ulong_t gmfn;
63 * Query the status of an IRQ line.
64 * @arg == pointer to physdev_irq_status_query structure.
66 #define PHYSDEVOP_irq_status_query 5
67 struct physdev_irq_status_query {
68 /* IN */
69 uint32_t irq;
70 /* OUT */
71 uint32_t flags; /* XENIRQSTAT_* */
74 /* Need to call PHYSDEVOP_eoi when the IRQ has been serviced? */
75 #define _XENIRQSTAT_needs_eoi (0)
76 #define XENIRQSTAT_needs_eoi (1U<<_XENIRQSTAT_needs_eoi)
78 /* IRQ shared by multiple guests? */
79 #define _XENIRQSTAT_shared (1)
80 #define XENIRQSTAT_shared (1U<<_XENIRQSTAT_shared)
83 * Set the current VCPU's I/O privilege level.
84 * @arg == pointer to physdev_set_iopl structure.
86 #define PHYSDEVOP_set_iopl 6
87 struct physdev_set_iopl {
88 /* IN */
89 uint32_t iopl;
93 * Set the current VCPU's I/O-port permissions bitmap.
94 * @arg == pointer to physdev_set_iobitmap structure.
96 #define PHYSDEVOP_set_iobitmap 7
97 struct physdev_set_iobitmap {
98 /* IN */
99 uint8_t * bitmap;
100 uint32_t nr_ports;
104 * Read or write an IO-APIC register.
105 * @arg == pointer to physdev_apic structure.
107 #define PHYSDEVOP_apic_read 8
108 #define PHYSDEVOP_apic_write 9
109 struct physdev_apic {
110 /* IN */
111 unsigned long apic_physbase;
112 uint32_t reg;
113 /* IN or OUT */
114 uint32_t value;
118 * Allocate or free a physical upcall vector for the specified IRQ line.
119 * @arg == pointer to physdev_irq structure.
121 #define PHYSDEVOP_alloc_irq_vector 10
122 #define PHYSDEVOP_free_irq_vector 11
123 struct physdev_irq {
124 /* IN */
125 uint32_t irq;
126 /* IN or OUT */
127 uint32_t vector;
130 #define MAP_PIRQ_TYPE_MSI 0x0
131 #define MAP_PIRQ_TYPE_GSI 0x1
132 #define MAP_PIRQ_TYPE_UNKNOWN 0x2
133 #define MAP_PIRQ_TYPE_MSI_SEG 0x3
134 #define MAP_PIRQ_TYPE_MULTI_MSI 0x4
136 #define PHYSDEVOP_map_pirq 13
137 struct physdev_map_pirq {
138 domid_t domid;
139 /* IN */
140 int type;
141 /* IN */
142 int index;
143 /* IN or OUT */
144 int pirq;
145 /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
146 int bus;
147 /* IN */
148 int devfn;
149 /* IN
150 * - For MSI-X contains entry number.
151 * - For MSI with ..._MULTI_MSI contains number of vectors.
152 * OUT (..._MULTI_MSI only)
153 * - Number of vectors allocated.
155 int entry_nr;
156 /* IN */
157 uint64_t table_base;
160 #define PHYSDEVOP_unmap_pirq 14
161 struct physdev_unmap_pirq {
162 domid_t domid;
163 /* IN */
164 int pirq;
167 #define PHYSDEVOP_manage_pci_add 15
168 #define PHYSDEVOP_manage_pci_remove 16
169 struct physdev_manage_pci {
170 /* IN */
171 uint8_t bus;
172 uint8_t devfn;
175 #define PHYSDEVOP_restore_msi 19
176 struct physdev_restore_msi {
177 /* IN */
178 uint8_t bus;
179 uint8_t devfn;
182 #define PHYSDEVOP_manage_pci_add_ext 20
183 struct physdev_manage_pci_ext {
184 /* IN */
185 uint8_t bus;
186 uint8_t devfn;
187 unsigned is_extfn;
188 unsigned is_virtfn;
189 struct {
190 uint8_t bus;
191 uint8_t devfn;
192 } physfn;
196 * Argument to physdev_op_compat() hypercall. Superceded by new physdev_op()
197 * hypercall since 0x00030202.
199 struct physdev_op {
200 uint32_t cmd;
201 union {
202 struct physdev_irq_status_query irq_status_query;
203 struct physdev_set_iopl set_iopl;
204 struct physdev_set_iobitmap set_iobitmap;
205 struct physdev_apic apic_op;
206 struct physdev_irq irq_op;
207 } u;
210 #define PHYSDEVOP_setup_gsi 21
211 struct physdev_setup_gsi {
212 int gsi;
213 /* IN */
214 uint8_t triggering;
215 /* IN */
216 uint8_t polarity;
217 /* IN */
220 #define PHYSDEVOP_get_nr_pirqs 22
221 struct physdev_nr_pirqs {
222 /* OUT */
223 uint32_t nr_pirqs;
226 /* type is MAP_PIRQ_TYPE_GSI or MAP_PIRQ_TYPE_MSI
227 * the hypercall returns a free pirq */
228 #define PHYSDEVOP_get_free_pirq 23
229 struct physdev_get_free_pirq {
230 /* IN */
231 int type;
232 /* OUT */
233 uint32_t pirq;
236 #define XEN_PCI_DEV_EXTFN 0x1
237 #define XEN_PCI_DEV_VIRTFN 0x2
238 #define XEN_PCI_DEV_PXM 0x4
240 #define XEN_PCI_MMCFG_RESERVED 0x1
242 #define PHYSDEVOP_pci_mmcfg_reserved 24
243 struct physdev_pci_mmcfg_reserved {
244 uint64_t address;
245 uint16_t segment;
246 uint8_t start_bus;
247 uint8_t end_bus;
248 uint32_t flags;
251 #define PHYSDEVOP_pci_device_add 25
252 struct physdev_pci_device_add {
253 /* IN */
254 uint16_t seg;
255 uint8_t bus;
256 uint8_t devfn;
257 uint32_t flags;
258 struct {
259 uint8_t bus;
260 uint8_t devfn;
261 } physfn;
262 #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
263 uint32_t optarr[];
264 #elif defined(__GNUC__)
265 uint32_t optarr[0];
266 #endif
269 #define PHYSDEVOP_pci_device_remove 26
270 #define PHYSDEVOP_restore_msi_ext 27
272 * Dom0 should use these two to announce MMIO resources assigned to
273 * MSI-X capable devices won't (prepare) or may (release) change.
275 #define PHYSDEVOP_prepare_msix 30
276 #define PHYSDEVOP_release_msix 31
277 struct physdev_pci_device {
278 /* IN */
279 uint16_t seg;
280 uint8_t bus;
281 uint8_t devfn;
284 #define PHYSDEVOP_DBGP_RESET_PREPARE 1
285 #define PHYSDEVOP_DBGP_RESET_DONE 2
287 #define PHYSDEVOP_DBGP_BUS_UNKNOWN 0
288 #define PHYSDEVOP_DBGP_BUS_PCI 1
290 #define PHYSDEVOP_dbgp_op 29
291 struct physdev_dbgp_op {
292 /* IN */
293 uint8_t op;
294 uint8_t bus;
295 union {
296 struct physdev_pci_device pci;
297 } u;
301 * Notify that some PIRQ-bound event channels have been unmasked.
302 * ** This command is obsolete since interface version 0x00030202 and is **
303 * ** unsupported by newer versions of Xen. **
305 #define PHYSDEVOP_IRQ_UNMASK_NOTIFY 4
308 * These all-capitals physdev operation names are superceded by the new names
309 * (defined above) since interface version 0x00030202.
311 #define PHYSDEVOP_IRQ_STATUS_QUERY PHYSDEVOP_irq_status_query
312 #define PHYSDEVOP_SET_IOPL PHYSDEVOP_set_iopl
313 #define PHYSDEVOP_SET_IOBITMAP PHYSDEVOP_set_iobitmap
314 #define PHYSDEVOP_APIC_READ PHYSDEVOP_apic_read
315 #define PHYSDEVOP_APIC_WRITE PHYSDEVOP_apic_write
316 #define PHYSDEVOP_ASSIGN_VECTOR PHYSDEVOP_alloc_irq_vector
317 #define PHYSDEVOP_FREE_VECTOR PHYSDEVOP_free_irq_vector
318 #define PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY XENIRQSTAT_needs_eoi
319 #define PHYSDEVOP_IRQ_SHARED XENIRQSTAT_shared
321 #endif /* __XEN_PUBLIC_PHYSDEV_H__ */