drivers/usb/phy/phy-omap-usb3.c

   1 /*
   2  * omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/usb/omap_usb.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/delay.h>
  28 #include <linux/usb/omap_control_usb.h>
  29
  30 #define PLL_STATUS              0x00000004
  31 #define PLL_GO                  0x00000008
  32 #define PLL_CONFIGURATION1      0x0000000C
  33 #define PLL_CONFIGURATION2      0x00000010
  34 #define PLL_CONFIGURATION3      0x00000014
  35 #define PLL_CONFIGURATION4      0x00000020
  36
  37 #define PLL_REGM_MASK           0x001FFE00
  38 #define PLL_REGM_SHIFT          0x9
  39 #define PLL_REGM_F_MASK         0x0003FFFF
  40 #define PLL_REGM_F_SHIFT        0x0
  41 #define PLL_REGN_MASK           0x000001FE
  42 #define PLL_REGN_SHIFT          0x1
  43 #define PLL_SELFREQDCO_MASK     0x0000000E
  44 #define PLL_SELFREQDCO_SHIFT    0x1
  45 #define PLL_SD_MASK             0x0003FC00
  46 #define PLL_SD_SHIFT            0x9
  47 #define SET_PLL_GO              0x1
  48 #define PLL_TICOPWDN            0x10000
  49 #define PLL_LOCK                0x2
  50 #define PLL_IDLE                0x1
  51
  52 /*
  53  * This is an Empirical value that works, need to confirm the actual
  54  * value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
  55  * to be correctly reflected in the USB3PHY_PLL_STATUS register.
  56  */
  57 # define PLL_IDLE_TIME  100;
  58
  59 struct usb_dpll_map {
  60         unsigned long rate;
  61         struct usb_dpll_params params;
  62 };
  63
  64 static struct usb_dpll_map dpll_map[] = {
  65         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
  66         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
  67         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
  68         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
  69         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
  70         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
  71 };
  72
  73 static struct usb_dpll_params *omap_usb3_get_dpll_params(unsigned long rate)
  74 {
  75         int i;
  76
  77         for (i = 0; i < ARRAY_SIZE(dpll_map); i++) {
  78                 if (rate == dpll_map[i].rate)
  79                         return &dpll_map[i].params;
  80         }
  81
  82         return 0;
  83 }
  84
  85 static int omap_usb3_suspend(struct usb_phy *x, int suspend)
  86 {
  87         struct omap_usb *phy = phy_to_omapusb(x);
  88         int     val;
  89         int timeout = PLL_IDLE_TIME;
  90
  91         if (suspend && !phy->is_suspended) {
  92                 val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  93                 val |= PLL_IDLE;
  94                 omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  95
  96                 do {
  97                         val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
  98                         if (val & PLL_TICOPWDN)
  99                                 break;
 100                         udelay(1);
 101                 } while (--timeout);
 102
 103                 omap_control_usb3_phy_power(phy->control_dev, 0);
 104
 105                 phy->is_suspended       = 1;
 106         } else if (!suspend && phy->is_suspended) {
 107                 phy->is_suspended       = 0;
 108
 109                 val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 110                 val &= ~PLL_IDLE;
 111                 omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 112
 113                 do {
 114                         val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
 115                         if (!(val & PLL_TICOPWDN))
 116                                 break;
 117                         udelay(1);
 118                 } while (--timeout);
 119         }
 120
 121         return 0;
 122 }
 123
 124 static void omap_usb_dpll_relock(struct omap_usb *phy)
 125 {
 126         u32             val;
 127         unsigned long   timeout;
 128
 129         omap_usb_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 130
 131         timeout = jiffies + msecs_to_jiffies(20);
 132         do {
 133                 val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
 134                 if (val & PLL_LOCK)
 135                         break;
 136         } while (!WARN_ON(time_after(jiffies, timeout)));
 137 }
 138
 139 static int omap_usb_dpll_lock(struct omap_usb *phy)
 140 {
 141         u32                     val;
 142         unsigned long           rate;
 143         struct usb_dpll_params *dpll_params;
 144
 145         rate = clk_get_rate(phy->sys_clk);
 146         dpll_params = omap_usb3_get_dpll_params(rate);
 147         if (!dpll_params) {
 148                 dev_err(phy->dev,
 149                           "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 150                 return -EINVAL;
 151         }
 152
 153         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 154         val &= ~PLL_REGN_MASK;
 155         val |= dpll_params->n << PLL_REGN_SHIFT;
 156         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 157
 158         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 159         val &= ~PLL_SELFREQDCO_MASK;
 160         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 161         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 162
 163         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 164         val &= ~PLL_REGM_MASK;
 165         val |= dpll_params->m << PLL_REGM_SHIFT;
 166         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 167
 168         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 169         val &= ~PLL_REGM_F_MASK;
 170         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 171         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 172
 173         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 174         val &= ~PLL_SD_MASK;
 175         val |= dpll_params->sd << PLL_SD_SHIFT;
 176         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 177
 178         omap_usb_dpll_relock(phy);
 179
 180         return 0;
 181 }
 182
 183 static int omap_usb3_init(struct usb_phy *x)
 184 {
 185         struct omap_usb *phy = phy_to_omapusb(x);
 186         int ret;
 187
 188         ret = omap_usb_dpll_lock(phy);
 189         if (ret)
 190                 return ret;
 191
 192         omap_control_usb3_phy_power(phy->control_dev, 1);
 193
 194         return 0;
 195 }
 196
 197 static int omap_usb3_probe(struct platform_device *pdev)
 198 {
 199         struct omap_usb                 *phy;
 200         struct resource                 *res;
 201
 202         phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
 203         if (!phy) {
 204                 dev_err(&pdev->dev, "unable to alloc mem for OMAP USB3 PHY\n");
 205                 return -ENOMEM;
 206         }
 207
 208         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
 209         phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
 210         if (IS_ERR(phy->pll_ctrl_base))
 211                 return PTR_ERR(phy->pll_ctrl_base);
 212
 213         phy->dev                = &pdev->dev;
 214
 215         phy->phy.dev            = phy->dev;
 216         phy->phy.label          = "omap-usb3";
 217         phy->phy.init           = omap_usb3_init;
 218         phy->phy.set_suspend    = omap_usb3_suspend;
 219         phy->phy.type           = USB_PHY_TYPE_USB3;
 220
 221         phy->is_suspended       = 1;
 222         phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
 223         if (IS_ERR(phy->wkupclk)) {
 224                 dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
 225                 return PTR_ERR(phy->wkupclk);
 226         }
 227         clk_prepare(phy->wkupclk);
 228
 229         phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
 230         if (IS_ERR(phy->optclk)) {
 231                 dev_err(&pdev->dev, "unable to get usb_otg_ss_refclk960m\n");
 232                 return PTR_ERR(phy->optclk);
 233         }
 234         clk_prepare(phy->optclk);
 235
 236         phy->sys_clk = devm_clk_get(phy->dev, "sys_clkin");
 237         if (IS_ERR(phy->sys_clk)) {
 238                 pr_err("%s: unable to get sys_clkin\n", __func__);
 239                 return -EINVAL;
 240         }
 241
 242         phy->control_dev = omap_get_control_dev();
 243         if (IS_ERR(phy->control_dev)) {
 244                 dev_dbg(&pdev->dev, "Failed to get control device\n");
 245                 return -ENODEV;
 246         }
 247
 248         omap_control_usb3_phy_power(phy->control_dev, 0);
 249         usb_add_phy_dev(&phy->phy);
 250
 251         platform_set_drvdata(pdev, phy);
 252
 253         pm_runtime_enable(phy->dev);
 254         pm_runtime_get(&pdev->dev);
 255
 256         return 0;
 257 }
 258
 259 static int omap_usb3_remove(struct platform_device *pdev)
 260 {
 261         struct omap_usb *phy = platform_get_drvdata(pdev);
 262
 263         clk_unprepare(phy->wkupclk);
 264         clk_unprepare(phy->optclk);
 265         usb_remove_phy(&phy->phy);
 266         if (!pm_runtime_suspended(&pdev->dev))
 267                 pm_runtime_put(&pdev->dev);
 268         pm_runtime_disable(&pdev->dev);
 269
 270         return 0;
 271 }
 272
 273 #ifdef CONFIG_PM_RUNTIME
 274
 275 static int omap_usb3_runtime_suspend(struct device *dev)
 276 {
 277         struct platform_device  *pdev = to_platform_device(dev);
 278         struct omap_usb *phy = platform_get_drvdata(pdev);
 279
 280         clk_disable(phy->wkupclk);
 281         clk_disable(phy->optclk);
 282
 283         return 0;
 284 }
 285
 286 static int omap_usb3_runtime_resume(struct device *dev)
 287 {
 288         u32 ret = 0;
 289         struct platform_device  *pdev = to_platform_device(dev);
 290         struct omap_usb *phy = platform_get_drvdata(pdev);
 291
 292         ret = clk_enable(phy->optclk);
 293         if (ret) {
 294                 dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
 295                 goto err1;
 296         }
 297
 298         ret = clk_enable(phy->wkupclk);
 299         if (ret) {
 300                 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 301                 goto err2;
 302         }
 303
 304         return 0;
 305
 306 err2:
 307         clk_disable(phy->optclk);
 308
 309 err1:
 310         return ret;
 311 }
 312
 313 static const struct dev_pm_ops omap_usb3_pm_ops = {
 314         SET_RUNTIME_PM_OPS(omap_usb3_runtime_suspend, omap_usb3_runtime_resume,
 315                 NULL)
 316 };
 317
 318 #define DEV_PM_OPS     (&omap_usb3_pm_ops)
 319 #else
 320 #define DEV_PM_OPS     NULL
 321 #endif
 322
 323 #ifdef CONFIG_OF
 324 static const struct of_device_id omap_usb3_id_table[] = {
 325         { .compatible = "ti,omap-usb3" },
 326         {}
 327 };
 328 MODULE_DEVICE_TABLE(of, omap_usb3_id_table);
 329 #endif
 330
 331 static struct platform_driver omap_usb3_driver = {
 332         .probe          = omap_usb3_probe,
 333         .remove         = omap_usb3_remove,
 334         .driver         = {
 335                 .name   = "omap-usb3",
 336                 .owner  = THIS_MODULE,
 337                 .pm     = DEV_PM_OPS,
 338                 .of_match_table = of_match_ptr(omap_usb3_id_table),
 339         },
 340 };
 341
 342 module_platform_driver(omap_usb3_driver);
 343
 344 MODULE_ALIAS("platform: omap_usb3");
 345 MODULE_AUTHOR("Texas Instruments Inc.");
 346 MODULE_DESCRIPTION("OMAP USB3 phy driver");
 347 MODULE_LICENSE("GPL v2");