Documentation/arm64/memory.txt

   1                      Memory Layout on AArch64 Linux
   2                      ==============================
   3
   4 Author: Catalin Marinas <catalin.marinas@arm.com>
   5
   6 This document describes the virtual memory layout used by the AArch64
   7 Linux kernel. The architecture allows up to 4 levels of translation
   8 tables with a 4KB page size and up to 3 levels with a 64KB page size.
   9
  10 AArch64 Linux uses either 3 levels or 4 levels of translation tables
  11 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
  12 (256TB) virtual addresses, respectively, for both user and kernel. With
  13 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
  14 virtual address, are used but the memory layout is the same.
  15
  16 User addresses have bits 63:48 set to 0 while the kernel addresses have
  17 the same bits set to 1. TTBRx selection is given by bit 63 of the
  18 virtual address. The swapper_pg_dir contains only kernel (global)
  19 mappings while the user pgd contains only user (non-global) mappings.
  20 The swapper_pg_dir address is written to TTBR1 and never written to
  21 TTBR0.
  22
  23
  24 AArch64 Linux memory layout with 4KB pages + 3 levels:
  25
  26 Start                   End                     Size            Use
  27 -----------------------------------------------------------------------
  28 0000000000000000        0000007fffffffff         512GB          user
  29 ffffff8000000000        ffffffffffffffff         512GB          kernel
  30
  31
  32 AArch64 Linux memory layout with 4KB pages + 4 levels:
  33
  34 Start                   End                     Size            Use
  35 -----------------------------------------------------------------------
  36 0000000000000000        0000ffffffffffff         256TB          user
  37 ffff000000000000        ffffffffffffffff         256TB          kernel
  38
  39
  40 AArch64 Linux memory layout with 64KB pages + 2 levels:
  41
  42 Start                   End                     Size            Use
  43 -----------------------------------------------------------------------
  44 0000000000000000        000003ffffffffff           4TB          user
  45 fffffc0000000000        ffffffffffffffff           4TB          kernel
  46
  47
  48 AArch64 Linux memory layout with 64KB pages + 3 levels:
  49
  50 Start                   End                     Size            Use
  51 -----------------------------------------------------------------------
  52 0000000000000000        0000ffffffffffff         256TB          user
  53 ffff000000000000        ffffffffffffffff         256TB          kernel
  54
  55
  56 For details of the virtual kernel memory layout please see the kernel
  57 booting log.
  58
  59
  60 Translation table lookup with 4KB pages:
  61
  62 +--------+--------+--------+--------+--------+--------+--------+--------+
  63 |63    56|55    48|47    40|39    32|31    24|23    16|15     8|7      0|
  64 +--------+--------+--------+--------+--------+--------+--------+--------+
  65  |                 |         |         |         |         |
  66  |                 |         |         |         |         v
  67  |                 |         |         |         |   [11:0]  in-page offset
  68  |                 |         |         |         +-> [20:12] L3 index
  69  |                 |         |         +-----------> [29:21] L2 index
  70  |                 |         +---------------------> [38:30] L1 index
  71  |                 +-------------------------------> [47:39] L0 index
  72  +-------------------------------------------------> [63] TTBR0/1
  73
  74
  75 Translation table lookup with 64KB pages:
  76
  77 +--------+--------+--------+--------+--------+--------+--------+--------+
  78 |63    56|55    48|47    40|39    32|31    24|23    16|15     8|7      0|
  79 +--------+--------+--------+--------+--------+--------+--------+--------+
  80  |                 |    |               |              |
  81  |                 |    |               |              v
  82  |                 |    |               |            [15:0]  in-page offset
  83  |                 |    |               +----------> [28:16] L3 index
  84  |                 |    +--------------------------> [41:29] L2 index
  85  |                 +-------------------------------> [47:42] L1 index
  86  +-------------------------------------------------> [63] TTBR0/1
  87
  88
  89 When using KVM without the Virtualization Host Extensions, the
  90 hypervisor maps kernel pages in EL2 at a fixed (and potentially
  91 random) offset from the linear mapping. See the kern_hyp_va macro and
  92 kvm_update_va_mask function for more details. MMIO devices such as
  93 GICv2 gets mapped next to the HYP idmap page, as do vectors when
  94 ARM64_HARDEN_EL2_VECTORS is selected for particular CPUs.
  95
  96 When using KVM with the Virtualization Host Extensions, no additional
  97 mappings are created, since the host kernel runs directly in EL2.