drivers/gpu/drm/exynos/exynos_dp_core.h

   1 /*
   2  * Header file for Samsung DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #ifndef _EXYNOS_DP_CORE_H
  14 #define _EXYNOS_DP_CORE_H
  15
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_dp_helper.h>
  18 #include <drm/exynos_drm.h>
  19
  20 #define DP_TIMEOUT_LOOP_COUNT 100
  21 #define MAX_CR_LOOP 5
  22 #define MAX_EQ_LOOP 5
  23
  24 enum link_rate_type {
  25         LINK_RATE_1_62GBPS = 0x06,
  26         LINK_RATE_2_70GBPS = 0x0a
  27 };
  28
  29 enum link_lane_count_type {
  30         LANE_COUNT1 = 1,
  31         LANE_COUNT2 = 2,
  32         LANE_COUNT4 = 4
  33 };
  34
  35 enum link_training_state {
  36         START,
  37         CLOCK_RECOVERY,
  38         EQUALIZER_TRAINING,
  39         FINISHED,
  40         FAILED
  41 };
  42
  43 enum voltage_swing_level {
  44         VOLTAGE_LEVEL_0,
  45         VOLTAGE_LEVEL_1,
  46         VOLTAGE_LEVEL_2,
  47         VOLTAGE_LEVEL_3,
  48 };
  49
  50 enum pre_emphasis_level {
  51         PRE_EMPHASIS_LEVEL_0,
  52         PRE_EMPHASIS_LEVEL_1,
  53         PRE_EMPHASIS_LEVEL_2,
  54         PRE_EMPHASIS_LEVEL_3,
  55 };
  56
  57 enum pattern_set {
  58         PRBS7,
  59         D10_2,
  60         TRAINING_PTN1,
  61         TRAINING_PTN2,
  62         DP_NONE
  63 };
  64
  65 enum color_space {
  66         COLOR_RGB,
  67         COLOR_YCBCR422,
  68         COLOR_YCBCR444
  69 };
  70
  71 enum color_depth {
  72         COLOR_6,
  73         COLOR_8,
  74         COLOR_10,
  75         COLOR_12
  76 };
  77
  78 enum color_coefficient {
  79         COLOR_YCBCR601,
  80         COLOR_YCBCR709
  81 };
  82
  83 enum dynamic_range {
  84         VESA,
  85         CEA
  86 };
  87
  88 enum pll_status {
  89         PLL_UNLOCKED,
  90         PLL_LOCKED
  91 };
  92
  93 enum clock_recovery_m_value_type {
  94         CALCULATED_M,
  95         REGISTER_M
  96 };
  97
  98 enum video_timing_recognition_type {
  99         VIDEO_TIMING_FROM_CAPTURE,
 100         VIDEO_TIMING_FROM_REGISTER
 101 };
 102
 103 enum analog_power_block {
 104         AUX_BLOCK,
 105         CH0_BLOCK,
 106         CH1_BLOCK,
 107         CH2_BLOCK,
 108         CH3_BLOCK,
 109         ANALOG_TOTAL,
 110         POWER_ALL
 111 };
 112
 113 enum dp_irq_type {
 114         DP_IRQ_TYPE_HP_CABLE_IN,
 115         DP_IRQ_TYPE_HP_CABLE_OUT,
 116         DP_IRQ_TYPE_HP_CHANGE,
 117         DP_IRQ_TYPE_UNKNOWN,
 118 };
 119
 120 struct video_info {
 121         char *name;
 122
 123         bool h_sync_polarity;
 124         bool v_sync_polarity;
 125         bool interlaced;
 126
 127         enum color_space color_space;
 128         enum dynamic_range dynamic_range;
 129         enum color_coefficient ycbcr_coeff;
 130         enum color_depth color_depth;
 131
 132         enum link_rate_type link_rate;
 133         enum link_lane_count_type lane_count;
 134 };
 135
 136 struct link_train {
 137         int eq_loop;
 138         int cr_loop[4];
 139
 140         u8 link_rate;
 141         u8 lane_count;
 142         u8 training_lane[4];
 143
 144         enum link_training_state lt_state;
 145 };
 146
 147 struct exynos_dp_device {
 148         struct device           *dev;
 149         struct drm_device       *drm_dev;
 150         struct drm_connector    connector;
 151         struct drm_encoder      *encoder;
 152         struct drm_panel        *panel;
 153         struct clk              *clock;
 154         unsigned int            irq;
 155         void __iomem            *reg_base;
 156         void __iomem            *phy_addr;
 157         unsigned int            enable_mask;
 158
 159         struct video_info       *video_info;
 160         struct link_train       link_train;
 161         struct work_struct      hotplug_work;
 162         struct phy              *phy;
 163         int                     dpms_mode;
 164         int                     hpd_gpio;
 165
 166         struct exynos_drm_panel_info priv;
 167 };
 168
 169 /* exynos_dp_reg.c */
 170 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
 171 void exynos_dp_stop_video(struct exynos_dp_device *dp);
 172 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
 173 void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
 174 void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
 175 void exynos_dp_reset(struct exynos_dp_device *dp);
 176 void exynos_dp_swreset(struct exynos_dp_device *dp);
 177 void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
 178 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
 179 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
 180 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 181                                 enum analog_power_block block,
 182                                 bool enable);
 183 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
 184 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
 185 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
 186 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
 187 void exynos_dp_reset_aux(struct exynos_dp_device *dp);
 188 void exynos_dp_init_aux(struct exynos_dp_device *dp);
 189 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
 190 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
 191 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
 192 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 193                                 unsigned int reg_addr,
 194                                 unsigned char data);
 195 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 196                                 unsigned int reg_addr,
 197                                 unsigned char *data);
 198 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 199                                 unsigned int reg_addr,
 200                                 unsigned int count,
 201                                 unsigned char data[]);
 202 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 203                                 unsigned int reg_addr,
 204                                 unsigned int count,
 205                                 unsigned char data[]);
 206 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 207                                 unsigned int device_addr,
 208                                 unsigned int reg_addr);
 209 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 210                                 unsigned int device_addr,
 211                                 unsigned int reg_addr,
 212                                 unsigned int *data);
 213 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 214                                 unsigned int device_addr,
 215                                 unsigned int reg_addr,
 216                                 unsigned int count,
 217                                 unsigned char edid[]);
 218 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
 219 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
 220 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
 221 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
 222 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
 223 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 224                                  enum pattern_set pattern);
 225 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 226 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 227 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 228 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 229 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 230                                 u32 training_lane);
 231 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 232                                 u32 training_lane);
 233 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 234                                 u32 training_lane);
 235 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 236                                 u32 training_lane);
 237 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
 238 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
 239 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
 240 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
 241 void exynos_dp_reset_macro(struct exynos_dp_device *dp);
 242 void exynos_dp_init_video(struct exynos_dp_device *dp);
 243
 244 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
 245 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
 246 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
 247                         enum clock_recovery_m_value_type type,
 248                         u32 m_value,
 249                         u32 n_value);
 250 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
 251 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
 252 void exynos_dp_start_video(struct exynos_dp_device *dp);
 253 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
 254 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
 255 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
 256 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
 257
 258 /* I2C EDID Chip ID, Slave Address */
 259 #define I2C_EDID_DEVICE_ADDR                    0x50
 260 #define I2C_E_EDID_DEVICE_ADDR                  0x30
 261
 262 #define EDID_BLOCK_LENGTH                       0x80
 263 #define EDID_HEADER_PATTERN                     0x00
 264 #define EDID_EXTENSION_FLAG                     0x7e
 265 #define EDID_CHECKSUM                           0x7f
 266
 267 /* DP_MAX_LANE_COUNT */
 268 #define DPCD_ENHANCED_FRAME_CAP(x)              (((x) >> 7) & 0x1)
 269 #define DPCD_MAX_LANE_COUNT(x)                  ((x) & 0x1f)
 270
 271 /* DP_LANE_COUNT_SET */
 272 #define DPCD_LANE_COUNT_SET(x)                  ((x) & 0x1f)
 273
 274 /* DP_TRAINING_LANE0_SET */
 275 #define DPCD_PRE_EMPHASIS_SET(x)                (((x) & 0x3) << 3)
 276 #define DPCD_PRE_EMPHASIS_GET(x)                (((x) >> 3) & 0x3)
 277 #define DPCD_VOLTAGE_SWING_SET(x)               (((x) & 0x3) << 0)
 278 #define DPCD_VOLTAGE_SWING_GET(x)               (((x) >> 0) & 0x3)
 279
 280 #endif /* _EXYNOS_DP_CORE_H */