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drm: powerpc can use a simpler drm_io_prot()
[linux/fpc-iii.git] / drivers / gpu / drm / exynos / exynos_drm_dsi.c
blob24741d8758e88521439f82309b656c35afa83785
1 /*
2 * Samsung SoC MIPI DSI Master driver.
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
5 *
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <drm/drmP.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_mipi_dsi.h>
16 #include <drm/drm_panel.h>
17
18 #include <linux/clk.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/irq.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/phy/phy.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/component.h>
26
27 #include <video/mipi_display.h>
28 #include <video/videomode.h>
29
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_drv.h"
32
33 /* returns true iff both arguments logically differs */
34 #define NEQV(a, b) (!(a) ^ !(b))
35
36 #define DSIM_STATUS_REG 0x0 /* Status register */
37 #define DSIM_SWRST_REG 0x4 /* Software reset register */
38 #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */
39 #define DSIM_TIMEOUT_REG 0xc /* Time out register */
40 #define DSIM_CONFIG_REG 0x10 /* Configuration register */
41 #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */
42
43 /* Main display image resolution register */
44 #define DSIM_MDRESOL_REG 0x18
45 #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */
46 #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */
47 #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */
48
49 /* Sub display image resolution register */
50 #define DSIM_SDRESOL_REG 0x28
51 #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */
52 #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */
53 #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */
54 #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */
55 #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */
56 #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */
57 #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */
58
59 /* FIFO memory AC characteristic register */
60 #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */
61 #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */
62 #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */
63 #define DSIM_PHYCTRL_REG 0x5c
64 #define DSIM_PHYTIMING_REG 0x64
65 #define DSIM_PHYTIMING1_REG 0x68
66 #define DSIM_PHYTIMING2_REG 0x6c
67
68 /* DSIM_STATUS */
69 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
70 #define DSIM_STOP_STATE_CLK (1 << 8)
71 #define DSIM_TX_READY_HS_CLK (1 << 10)
72 #define DSIM_PLL_STABLE (1 << 31)
73
74 /* DSIM_SWRST */
75 #define DSIM_FUNCRST (1 << 16)
76 #define DSIM_SWRST (1 << 0)
77
78 /* DSIM_TIMEOUT */
79 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
80 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
81
82 /* DSIM_CLKCTRL */
83 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
84 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
85 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
86 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
87 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
88 #define DSIM_BYTE_CLKEN (1 << 24)
89 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
90 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
91 #define DSIM_PLL_BYPASS (1 << 27)
92 #define DSIM_ESC_CLKEN (1 << 28)
93 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
94
95 /* DSIM_CONFIG */
96 #define DSIM_LANE_EN_CLK (1 << 0)
97 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
98 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
99 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
100 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
101 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
102 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
103 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
104 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
105 #define DSIM_SUB_VC (((x) & 0x3) << 16)
106 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
107 #define DSIM_HSA_MODE (1 << 20)
108 #define DSIM_HBP_MODE (1 << 21)
109 #define DSIM_HFP_MODE (1 << 22)
110 #define DSIM_HSE_MODE (1 << 23)
111 #define DSIM_AUTO_MODE (1 << 24)
112 #define DSIM_VIDEO_MODE (1 << 25)
113 #define DSIM_BURST_MODE (1 << 26)
114 #define DSIM_SYNC_INFORM (1 << 27)
115 #define DSIM_EOT_DISABLE (1 << 28)
116 #define DSIM_MFLUSH_VS (1 << 29)
117 /* This flag is valid only for exynos3250/3472/4415/5260/5430 */
118 #define DSIM_CLKLANE_STOP (1 << 30)
119
120 /* DSIM_ESCMODE */
121 #define DSIM_TX_TRIGGER_RST (1 << 4)
122 #define DSIM_TX_LPDT_LP (1 << 6)
123 #define DSIM_CMD_LPDT_LP (1 << 7)
124 #define DSIM_FORCE_BTA (1 << 16)
125 #define DSIM_FORCE_STOP_STATE (1 << 20)
126 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
127 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
128
129 /* DSIM_MDRESOL */
130 #define DSIM_MAIN_STAND_BY (1 << 31)
131 #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
132 #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
133
134 /* DSIM_MVPORCH */
135 #define DSIM_CMD_ALLOW(x) ((x) << 28)
136 #define DSIM_STABLE_VFP(x) ((x) << 16)
137 #define DSIM_MAIN_VBP(x) ((x) << 0)
138 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
139 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
140 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
141
142 /* DSIM_MHPORCH */
143 #define DSIM_MAIN_HFP(x) ((x) << 16)
144 #define DSIM_MAIN_HBP(x) ((x) << 0)
145 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
146 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
147
148 /* DSIM_MSYNC */
149 #define DSIM_MAIN_VSA(x) ((x) << 22)
150 #define DSIM_MAIN_HSA(x) ((x) << 0)
151 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
152 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
153
154 /* DSIM_SDRESOL */
155 #define DSIM_SUB_STANDY(x) ((x) << 31)
156 #define DSIM_SUB_VRESOL(x) ((x) << 16)
157 #define DSIM_SUB_HRESOL(x) ((x) << 0)
158 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
159 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
160 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
161
162 /* DSIM_INTSRC */
163 #define DSIM_INT_PLL_STABLE (1 << 31)
164 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
165 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
166 #define DSIM_INT_BTA (1 << 25)
167 #define DSIM_INT_FRAME_DONE (1 << 24)
168 #define DSIM_INT_RX_TIMEOUT (1 << 21)
169 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
170 #define DSIM_INT_RX_DONE (1 << 18)
171 #define DSIM_INT_RX_TE (1 << 17)
172 #define DSIM_INT_RX_ACK (1 << 16)
173 #define DSIM_INT_RX_ECC_ERR (1 << 15)
174 #define DSIM_INT_RX_CRC_ERR (1 << 14)
175
176 /* DSIM_FIFOCTRL */
177 #define DSIM_RX_DATA_FULL (1 << 25)
178 #define DSIM_RX_DATA_EMPTY (1 << 24)
179 #define DSIM_SFR_HEADER_FULL (1 << 23)
180 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
181 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
182 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
183 #define DSIM_I80_HEADER_FULL (1 << 19)
184 #define DSIM_I80_HEADER_EMPTY (1 << 18)
185 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
186 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
187 #define DSIM_SD_HEADER_FULL (1 << 15)
188 #define DSIM_SD_HEADER_EMPTY (1 << 14)
189 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
190 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
191 #define DSIM_MD_HEADER_FULL (1 << 11)
192 #define DSIM_MD_HEADER_EMPTY (1 << 10)
193 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
194 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
195 #define DSIM_RX_FIFO (1 << 4)
196 #define DSIM_SFR_FIFO (1 << 3)
197 #define DSIM_I80_FIFO (1 << 2)
198 #define DSIM_SD_FIFO (1 << 1)
199 #define DSIM_MD_FIFO (1 << 0)
200
201 /* DSIM_PHYACCHR */
202 #define DSIM_AFC_EN (1 << 14)
203 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
204
205 /* DSIM_PLLCTRL */
206 #define DSIM_FREQ_BAND(x) ((x) << 24)
207 #define DSIM_PLL_EN (1 << 23)
208 #define DSIM_PLL_P(x) ((x) << 13)
209 #define DSIM_PLL_M(x) ((x) << 4)
210 #define DSIM_PLL_S(x) ((x) << 1)
211
212 /* DSIM_PHYCTRL */
213 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
214
215 /* DSIM_PHYTIMING */
216 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
217 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
218
219 /* DSIM_PHYTIMING1 */
220 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
221 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
222 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
223 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
224
225 /* DSIM_PHYTIMING2 */
226 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
227 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
228 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
229
230 #define DSI_MAX_BUS_WIDTH 4
231 #define DSI_NUM_VIRTUAL_CHANNELS 4
232 #define DSI_TX_FIFO_SIZE 2048
233 #define DSI_RX_FIFO_SIZE 256
234 #define DSI_XFER_TIMEOUT_MS 100
235 #define DSI_RX_FIFO_EMPTY 0x30800002
236
237 enum exynos_dsi_transfer_type {
238 EXYNOS_DSI_TX,
239 EXYNOS_DSI_RX,
240 };
241
242 struct exynos_dsi_transfer {
243 struct list_head list;
244 struct completion completed;
245 int result;
246 u8 data_id;
247 u8 data[2];
248 u16 flags;
249
250 const u8 *tx_payload;
251 u16 tx_len;
252 u16 tx_done;
253
254 u8 *rx_payload;
255 u16 rx_len;
256 u16 rx_done;
257 };
258
259 #define DSIM_STATE_ENABLED BIT(0)
260 #define DSIM_STATE_INITIALIZED BIT(1)
261 #define DSIM_STATE_CMD_LPM BIT(2)
262
263 struct exynos_dsi_driver_data {
264 unsigned int plltmr_reg;
265
266 unsigned int has_freqband:1;
267 unsigned int has_clklane_stop:1;
268 };
269
270 struct exynos_dsi {
271 struct mipi_dsi_host dsi_host;
272 struct drm_connector connector;
273 struct drm_encoder *encoder;
274 struct device_node *panel_node;
275 struct drm_panel *panel;
276 struct device *dev;
277
278 void __iomem *reg_base;
279 struct phy *phy;
280 struct clk *pll_clk;
281 struct clk *bus_clk;
282 struct regulator_bulk_data supplies[2];
283 int irq;
284 int te_gpio;
285
286 u32 pll_clk_rate;
287 u32 burst_clk_rate;
288 u32 esc_clk_rate;
289 u32 lanes;
290 u32 mode_flags;
291 u32 format;
292 struct videomode vm;
293
294 int state;
295 struct drm_property *brightness;
296 struct completion completed;
297
298 spinlock_t transfer_lock; /* protects transfer_list */
299 struct list_head transfer_list;
300
301 struct exynos_dsi_driver_data *driver_data;
302 };
303
304 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
305 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
306
307 static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
308 .plltmr_reg = 0x50,
309 .has_freqband = 1,
310 .has_clklane_stop = 1,
311 };
312
313 static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
314 .plltmr_reg = 0x50,
315 .has_freqband = 1,
316 .has_clklane_stop = 1,
317 };
318
319 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
320 .plltmr_reg = 0x58,
321 };
322
323 static struct of_device_id exynos_dsi_of_match[] = {
324 { .compatible = "samsung,exynos3250-mipi-dsi",
325 .data = &exynos3_dsi_driver_data },
326 { .compatible = "samsung,exynos4210-mipi-dsi",
327 .data = &exynos4_dsi_driver_data },
328 { .compatible = "samsung,exynos5410-mipi-dsi",
329 .data = &exynos5_dsi_driver_data },
330 { }
331 };
332
333 static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
334 struct platform_device *pdev)
335 {
336 const struct of_device_id *of_id =
337 of_match_device(exynos_dsi_of_match, &pdev->dev);
338
339 return (struct exynos_dsi_driver_data *)of_id->data;
340 }
341
342 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
343 {
344 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
345 return;
346
347 dev_err(dsi->dev, "timeout waiting for reset\n");
348 }
349
350 static void exynos_dsi_reset(struct exynos_dsi *dsi)
351 {
352 reinit_completion(&dsi->completed);
353 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
354 }
355
356 #ifndef MHZ
357 #define MHZ (1000*1000)
358 #endif
359
360 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
361 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
362 {
363 unsigned long best_freq = 0;
364 u32 min_delta = 0xffffffff;
365 u8 p_min, p_max;
366 u8 _p, uninitialized_var(best_p);
367 u16 _m, uninitialized_var(best_m);
368 u8 _s, uninitialized_var(best_s);
369
370 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
371 p_max = fin / (6 * MHZ);
372
373 for (_p = p_min; _p <= p_max; ++_p) {
374 for (_s = 0; _s <= 5; ++_s) {
375 u64 tmp;
376 u32 delta;
377
378 tmp = (u64)fout * (_p << _s);
379 do_div(tmp, fin);
380 _m = tmp;
381 if (_m < 41 || _m > 125)
382 continue;
383
384 tmp = (u64)_m * fin;
385 do_div(tmp, _p);
386 if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
387 continue;
388
389 tmp = (u64)_m * fin;
390 do_div(tmp, _p << _s);
391
392 delta = abs(fout - tmp);
393 if (delta < min_delta) {
394 best_p = _p;
395 best_m = _m;
396 best_s = _s;
397 min_delta = delta;
398 best_freq = tmp;
399 }
400 }
401 }
402
403 if (best_freq) {
404 *p = best_p;
405 *m = best_m;
406 *s = best_s;
407 }
408
409 return best_freq;
410 }
411
412 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
413 unsigned long freq)
414 {
415 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
416 unsigned long fin, fout;
417 int timeout;
418 u8 p, s;
419 u16 m;
420 u32 reg;
421
422 clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
423
424 fin = clk_get_rate(dsi->pll_clk);
425 if (!fin) {
426 dev_err(dsi->dev, "failed to get PLL clock frequency\n");
427 return 0;
428 }
429
430 dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
431
432 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
433 if (!fout) {
434 dev_err(dsi->dev,
435 "failed to find PLL PMS for requested frequency\n");
436 return 0;
437 }
438 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
439
440 writel(500, dsi->reg_base + driver_data->plltmr_reg);
441
442 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
443
444 if (driver_data->has_freqband) {
445 static const unsigned long freq_bands[] = {
446 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
447 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
448 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
449 770 * MHZ, 870 * MHZ, 950 * MHZ,
450 };
451 int band;
452
453 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
454 if (fout < freq_bands[band])
455 break;
456
457 dev_dbg(dsi->dev, "band %d\n", band);
458
459 reg |= DSIM_FREQ_BAND(band);
460 }
461
462 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
463
464 timeout = 1000;
465 do {
466 if (timeout-- == 0) {
467 dev_err(dsi->dev, "PLL failed to stabilize\n");
468 return 0;
469 }
470 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
471 } while ((reg & DSIM_PLL_STABLE) == 0);
472
473 return fout;
474 }
475
476 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
477 {
478 unsigned long hs_clk, byte_clk, esc_clk;
479 unsigned long esc_div;
480 u32 reg;
481
482 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
483 if (!hs_clk) {
484 dev_err(dsi->dev, "failed to configure DSI PLL\n");
485 return -EFAULT;
486 }
487
488 byte_clk = hs_clk / 8;
489 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
490 esc_clk = byte_clk / esc_div;
491
492 if (esc_clk > 20 * MHZ) {
493 ++esc_div;
494 esc_clk = byte_clk / esc_div;
495 }
496
497 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
498 hs_clk, byte_clk, esc_clk);
499
500 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
501 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
502 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
503 | DSIM_BYTE_CLK_SRC_MASK);
504 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
505 | DSIM_ESC_PRESCALER(esc_div)
506 | DSIM_LANE_ESC_CLK_EN_CLK
507 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
508 | DSIM_BYTE_CLK_SRC(0)
509 | DSIM_TX_REQUEST_HSCLK;
510 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
511
512 return 0;
513 }
514
515 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
516 {
517 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
518 u32 reg;
519
520 if (driver_data->has_freqband)
521 return;
522
523 /* B D-PHY: D-PHY Master & Slave Analog Block control */
524 reg = DSIM_PHYCTRL_ULPS_EXIT(0x0af);
525 writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);
526
527 /*
528 * T LPX: Transmitted length of any Low-Power state period
529 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
530 * burst
531 */
532 reg = DSIM_PHYTIMING_LPX(0x06) | DSIM_PHYTIMING_HS_EXIT(0x0b);
533 writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);
534
535 /*
536 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
537 * Line state immediately before the HS-0 Line state starting the
538 * HS transmission
539 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
540 * transmitting the Clock.
541 * T CLK_POST: Time that the transmitter continues to send HS clock
542 * after the last associated Data Lane has transitioned to LP Mode
543 * Interval is defined as the period from the end of T HS-TRAIL to
544 * the beginning of T CLK-TRAIL
545 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
546 * the last payload clock bit of a HS transmission burst
547 */
548 reg = DSIM_PHYTIMING1_CLK_PREPARE(0x07) |
549 DSIM_PHYTIMING1_CLK_ZERO(0x27) |
550 DSIM_PHYTIMING1_CLK_POST(0x0d) |
551 DSIM_PHYTIMING1_CLK_TRAIL(0x08);
552 writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);
553
554 /*
555 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
556 * Line state immediately before the HS-0 Line state starting the
557 * HS transmission
558 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
559 * transmitting the Sync sequence.
560 * T HS-TRAIL: Time that the transmitter drives the flipped differential
561 * state after last payload data bit of a HS transmission burst
562 */
563 reg = DSIM_PHYTIMING2_HS_PREPARE(0x09) | DSIM_PHYTIMING2_HS_ZERO(0x0d) |
564 DSIM_PHYTIMING2_HS_TRAIL(0x0b);
565 writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
566 }
567
568 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
569 {
570 u32 reg;
571
572 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
573 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
574 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
575 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
576
577 reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
578 reg &= ~DSIM_PLL_EN;
579 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
580 }
581
582 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
583 {
584 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
585 int timeout;
586 u32 reg;
587 u32 lanes_mask;
588
589 /* Initialize FIFO pointers */
590 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
591 reg &= ~0x1f;
592 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
593
594 usleep_range(9000, 11000);
595
596 reg |= 0x1f;
597 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
598
599 usleep_range(9000, 11000);
600
601 /* DSI configuration */
602 reg = 0;
603
604 /*
605 * The first bit of mode_flags specifies display configuration.
606 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
607 * mode, otherwise it will support command mode.
608 */
609 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
610 reg |= DSIM_VIDEO_MODE;
611
612 /*
613 * The user manual describes that following bits are ignored in
614 * command mode.
615 */
616 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
617 reg |= DSIM_MFLUSH_VS;
618 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
619 reg |= DSIM_SYNC_INFORM;
620 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
621 reg |= DSIM_BURST_MODE;
622 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
623 reg |= DSIM_AUTO_MODE;
624 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
625 reg |= DSIM_HSE_MODE;
626 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
627 reg |= DSIM_HFP_MODE;
628 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
629 reg |= DSIM_HBP_MODE;
630 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
631 reg |= DSIM_HSA_MODE;
632 }
633
634 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
635 reg |= DSIM_EOT_DISABLE;
636
637 switch (dsi->format) {
638 case MIPI_DSI_FMT_RGB888:
639 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
640 break;
641 case MIPI_DSI_FMT_RGB666:
642 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
643 break;
644 case MIPI_DSI_FMT_RGB666_PACKED:
645 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
646 break;
647 case MIPI_DSI_FMT_RGB565:
648 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
649 break;
650 default:
651 dev_err(dsi->dev, "invalid pixel format\n");
652 return -EINVAL;
653 }
654
655 reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
656
657 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
658
659 reg |= DSIM_LANE_EN_CLK;
660 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
661
662 lanes_mask = BIT(dsi->lanes) - 1;
663 reg |= DSIM_LANE_EN(lanes_mask);
664 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
665
666 /*
667 * Use non-continuous clock mode if the periparal wants and
668 * host controller supports
669 *
670 * In non-continous clock mode, host controller will turn off
671 * the HS clock between high-speed transmissions to reduce
672 * power consumption.
673 */
674 if (driver_data->has_clklane_stop &&
675 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
676 reg |= DSIM_CLKLANE_STOP;
677 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
678 }
679
680 /* Check clock and data lane state are stop state */
681 timeout = 100;
682 do {
683 if (timeout-- == 0) {
684 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
685 return -EFAULT;
686 }
687
688 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
689 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
690 != DSIM_STOP_STATE_DAT(lanes_mask))
691 continue;
692 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
693
694 reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
695 reg &= ~DSIM_STOP_STATE_CNT_MASK;
696 reg |= DSIM_STOP_STATE_CNT(0xf);
697 writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
698
699 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
700 writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
701
702 return 0;
703 }
704
705 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
706 {
707 struct videomode *vm = &dsi->vm;
708 u32 reg;
709
710 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
711 reg = DSIM_CMD_ALLOW(0xf)
712 | DSIM_STABLE_VFP(vm->vfront_porch)
713 | DSIM_MAIN_VBP(vm->vback_porch);
714 writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
715
716 reg = DSIM_MAIN_HFP(vm->hfront_porch)
717 | DSIM_MAIN_HBP(vm->hback_porch);
718 writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
719
720 reg = DSIM_MAIN_VSA(vm->vsync_len)
721 | DSIM_MAIN_HSA(vm->hsync_len);
722 writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
723 }
724
725 reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
726 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
727
728 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
729 }
730
731 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
732 {
733 u32 reg;
734
735 reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
736 if (enable)
737 reg |= DSIM_MAIN_STAND_BY;
738 else
739 reg &= ~DSIM_MAIN_STAND_BY;
740 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
741 }
742
743 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
744 {
745 int timeout = 2000;
746
747 do {
748 u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
749
750 if (!(reg & DSIM_SFR_HEADER_FULL))
751 return 0;
752
753 if (!cond_resched())
754 usleep_range(950, 1050);
755 } while (--timeout);
756
757 return -ETIMEDOUT;
758 }
759
760 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
761 {
762 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
763
764 if (lpm)
765 v |= DSIM_CMD_LPDT_LP;
766 else
767 v &= ~DSIM_CMD_LPDT_LP;
768
769 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
770 }
771
772 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
773 {
774 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
775
776 v |= DSIM_FORCE_BTA;
777 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
778 }
779
780 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
781 struct exynos_dsi_transfer *xfer)
782 {
783 struct device *dev = dsi->dev;
784 const u8 *payload = xfer->tx_payload + xfer->tx_done;
785 u16 length = xfer->tx_len - xfer->tx_done;
786 bool first = !xfer->tx_done;
787 u32 reg;
788
789 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
790 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
791
792 if (length > DSI_TX_FIFO_SIZE)
793 length = DSI_TX_FIFO_SIZE;
794
795 xfer->tx_done += length;
796
797 /* Send payload */
798 while (length >= 4) {
799 reg = (payload[3] << 24) | (payload[2] << 16)
800 | (payload[1] << 8) | payload[0];
801 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
802 payload += 4;
803 length -= 4;
804 }
805
806 reg = 0;
807 switch (length) {
808 case 3:
809 reg |= payload[2] << 16;
810 /* Fall through */
811 case 2:
812 reg |= payload[1] << 8;
813 /* Fall through */
814 case 1:
815 reg |= payload[0];
816 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
817 break;
818 case 0:
819 /* Do nothing */
820 break;
821 }
822
823 /* Send packet header */
824 if (!first)
825 return;
826
827 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
828 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
829 dev_err(dev, "waiting for header FIFO timed out\n");
830 return;
831 }
832
833 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
834 dsi->state & DSIM_STATE_CMD_LPM)) {
835 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
836 dsi->state ^= DSIM_STATE_CMD_LPM;
837 }
838
839 writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
840
841 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
842 exynos_dsi_force_bta(dsi);
843 }
844
845 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
846 struct exynos_dsi_transfer *xfer)
847 {
848 u8 *payload = xfer->rx_payload + xfer->rx_done;
849 bool first = !xfer->rx_done;
850 struct device *dev = dsi->dev;
851 u16 length;
852 u32 reg;
853
854 if (first) {
855 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
856
857 switch (reg & 0x3f) {
858 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
859 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
860 if (xfer->rx_len >= 2) {
861 payload[1] = reg >> 16;
862 ++xfer->rx_done;
863 }
864 /* Fall through */
865 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
866 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
867 payload[0] = reg >> 8;
868 ++xfer->rx_done;
869 xfer->rx_len = xfer->rx_done;
870 xfer->result = 0;
871 goto clear_fifo;
872 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
873 dev_err(dev, "DSI Error Report: 0x%04x\n",
874 (reg >> 8) & 0xffff);
875 xfer->result = 0;
876 goto clear_fifo;
877 }
878
879 length = (reg >> 8) & 0xffff;
880 if (length > xfer->rx_len) {
881 dev_err(dev,
882 "response too long (%u > %u bytes), stripping\n",
883 xfer->rx_len, length);
884 length = xfer->rx_len;
885 } else if (length < xfer->rx_len)
886 xfer->rx_len = length;
887 }
888
889 length = xfer->rx_len - xfer->rx_done;
890 xfer->rx_done += length;
891
892 /* Receive payload */
893 while (length >= 4) {
894 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
895 payload[0] = (reg >> 0) & 0xff;
896 payload[1] = (reg >> 8) & 0xff;
897 payload[2] = (reg >> 16) & 0xff;
898 payload[3] = (reg >> 24) & 0xff;
899 payload += 4;
900 length -= 4;
901 }
902
903 if (length) {
904 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
905 switch (length) {
906 case 3:
907 payload[2] = (reg >> 16) & 0xff;
908 /* Fall through */
909 case 2:
910 payload[1] = (reg >> 8) & 0xff;
911 /* Fall through */
912 case 1:
913 payload[0] = reg & 0xff;
914 }
915 }
916
917 if (xfer->rx_done == xfer->rx_len)
918 xfer->result = 0;
919
920 clear_fifo:
921 length = DSI_RX_FIFO_SIZE / 4;
922 do {
923 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
924 if (reg == DSI_RX_FIFO_EMPTY)
925 break;
926 } while (--length);
927 }
928
929 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
930 {
931 unsigned long flags;
932 struct exynos_dsi_transfer *xfer;
933 bool start = false;
934
935 again:
936 spin_lock_irqsave(&dsi->transfer_lock, flags);
937
938 if (list_empty(&dsi->transfer_list)) {
939 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
940 return;
941 }
942
943 xfer = list_first_entry(&dsi->transfer_list,
944 struct exynos_dsi_transfer, list);
945
946 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
947
948 if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
949 /* waiting for RX */
950 return;
951
952 exynos_dsi_send_to_fifo(dsi, xfer);
953
954 if (xfer->tx_len || xfer->rx_len)
955 return;
956
957 xfer->result = 0;
958 complete(&xfer->completed);
959
960 spin_lock_irqsave(&dsi->transfer_lock, flags);
961
962 list_del_init(&xfer->list);
963 start = !list_empty(&dsi->transfer_list);
964
965 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
966
967 if (start)
968 goto again;
969 }
970
971 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
972 {
973 struct exynos_dsi_transfer *xfer;
974 unsigned long flags;
975 bool start = true;
976
977 spin_lock_irqsave(&dsi->transfer_lock, flags);
978
979 if (list_empty(&dsi->transfer_list)) {
980 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
981 return false;
982 }
983
984 xfer = list_first_entry(&dsi->transfer_list,
985 struct exynos_dsi_transfer, list);
986
987 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
988
989 dev_dbg(dsi->dev,
990 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
991 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
992
993 if (xfer->tx_done != xfer->tx_len)
994 return true;
995
996 if (xfer->rx_done != xfer->rx_len)
997 exynos_dsi_read_from_fifo(dsi, xfer);
998
999 if (xfer->rx_done != xfer->rx_len)
1000 return true;
1001
1002 spin_lock_irqsave(&dsi->transfer_lock, flags);
1003
1004 list_del_init(&xfer->list);
1005 start = !list_empty(&dsi->transfer_list);
1006
1007 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1008
1009 if (!xfer->rx_len)
1010 xfer->result = 0;
1011 complete(&xfer->completed);
1012
1013 return start;
1014 }
1015
1016 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1017 struct exynos_dsi_transfer *xfer)
1018 {
1019 unsigned long flags;
1020 bool start;
1021
1022 spin_lock_irqsave(&dsi->transfer_lock, flags);
1023
1024 if (!list_empty(&dsi->transfer_list) &&
1025 xfer == list_first_entry(&dsi->transfer_list,
1026 struct exynos_dsi_transfer, list)) {
1027 list_del_init(&xfer->list);
1028 start = !list_empty(&dsi->transfer_list);
1029 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1030 if (start)
1031 exynos_dsi_transfer_start(dsi);
1032 return;
1033 }
1034
1035 list_del_init(&xfer->list);
1036
1037 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1038 }
1039
1040 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1041 struct exynos_dsi_transfer *xfer)
1042 {
1043 unsigned long flags;
1044 bool stopped;
1045
1046 xfer->tx_done = 0;
1047 xfer->rx_done = 0;
1048 xfer->result = -ETIMEDOUT;
1049 init_completion(&xfer->completed);
1050
1051 spin_lock_irqsave(&dsi->transfer_lock, flags);
1052
1053 stopped = list_empty(&dsi->transfer_list);
1054 list_add_tail(&xfer->list, &dsi->transfer_list);
1055
1056 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1057
1058 if (stopped)
1059 exynos_dsi_transfer_start(dsi);
1060
1061 wait_for_completion_timeout(&xfer->completed,
1062 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1063 if (xfer->result == -ETIMEDOUT) {
1064 exynos_dsi_remove_transfer(dsi, xfer);
1065 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
1066 xfer->tx_len, xfer->tx_payload);
1067 return -ETIMEDOUT;
1068 }
1069
1070 /* Also covers hardware timeout condition */
1071 return xfer->result;
1072 }
1073
1074 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1075 {
1076 struct exynos_dsi *dsi = dev_id;
1077 u32 status;
1078
1079 status = readl(dsi->reg_base + DSIM_INTSRC_REG);
1080 if (!status) {
1081 static unsigned long int j;
1082 if (printk_timed_ratelimit(&j, 500))
1083 dev_warn(dsi->dev, "spurious interrupt\n");
1084 return IRQ_HANDLED;
1085 }
1086 writel(status, dsi->reg_base + DSIM_INTSRC_REG);
1087
1088 if (status & DSIM_INT_SW_RST_RELEASE) {
1089 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
1090 writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
1091 complete(&dsi->completed);
1092 return IRQ_HANDLED;
1093 }
1094
1095 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
1096 return IRQ_HANDLED;
1097
1098 if (exynos_dsi_transfer_finish(dsi))
1099 exynos_dsi_transfer_start(dsi);
1100
1101 return IRQ_HANDLED;
1102 }
1103
1104 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1105 {
1106 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1107 struct drm_encoder *encoder = dsi->encoder;
1108
1109 if (dsi->state & DSIM_STATE_ENABLED)
1110 exynos_drm_crtc_te_handler(encoder->crtc);
1111
1112 return IRQ_HANDLED;
1113 }
1114
1115 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1116 {
1117 enable_irq(dsi->irq);
1118
1119 if (gpio_is_valid(dsi->te_gpio))
1120 enable_irq(gpio_to_irq(dsi->te_gpio));
1121 }
1122
1123 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1124 {
1125 if (gpio_is_valid(dsi->te_gpio))
1126 disable_irq(gpio_to_irq(dsi->te_gpio));
1127
1128 disable_irq(dsi->irq);
1129 }
1130
1131 static int exynos_dsi_init(struct exynos_dsi *dsi)
1132 {
1133 exynos_dsi_reset(dsi);
1134 exynos_dsi_enable_irq(dsi);
1135 exynos_dsi_enable_clock(dsi);
1136 exynos_dsi_wait_for_reset(dsi);
1137 exynos_dsi_set_phy_ctrl(dsi);
1138 exynos_dsi_init_link(dsi);
1139
1140 return 0;
1141 }
1142
1143 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
1144 {
1145 int ret;
1146
1147 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
1148 if (!gpio_is_valid(dsi->te_gpio)) {
1149 dev_err(dsi->dev, "no te-gpios specified\n");
1150 ret = dsi->te_gpio;
1151 goto out;
1152 }
1153
1154 ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
1155 if (ret) {
1156 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1157 goto out;
1158 }
1159
1160 /*
1161 * This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
1162 * calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
1163 * It means that te_gpio is invalid when exynos_dsi_enable_irq() is
1164 * called by drm_panel_init() before panel is attached.
1165 */
1166 ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio),
1167 exynos_dsi_te_irq_handler, NULL,
1168 IRQF_TRIGGER_RISING, "TE", dsi);
1169 if (ret) {
1170 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1171 gpio_free(dsi->te_gpio);
1172 goto out;
1173 }
1174
1175 out:
1176 return ret;
1177 }
1178
1179 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1180 {
1181 if (gpio_is_valid(dsi->te_gpio)) {
1182 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1183 gpio_free(dsi->te_gpio);
1184 dsi->te_gpio = -ENOENT;
1185 }
1186 }
1187
1188 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1189 struct mipi_dsi_device *device)
1190 {
1191 struct exynos_dsi *dsi = host_to_dsi(host);
1192
1193 dsi->lanes = device->lanes;
1194 dsi->format = device->format;
1195 dsi->mode_flags = device->mode_flags;
1196 dsi->panel_node = device->dev.of_node;
1197
1198 if (dsi->connector.dev)
1199 drm_helper_hpd_irq_event(dsi->connector.dev);
1200
1201 /*
1202 * This is a temporary solution and should be made by more generic way.
1203 *
1204 * If attached panel device is for command mode one, dsi should register
1205 * TE interrupt handler.
1206 */
1207 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1208 int ret = exynos_dsi_register_te_irq(dsi);
1209
1210 if (ret)
1211 return ret;
1212 }
1213
1214 return 0;
1215 }
1216
1217 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1218 struct mipi_dsi_device *device)
1219 {
1220 struct exynos_dsi *dsi = host_to_dsi(host);
1221
1222 exynos_dsi_unregister_te_irq(dsi);
1223
1224 dsi->panel_node = NULL;
1225
1226 if (dsi->connector.dev)
1227 drm_helper_hpd_irq_event(dsi->connector.dev);
1228
1229 return 0;
1230 }
1231
1232 /* distinguish between short and long DSI packet types */
1233 static bool exynos_dsi_is_short_dsi_type(u8 type)
1234 {
1235 return (type & 0x0f) <= 8;
1236 }
1237
1238 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1239 struct mipi_dsi_msg *msg)
1240 {
1241 struct exynos_dsi *dsi = host_to_dsi(host);
1242 struct exynos_dsi_transfer xfer;
1243 int ret;
1244
1245 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1246 ret = exynos_dsi_init(dsi);
1247 if (ret)
1248 return ret;
1249 dsi->state |= DSIM_STATE_INITIALIZED;
1250 }
1251
1252 if (msg->tx_len == 0)
1253 return -EINVAL;
1254
1255 xfer.data_id = msg->type | (msg->channel << 6);
1256
1257 if (exynos_dsi_is_short_dsi_type(msg->type)) {
1258 const char *tx_buf = msg->tx_buf;
1259
1260 if (msg->tx_len > 2)
1261 return -EINVAL;
1262 xfer.tx_len = 0;
1263 xfer.data[0] = tx_buf[0];
1264 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1265 } else {
1266 xfer.tx_len = msg->tx_len;
1267 xfer.data[0] = msg->tx_len & 0xff;
1268 xfer.data[1] = msg->tx_len >> 8;
1269 xfer.tx_payload = msg->tx_buf;
1270 }
1271
1272 xfer.rx_len = msg->rx_len;
1273 xfer.rx_payload = msg->rx_buf;
1274 xfer.flags = msg->flags;
1275
1276 ret = exynos_dsi_transfer(dsi, &xfer);
1277 return (ret < 0) ? ret : xfer.rx_done;
1278 }
1279
1280 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1281 .attach = exynos_dsi_host_attach,
1282 .detach = exynos_dsi_host_detach,
1283 .transfer = exynos_dsi_host_transfer,
1284 };
1285
1286 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1287 {
1288 int ret;
1289
1290 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1291 if (ret < 0) {
1292 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1293 return ret;
1294 }
1295
1296 ret = clk_prepare_enable(dsi->bus_clk);
1297 if (ret < 0) {
1298 dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1299 goto err_bus_clk;
1300 }
1301
1302 ret = clk_prepare_enable(dsi->pll_clk);
1303 if (ret < 0) {
1304 dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1305 goto err_pll_clk;
1306 }
1307
1308 ret = phy_power_on(dsi->phy);
1309 if (ret < 0) {
1310 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1311 goto err_phy;
1312 }
1313
1314 return 0;
1315
1316 err_phy:
1317 clk_disable_unprepare(dsi->pll_clk);
1318 err_pll_clk:
1319 clk_disable_unprepare(dsi->bus_clk);
1320 err_bus_clk:
1321 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1322
1323 return ret;
1324 }
1325
1326 static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1327 {
1328 int ret;
1329
1330 usleep_range(10000, 20000);
1331
1332 if (dsi->state & DSIM_STATE_INITIALIZED) {
1333 dsi->state &= ~DSIM_STATE_INITIALIZED;
1334
1335 exynos_dsi_disable_clock(dsi);
1336
1337 exynos_dsi_disable_irq(dsi);
1338 }
1339
1340 dsi->state &= ~DSIM_STATE_CMD_LPM;
1341
1342 phy_power_off(dsi->phy);
1343
1344 clk_disable_unprepare(dsi->pll_clk);
1345 clk_disable_unprepare(dsi->bus_clk);
1346
1347 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1348 if (ret < 0)
1349 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1350 }
1351
1352 static int exynos_dsi_enable(struct exynos_dsi *dsi)
1353 {
1354 int ret;
1355
1356 if (dsi->state & DSIM_STATE_ENABLED)
1357 return 0;
1358
1359 ret = exynos_dsi_poweron(dsi);
1360 if (ret < 0)
1361 return ret;
1362
1363 ret = drm_panel_prepare(dsi->panel);
1364 if (ret < 0) {
1365 exynos_dsi_poweroff(dsi);
1366 return ret;
1367 }
1368
1369 exynos_dsi_set_display_mode(dsi);
1370 exynos_dsi_set_display_enable(dsi, true);
1371
1372 ret = drm_panel_enable(dsi->panel);
1373 if (ret < 0) {
1374 exynos_dsi_set_display_enable(dsi, false);
1375 drm_panel_unprepare(dsi->panel);
1376 exynos_dsi_poweroff(dsi);
1377 return ret;
1378 }
1379
1380 dsi->state |= DSIM_STATE_ENABLED;
1381
1382 return 0;
1383 }
1384
1385 static void exynos_dsi_disable(struct exynos_dsi *dsi)
1386 {
1387 if (!(dsi->state & DSIM_STATE_ENABLED))
1388 return;
1389
1390 drm_panel_disable(dsi->panel);
1391 exynos_dsi_set_display_enable(dsi, false);
1392 drm_panel_unprepare(dsi->panel);
1393 exynos_dsi_poweroff(dsi);
1394
1395 dsi->state &= ~DSIM_STATE_ENABLED;
1396 }
1397
1398 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1399 {
1400 struct exynos_dsi *dsi = display->ctx;
1401
1402 if (dsi->panel) {
1403 switch (mode) {
1404 case DRM_MODE_DPMS_ON:
1405 exynos_dsi_enable(dsi);
1406 break;
1407 case DRM_MODE_DPMS_STANDBY:
1408 case DRM_MODE_DPMS_SUSPEND:
1409 case DRM_MODE_DPMS_OFF:
1410 exynos_dsi_disable(dsi);
1411 break;
1412 default:
1413 break;
1414 }
1415 }
1416 }
1417
1418 static enum drm_connector_status
1419 exynos_dsi_detect(struct drm_connector *connector, bool force)
1420 {
1421 struct exynos_dsi *dsi = connector_to_dsi(connector);
1422
1423 if (!dsi->panel) {
1424 dsi->panel = of_drm_find_panel(dsi->panel_node);
1425 if (dsi->panel)
1426 drm_panel_attach(dsi->panel, &dsi->connector);
1427 } else if (!dsi->panel_node) {
1428 struct exynos_drm_display *display;
1429
1430 display = platform_get_drvdata(to_platform_device(dsi->dev));
1431 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1432 drm_panel_detach(dsi->panel);
1433 dsi->panel = NULL;
1434 }
1435
1436 if (dsi->panel)
1437 return connector_status_connected;
1438
1439 return connector_status_disconnected;
1440 }
1441
1442 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1443 {
1444 drm_connector_unregister(connector);
1445 drm_connector_cleanup(connector);
1446 connector->dev = NULL;
1447 }
1448
1449 static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1450 .dpms = drm_helper_connector_dpms,
1451 .detect = exynos_dsi_detect,
1452 .fill_modes = drm_helper_probe_single_connector_modes,
1453 .destroy = exynos_dsi_connector_destroy,
1454 };
1455
1456 static int exynos_dsi_get_modes(struct drm_connector *connector)
1457 {
1458 struct exynos_dsi *dsi = connector_to_dsi(connector);
1459
1460 if (dsi->panel)
1461 return dsi->panel->funcs->get_modes(dsi->panel);
1462
1463 return 0;
1464 }
1465
1466 static int exynos_dsi_mode_valid(struct drm_connector *connector,
1467 struct drm_display_mode *mode)
1468 {
1469 return MODE_OK;
1470 }
1471
1472 static struct drm_encoder *
1473 exynos_dsi_best_encoder(struct drm_connector *connector)
1474 {
1475 struct exynos_dsi *dsi = connector_to_dsi(connector);
1476
1477 return dsi->encoder;
1478 }
1479
1480 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1481 .get_modes = exynos_dsi_get_modes,
1482 .mode_valid = exynos_dsi_mode_valid,
1483 .best_encoder = exynos_dsi_best_encoder,
1484 };
1485
1486 static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1487 struct drm_encoder *encoder)
1488 {
1489 struct exynos_dsi *dsi = display->ctx;
1490 struct drm_connector *connector = &dsi->connector;
1491 int ret;
1492
1493 dsi->encoder = encoder;
1494
1495 connector->polled = DRM_CONNECTOR_POLL_HPD;
1496
1497 ret = drm_connector_init(encoder->dev, connector,
1498 &exynos_dsi_connector_funcs,
1499 DRM_MODE_CONNECTOR_DSI);
1500 if (ret) {
1501 DRM_ERROR("Failed to initialize connector with drm\n");
1502 return ret;
1503 }
1504
1505 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1506 drm_connector_register(connector);
1507 drm_mode_connector_attach_encoder(connector, encoder);
1508
1509 return 0;
1510 }
1511
1512 static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1513 struct drm_display_mode *mode)
1514 {
1515 struct exynos_dsi *dsi = display->ctx;
1516 struct videomode *vm = &dsi->vm;
1517
1518 vm->hactive = mode->hdisplay;
1519 vm->vactive = mode->vdisplay;
1520 vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1521 vm->vback_porch = mode->vtotal - mode->vsync_end;
1522 vm->vsync_len = mode->vsync_end - mode->vsync_start;
1523 vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1524 vm->hback_porch = mode->htotal - mode->hsync_end;
1525 vm->hsync_len = mode->hsync_end - mode->hsync_start;
1526 }
1527
1528 static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1529 .create_connector = exynos_dsi_create_connector,
1530 .mode_set = exynos_dsi_mode_set,
1531 .dpms = exynos_dsi_dpms
1532 };
1533
1534 static struct exynos_drm_display exynos_dsi_display = {
1535 .type = EXYNOS_DISPLAY_TYPE_LCD,
1536 .ops = &exynos_dsi_display_ops,
1537 };
1538 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1539
1540 /* of_* functions will be removed after merge of of_graph patches */
1541 static struct device_node *
1542 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1543 {
1544 struct device_node *np;
1545
1546 for_each_child_of_node(parent, np) {
1547 u32 r;
1548
1549 if (!np->name || of_node_cmp(np->name, name))
1550 continue;
1551
1552 if (of_property_read_u32(np, "reg", &r) < 0)
1553 r = 0;
1554
1555 if (reg == r)
1556 break;
1557 }
1558
1559 return np;
1560 }
1561
1562 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1563 u32 reg)
1564 {
1565 struct device_node *ports, *port;
1566
1567 ports = of_get_child_by_name(parent, "ports");
1568 if (ports)
1569 parent = ports;
1570
1571 port = of_get_child_by_name_reg(parent, "port", reg);
1572
1573 of_node_put(ports);
1574
1575 return port;
1576 }
1577
1578 static struct device_node *
1579 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1580 {
1581 return of_get_child_by_name_reg(port, "endpoint", reg);
1582 }
1583
1584 static int exynos_dsi_of_read_u32(const struct device_node *np,
1585 const char *propname, u32 *out_value)
1586 {
1587 int ret = of_property_read_u32(np, propname, out_value);
1588
1589 if (ret < 0)
1590 pr_err("%s: failed to get '%s' property\n", np->full_name,
1591 propname);
1592
1593 return ret;
1594 }
1595
1596 enum {
1597 DSI_PORT_IN,
1598 DSI_PORT_OUT
1599 };
1600
1601 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1602 {
1603 struct device *dev = dsi->dev;
1604 struct device_node *node = dev->of_node;
1605 struct device_node *port, *ep;
1606 int ret;
1607
1608 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1609 &dsi->pll_clk_rate);
1610 if (ret < 0)
1611 return ret;
1612
1613 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1614 if (!port) {
1615 dev_err(dev, "no output port specified\n");
1616 return -EINVAL;
1617 }
1618
1619 ep = of_graph_get_endpoint_by_reg(port, 0);
1620 of_node_put(port);
1621 if (!ep) {
1622 dev_err(dev, "no endpoint specified in output port\n");
1623 return -EINVAL;
1624 }
1625
1626 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1627 &dsi->burst_clk_rate);
1628 if (ret < 0)
1629 goto end;
1630
1631 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1632 &dsi->esc_clk_rate);
1633
1634 end:
1635 of_node_put(ep);
1636
1637 return ret;
1638 }
1639
1640 static int exynos_dsi_bind(struct device *dev, struct device *master,
1641 void *data)
1642 {
1643 struct drm_device *drm_dev = data;
1644 struct exynos_dsi *dsi;
1645 int ret;
1646
1647 ret = exynos_drm_create_enc_conn(drm_dev, &exynos_dsi_display);
1648 if (ret) {
1649 DRM_ERROR("Encoder create [%d] failed with %d\n",
1650 exynos_dsi_display.type, ret);
1651 return ret;
1652 }
1653
1654 dsi = exynos_dsi_display.ctx;
1655
1656 return mipi_dsi_host_register(&dsi->dsi_host);
1657 }
1658
1659 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1660 void *data)
1661 {
1662 struct exynos_dsi *dsi = exynos_dsi_display.ctx;
1663 struct drm_encoder *encoder = dsi->encoder;
1664
1665 exynos_dsi_dpms(&exynos_dsi_display, DRM_MODE_DPMS_OFF);
1666
1667 exynos_dsi_connector_destroy(&dsi->connector);
1668 encoder->funcs->destroy(encoder);
1669
1670 mipi_dsi_host_unregister(&dsi->dsi_host);
1671 }
1672
1673 static const struct component_ops exynos_dsi_component_ops = {
1674 .bind = exynos_dsi_bind,
1675 .unbind = exynos_dsi_unbind,
1676 };
1677
1678 static int exynos_dsi_probe(struct platform_device *pdev)
1679 {
1680 struct resource *res;
1681 struct exynos_dsi *dsi;
1682 int ret;
1683
1684 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1685 exynos_dsi_display.type);
1686 if (ret)
1687 return ret;
1688
1689 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1690 if (!dsi) {
1691 dev_err(&pdev->dev, "failed to allocate dsi object.\n");
1692 ret = -ENOMEM;
1693 goto err_del_component;
1694 }
1695
1696 /* To be checked as invalid one */
1697 dsi->te_gpio = -ENOENT;
1698
1699 init_completion(&dsi->completed);
1700 spin_lock_init(&dsi->transfer_lock);
1701 INIT_LIST_HEAD(&dsi->transfer_list);
1702
1703 dsi->dsi_host.ops = &exynos_dsi_ops;
1704 dsi->dsi_host.dev = &pdev->dev;
1705
1706 dsi->dev = &pdev->dev;
1707 dsi->driver_data = exynos_dsi_get_driver_data(pdev);
1708
1709 ret = exynos_dsi_parse_dt(dsi);
1710 if (ret)
1711 goto err_del_component;
1712
1713 dsi->supplies[0].supply = "vddcore";
1714 dsi->supplies[1].supply = "vddio";
1715 ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(dsi->supplies),
1716 dsi->supplies);
1717 if (ret) {
1718 dev_info(&pdev->dev, "failed to get regulators: %d\n", ret);
1719 return -EPROBE_DEFER;
1720 }
1721
1722 dsi->pll_clk = devm_clk_get(&pdev->dev, "pll_clk");
1723 if (IS_ERR(dsi->pll_clk)) {
1724 dev_info(&pdev->dev, "failed to get dsi pll input clock\n");
1725 ret = PTR_ERR(dsi->pll_clk);
1726 goto err_del_component;
1727 }
1728
1729 dsi->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
1730 if (IS_ERR(dsi->bus_clk)) {
1731 dev_info(&pdev->dev, "failed to get dsi bus clock\n");
1732 ret = PTR_ERR(dsi->bus_clk);
1733 goto err_del_component;
1734 }
1735
1736 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1737 dsi->reg_base = devm_ioremap_resource(&pdev->dev, res);
1738 if (IS_ERR(dsi->reg_base)) {
1739 dev_err(&pdev->dev, "failed to remap io region\n");
1740 ret = PTR_ERR(dsi->reg_base);
1741 goto err_del_component;
1742 }
1743
1744 dsi->phy = devm_phy_get(&pdev->dev, "dsim");
1745 if (IS_ERR(dsi->phy)) {
1746 dev_info(&pdev->dev, "failed to get dsim phy\n");
1747 ret = PTR_ERR(dsi->phy);
1748 goto err_del_component;
1749 }
1750
1751 dsi->irq = platform_get_irq(pdev, 0);
1752 if (dsi->irq < 0) {
1753 dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1754 ret = dsi->irq;
1755 goto err_del_component;
1756 }
1757
1758 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1759 ret = devm_request_threaded_irq(&pdev->dev, dsi->irq, NULL,
1760 exynos_dsi_irq, IRQF_ONESHOT,
1761 dev_name(&pdev->dev), dsi);
1762 if (ret) {
1763 dev_err(&pdev->dev, "failed to request dsi irq\n");
1764 goto err_del_component;
1765 }
1766
1767 exynos_dsi_display.ctx = dsi;
1768
1769 platform_set_drvdata(pdev, &exynos_dsi_display);
1770
1771 ret = component_add(&pdev->dev, &exynos_dsi_component_ops);
1772 if (ret)
1773 goto err_del_component;
1774
1775 return ret;
1776
1777 err_del_component:
1778 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1779 return ret;
1780 }
1781
1782 static int exynos_dsi_remove(struct platform_device *pdev)
1783 {
1784 component_del(&pdev->dev, &exynos_dsi_component_ops);
1785 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1786
1787 return 0;
1788 }
1789
1790 struct platform_driver dsi_driver = {
1791 .probe = exynos_dsi_probe,
1792 .remove = exynos_dsi_remove,
1793 .driver = {
1794 .name = "exynos-dsi",
1795 .owner = THIS_MODULE,
1796 .of_match_table = exynos_dsi_of_match,
1797 },
1798 };
1799
1800 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1801 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1802 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1803 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support