drivers/gpu/drm/i915/i915_gem_gtt.h

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Please try to maintain the following order within this file unless it makes
  24  * sense to do otherwise. From top to bottom:
  25  * 1. typedefs
  26  * 2. #defines, and macros
  27  * 3. structure definitions
  28  * 4. function prototypes
  29  *
  30  * Within each section, please try to order by generation in ascending order,
  31  * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
  32  */
  33
  34 #ifndef __I915_GEM_GTT_H__
  35 #define __I915_GEM_GTT_H__
  36
  37 struct drm_i915_file_private;
  38
  39 typedef uint32_t gen6_gtt_pte_t;
  40 typedef uint64_t gen8_gtt_pte_t;
  41 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
  42
  43 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
  44
  45 #define I915_PPGTT_PT_ENTRIES           (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  46 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
  47 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  48 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  49 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  50 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  51 #define GEN6_PTE_UNCACHED               (1 << 1)
  52 #define GEN6_PTE_VALID                  (1 << 0)
  53
  54 #define GEN6_PPGTT_PD_ENTRIES           512
  55 #define GEN6_PD_SIZE                    (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
  56 #define GEN6_PD_ALIGN                   (PAGE_SIZE * 16)
  57 #define GEN6_PDE_VALID                  (1 << 0)
  58
  59 #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  60
  61 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
  62 #define BYT_PTE_WRITEABLE               (1 << 1)
  63
  64 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
  65  * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  66  */
  67 #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  68                                          (((bits) & 0x8) << (11 - 3)))
  69 #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  70 #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  71 #define HSW_WB_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x8)
  72 #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  73 #define HSW_WT_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x7)
  74 #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  75 #define HSW_PTE_UNCACHED                (0)
  76 #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  77 #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  78
  79 /* GEN8 legacy style address is defined as a 3 level page table:
  80  * 31:30 | 29:21 | 20:12 |  11:0
  81  * PDPE  |  PDE  |  PTE  | offset
  82  * The difference as compared to normal x86 3 level page table is the PDPEs are
  83  * programmed via register.
  84  */
  85 #define GEN8_PDPE_SHIFT                 30
  86 #define GEN8_PDPE_MASK                  0x3
  87 #define GEN8_PDE_SHIFT                  21
  88 #define GEN8_PDE_MASK                   0x1ff
  89 #define GEN8_PTE_SHIFT                  12
  90 #define GEN8_PTE_MASK                   0x1ff
  91 #define GEN8_LEGACY_PDPS                4
  92 #define GEN8_PTES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
  93 #define GEN8_PDES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
  94
  95 #define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
  96 #define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
  97 #define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
  98 #define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
  99
 100 #define CHV_PPAT_SNOOP                  (1<<6)
 101 #define GEN8_PPAT_AGE(x)                (x<<4)
 102 #define GEN8_PPAT_LLCeLLC               (3<<2)
 103 #define GEN8_PPAT_LLCELLC               (2<<2)
 104 #define GEN8_PPAT_LLC                   (1<<2)
 105 #define GEN8_PPAT_WB                    (3<<0)
 106 #define GEN8_PPAT_WT                    (2<<0)
 107 #define GEN8_PPAT_WC                    (1<<0)
 108 #define GEN8_PPAT_UC                    (0<<0)
 109 #define GEN8_PPAT_ELLC_OVERRIDE         (0<<2)
 110 #define GEN8_PPAT(i, x)                 ((uint64_t) (x) << ((i) * 8))
 111
 112 enum i915_cache_level;
 113 /**
 114  * A VMA represents a GEM BO that is bound into an address space. Therefore, a
 115  * VMA's presence cannot be guaranteed before binding, or after unbinding the
 116  * object into/from the address space.
 117  *
 118  * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
 119  * will always be <= an objects lifetime. So object refcounting should cover us.
 120  */
 121 struct i915_vma {
 122         struct drm_mm_node node;
 123         struct drm_i915_gem_object *obj;
 124         struct i915_address_space *vm;
 125
 126         /** This object's place on the active/inactive lists */
 127         struct list_head mm_list;
 128
 129         struct list_head vma_link; /* Link in the object's VMA list */
 130
 131         /** This vma's place in the batchbuffer or on the eviction list */
 132         struct list_head exec_list;
 133
 134         /**
 135          * Used for performing relocations during execbuffer insertion.
 136          */
 137         struct hlist_node exec_node;
 138         unsigned long exec_handle;
 139         struct drm_i915_gem_exec_object2 *exec_entry;
 140
 141         /**
 142          * How many users have pinned this object in GTT space. The following
 143          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 144          * (via user_pin_count), execbuffer (objects are not allowed multiple
 145          * times for the same batchbuffer), and the framebuffer code. When
 146          * switching/pageflipping, the framebuffer code has at most two buffers
 147          * pinned per crtc.
 148          *
 149          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 150          * bits with absolutely no headroom. So use 4 bits. */
 151         unsigned int pin_count:4;
 152 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 153
 154         /** Unmap an object from an address space. This usually consists of
 155          * setting the valid PTE entries to a reserved scratch page. */
 156         void (*unbind_vma)(struct i915_vma *vma);
 157         /* Map an object into an address space with the given cache flags. */
 158 #define GLOBAL_BIND (1<<0)
 159 #define PTE_READ_ONLY (1<<1)
 160         void (*bind_vma)(struct i915_vma *vma,
 161                          enum i915_cache_level cache_level,
 162                          u32 flags);
 163 };
 164
 165 struct i915_address_space {
 166         struct drm_mm mm;
 167         struct drm_device *dev;
 168         struct list_head global_link;
 169         unsigned long start;            /* Start offset always 0 for dri2 */
 170         size_t total;           /* size addr space maps (ex. 2GB for ggtt) */
 171
 172         struct {
 173                 dma_addr_t addr;
 174                 struct page *page;
 175         } scratch;
 176
 177         /**
 178          * List of objects currently involved in rendering.
 179          *
 180          * Includes buffers having the contents of their GPU caches
 181          * flushed, not necessarily primitives.  last_rendering_seqno
 182          * represents when the rendering involved will be completed.
 183          *
 184          * A reference is held on the buffer while on this list.
 185          */
 186         struct list_head active_list;
 187
 188         /**
 189          * LRU list of objects which are not in the ringbuffer and
 190          * are ready to unbind, but are still in the GTT.
 191          *
 192          * last_rendering_seqno is 0 while an object is in this list.
 193          *
 194          * A reference is not held on the buffer while on this list,
 195          * as merely being GTT-bound shouldn't prevent its being
 196          * freed, and we'll pull it off the list in the free path.
 197          */
 198         struct list_head inactive_list;
 199
 200         /* FIXME: Need a more generic return type */
 201         gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
 202                                      enum i915_cache_level level,
 203                                      bool valid, u32 flags); /* Create a valid PTE */
 204         void (*clear_range)(struct i915_address_space *vm,
 205                             uint64_t start,
 206                             uint64_t length,
 207                             bool use_scratch);
 208         void (*insert_entries)(struct i915_address_space *vm,
 209                                struct sg_table *st,
 210                                uint64_t start,
 211                                enum i915_cache_level cache_level, u32 flags);
 212         void (*cleanup)(struct i915_address_space *vm);
 213 };
 214
 215 /* The Graphics Translation Table is the way in which GEN hardware translates a
 216  * Graphics Virtual Address into a Physical Address. In addition to the normal
 217  * collateral associated with any va->pa translations GEN hardware also has a
 218  * portion of the GTT which can be mapped by the CPU and remain both coherent
 219  * and correct (in cases like swizzling). That region is referred to as GMADR in
 220  * the spec.
 221  */
 222 struct i915_gtt {
 223         struct i915_address_space base;
 224         size_t stolen_size;             /* Total size of stolen memory */
 225
 226         unsigned long mappable_end;     /* End offset that we can CPU map */
 227         struct io_mapping *mappable;    /* Mapping to our CPU mappable region */
 228         phys_addr_t mappable_base;      /* PA of our GMADR */
 229
 230         /** "Graphics Stolen Memory" holds the global PTEs */
 231         void __iomem *gsm;
 232
 233         bool do_idle_maps;
 234
 235         int mtrr;
 236
 237         /* global gtt ops */
 238         int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
 239                           size_t *stolen, phys_addr_t *mappable_base,
 240                           unsigned long *mappable_end);
 241 };
 242
 243 struct i915_hw_ppgtt {
 244         struct i915_address_space base;
 245         struct kref ref;
 246         struct drm_mm_node node;
 247         unsigned num_pd_entries;
 248         unsigned num_pd_pages; /* gen8+ */
 249         union {
 250                 struct page **pt_pages;
 251                 struct page **gen8_pt_pages[GEN8_LEGACY_PDPS];
 252         };
 253         struct page *pd_pages;
 254         union {
 255                 uint32_t pd_offset;
 256                 dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS];
 257         };
 258         union {
 259                 dma_addr_t *pt_dma_addr;
 260                 dma_addr_t *gen8_pt_dma_addr[4];
 261         };
 262
 263         struct drm_i915_file_private *file_priv;
 264
 265         int (*enable)(struct i915_hw_ppgtt *ppgtt);
 266         int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
 267                          struct intel_engine_cs *ring);
 268         void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
 269 };
 270
 271 int i915_gem_gtt_init(struct drm_device *dev);
 272 void i915_gem_init_global_gtt(struct drm_device *dev);
 273 int i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
 274                               unsigned long mappable_end, unsigned long end);
 275 void i915_global_gtt_cleanup(struct drm_device *dev);
 276
 277
 278 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
 279 int i915_ppgtt_init_hw(struct drm_device *dev);
 280 void i915_ppgtt_release(struct kref *kref);
 281 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
 282                                         struct drm_i915_file_private *fpriv);
 283 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
 284 {
 285         if (ppgtt)
 286                 kref_get(&ppgtt->ref);
 287 }
 288 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
 289 {
 290         if (ppgtt)
 291                 kref_put(&ppgtt->ref, i915_ppgtt_release);
 292 }
 293
 294 void i915_check_and_clear_faults(struct drm_device *dev);
 295 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
 296 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
 297
 298 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
 299 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
 300
 301 #endif