include/video/imx-ipu-v3.h

   1 /*
   2  * Copyright 2005-2009 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU Lesser General
   5  * Public License.  You may obtain a copy of the GNU Lesser General
   6  * Public License Version 2.1 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/lgpl-license.html
   9  * http://www.gnu.org/copyleft/lgpl.html
  10  */
  11
  12 #ifndef __DRM_IPU_H__
  13 #define __DRM_IPU_H__
  14
  15 #include <linux/types.h>
  16 #include <linux/videodev2.h>
  17 #include <linux/bitmap.h>
  18 #include <linux/fb.h>
  19 #include <media/v4l2-mediabus.h>
  20
  21 struct ipu_soc;
  22
  23 enum ipuv3_type {
  24         IPUV3EX,
  25         IPUV3M,
  26         IPUV3H,
  27 };
  28
  29 #define IPU_PIX_FMT_GBR24       v4l2_fourcc('G', 'B', 'R', '3')
  30
  31 /*
  32  * Bitfield of Display Interface signal polarities.
  33  */
  34 struct ipu_di_signal_cfg {
  35         unsigned datamask_en:1;
  36         unsigned interlaced:1;
  37         unsigned odd_field_first:1;
  38         unsigned clksel_en:1;
  39         unsigned clkidle_en:1;
  40         unsigned data_pol:1;    /* true = inverted */
  41         unsigned clk_pol:1;     /* true = rising edge */
  42         unsigned enable_pol:1;
  43         unsigned Hsync_pol:1;   /* true = active high */
  44         unsigned Vsync_pol:1;
  45
  46         u16 width;
  47         u16 height;
  48         u32 pixel_fmt;
  49         u16 h_start_width;
  50         u16 h_sync_width;
  51         u16 h_end_width;
  52         u16 v_start_width;
  53         u16 v_sync_width;
  54         u16 v_end_width;
  55         u32 v_to_h_sync;
  56         unsigned long pixelclock;
  57 #define IPU_DI_CLKMODE_SYNC     (1 << 0)
  58 #define IPU_DI_CLKMODE_EXT      (1 << 1)
  59         unsigned long clkflags;
  60
  61         u8 hsync_pin;
  62         u8 vsync_pin;
  63 };
  64
  65 /*
  66  * Enumeration of CSI destinations
  67  */
  68 enum ipu_csi_dest {
  69         IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
  70         IPU_CSI_DEST_IC,        /* to Image Converter */
  71         IPU_CSI_DEST_VDIC,  /* to VDIC */
  72 };
  73
  74 /*
  75  * Enumeration of IPU rotation modes
  76  */
  77 enum ipu_rotate_mode {
  78         IPU_ROTATE_NONE = 0,
  79         IPU_ROTATE_VERT_FLIP,
  80         IPU_ROTATE_HORIZ_FLIP,
  81         IPU_ROTATE_180,
  82         IPU_ROTATE_90_RIGHT,
  83         IPU_ROTATE_90_RIGHT_VFLIP,
  84         IPU_ROTATE_90_RIGHT_HFLIP,
  85         IPU_ROTATE_90_LEFT,
  86 };
  87
  88 enum ipu_color_space {
  89         IPUV3_COLORSPACE_RGB,
  90         IPUV3_COLORSPACE_YUV,
  91         IPUV3_COLORSPACE_UNKNOWN,
  92 };
  93
  94 struct ipuv3_channel;
  95
  96 enum ipu_channel_irq {
  97         IPU_IRQ_EOF = 0,
  98         IPU_IRQ_NFACK = 64,
  99         IPU_IRQ_NFB4EOF = 128,
 100         IPU_IRQ_EOS = 192,
 101 };
 102
 103 /*
 104  * Enumeration of IDMAC channels
 105  */
 106 #define IPUV3_CHANNEL_CSI0                       0
 107 #define IPUV3_CHANNEL_CSI1                       1
 108 #define IPUV3_CHANNEL_CSI2                       2
 109 #define IPUV3_CHANNEL_CSI3                       3
 110 #define IPUV3_CHANNEL_VDI_MEM_IC_VF              5
 111 #define IPUV3_CHANNEL_MEM_IC_PP                 11
 112 #define IPUV3_CHANNEL_MEM_IC_PRP_VF             12
 113 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF           14
 114 #define IPUV3_CHANNEL_G_MEM_IC_PP               15
 115 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM            20
 116 #define IPUV3_CHANNEL_IC_PRP_VF_MEM             21
 117 #define IPUV3_CHANNEL_IC_PP_MEM                 22
 118 #define IPUV3_CHANNEL_MEM_BG_SYNC               23
 119 #define IPUV3_CHANNEL_MEM_BG_ASYNC              24
 120 #define IPUV3_CHANNEL_MEM_FG_SYNC               27
 121 #define IPUV3_CHANNEL_MEM_DC_SYNC               28
 122 #define IPUV3_CHANNEL_MEM_FG_ASYNC              29
 123 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA         31
 124 #define IPUV3_CHANNEL_MEM_DC_ASYNC              41
 125 #define IPUV3_CHANNEL_MEM_ROT_ENC               45
 126 #define IPUV3_CHANNEL_MEM_ROT_VF                46
 127 #define IPUV3_CHANNEL_MEM_ROT_PP                47
 128 #define IPUV3_CHANNEL_ROT_ENC_MEM               48
 129 #define IPUV3_CHANNEL_ROT_VF_MEM                49
 130 #define IPUV3_CHANNEL_ROT_PP_MEM                50
 131 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA         51
 132
 133 int ipu_map_irq(struct ipu_soc *ipu, int irq);
 134 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
 135                 enum ipu_channel_irq irq);
 136
 137 #define IPU_IRQ_DP_SF_START             (448 + 2)
 138 #define IPU_IRQ_DP_SF_END               (448 + 3)
 139 #define IPU_IRQ_BG_SF_END               IPU_IRQ_DP_SF_END,
 140 #define IPU_IRQ_DC_FC_0                 (448 + 8)
 141 #define IPU_IRQ_DC_FC_1                 (448 + 9)
 142 #define IPU_IRQ_DC_FC_2                 (448 + 10)
 143 #define IPU_IRQ_DC_FC_3                 (448 + 11)
 144 #define IPU_IRQ_DC_FC_4                 (448 + 12)
 145 #define IPU_IRQ_DC_FC_6                 (448 + 13)
 146 #define IPU_IRQ_VSYNC_PRE_0             (448 + 14)
 147 #define IPU_IRQ_VSYNC_PRE_1             (448 + 15)
 148
 149 /*
 150  * IPU Common functions
 151  */
 152 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
 153 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
 154 void ipu_dump(struct ipu_soc *ipu);
 155
 156 /*
 157  * IPU Image DMA Controller (idmac) functions
 158  */
 159 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
 160 void ipu_idmac_put(struct ipuv3_channel *);
 161
 162 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
 163 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
 164 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
 165 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
 166 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
 167
 168 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 169                 bool doublebuffer);
 170 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
 171 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
 172 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
 173 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
 174
 175 /*
 176  * IPU Channel Parameter Memory (cpmem) functions
 177  */
 178 struct ipu_rgb {
 179         struct fb_bitfield      red;
 180         struct fb_bitfield      green;
 181         struct fb_bitfield      blue;
 182         struct fb_bitfield      transp;
 183         int                     bits_per_pixel;
 184 };
 185
 186 struct ipu_image {
 187         struct v4l2_pix_format pix;
 188         struct v4l2_rect rect;
 189         dma_addr_t phys0;
 190         dma_addr_t phys1;
 191 };
 192
 193 void ipu_cpmem_zero(struct ipuv3_channel *ch);
 194 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
 195 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
 196 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
 197 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
 198 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
 199 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
 200 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
 201 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
 202 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
 203                             enum ipu_rotate_mode rot);
 204 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
 205                              const struct ipu_rgb *rgb);
 206 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
 207 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
 208 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
 209                                    u32 pixel_format, int stride,
 210                                    int u_offset, int v_offset);
 211 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
 212                               u32 pixel_format, int stride, int height);
 213 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
 214 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
 215 void ipu_cpmem_dump(struct ipuv3_channel *ch);
 216
 217 /*
 218  * IPU Display Controller (dc) functions
 219  */
 220 struct ipu_dc;
 221 struct ipu_di;
 222 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
 223 void ipu_dc_put(struct ipu_dc *dc);
 224 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 225                 u32 pixel_fmt, u32 width);
 226 void ipu_dc_enable(struct ipu_soc *ipu);
 227 void ipu_dc_enable_channel(struct ipu_dc *dc);
 228 void ipu_dc_disable_channel(struct ipu_dc *dc);
 229 void ipu_dc_disable(struct ipu_soc *ipu);
 230
 231 /*
 232  * IPU Display Interface (di) functions
 233  */
 234 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
 235 void ipu_di_put(struct ipu_di *);
 236 int ipu_di_disable(struct ipu_di *);
 237 int ipu_di_enable(struct ipu_di *);
 238 int ipu_di_get_num(struct ipu_di *);
 239 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
 240
 241 /*
 242  * IPU Display Multi FIFO Controller (dmfc) functions
 243  */
 244 struct dmfc_channel;
 245 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
 246 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
 247 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
 248                 unsigned long bandwidth_mbs, int burstsize);
 249 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
 250 int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
 251 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
 252 void ipu_dmfc_put(struct dmfc_channel *dmfc);
 253
 254 /*
 255  * IPU Display Processor (dp) functions
 256  */
 257 #define IPU_DP_FLOW_SYNC_BG     0
 258 #define IPU_DP_FLOW_SYNC_FG     1
 259 #define IPU_DP_FLOW_ASYNC0_BG   2
 260 #define IPU_DP_FLOW_ASYNC0_FG   3
 261 #define IPU_DP_FLOW_ASYNC1_BG   4
 262 #define IPU_DP_FLOW_ASYNC1_FG   5
 263
 264 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
 265 void ipu_dp_put(struct ipu_dp *);
 266 int ipu_dp_enable(struct ipu_soc *ipu);
 267 int ipu_dp_enable_channel(struct ipu_dp *dp);
 268 void ipu_dp_disable_channel(struct ipu_dp *dp);
 269 void ipu_dp_disable(struct ipu_soc *ipu);
 270 int ipu_dp_setup_channel(struct ipu_dp *dp,
 271                 enum ipu_color_space in, enum ipu_color_space out);
 272 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
 273 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
 274                 bool bg_chan);
 275
 276 /*
 277  * IPU CMOS Sensor Interface (csi) functions
 278  */
 279 struct ipu_csi;
 280 int ipu_csi_init_interface(struct ipu_csi *csi,
 281                            struct v4l2_mbus_config *mbus_cfg,
 282                            struct v4l2_mbus_framefmt *mbus_fmt);
 283 bool ipu_csi_is_interlaced(struct ipu_csi *csi);
 284 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
 285 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
 286 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
 287                                 u32 r_value, u32 g_value, u32 b_value,
 288                                 u32 pix_clk);
 289 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
 290                               struct v4l2_mbus_framefmt *mbus_fmt);
 291 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
 292                           u32 max_ratio, u32 id);
 293 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
 294 int ipu_csi_enable(struct ipu_csi *csi);
 295 int ipu_csi_disable(struct ipu_csi *csi);
 296 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
 297 void ipu_csi_put(struct ipu_csi *csi);
 298 void ipu_csi_dump(struct ipu_csi *csi);
 299
 300 /*
 301  * IPU Image Converter (ic) functions
 302  */
 303 enum ipu_ic_task {
 304         IC_TASK_ENCODER,
 305         IC_TASK_VIEWFINDER,
 306         IC_TASK_POST_PROCESSOR,
 307         IC_NUM_TASKS,
 308 };
 309
 310 struct ipu_ic;
 311 int ipu_ic_task_init(struct ipu_ic *ic,
 312                      int in_width, int in_height,
 313                      int out_width, int out_height,
 314                      enum ipu_color_space in_cs,
 315                      enum ipu_color_space out_cs);
 316 int ipu_ic_task_graphics_init(struct ipu_ic *ic,
 317                               enum ipu_color_space in_g_cs,
 318                               bool galpha_en, u32 galpha,
 319                               bool colorkey_en, u32 colorkey);
 320 void ipu_ic_task_enable(struct ipu_ic *ic);
 321 void ipu_ic_task_disable(struct ipu_ic *ic);
 322 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
 323                           u32 width, u32 height, int burst_size,
 324                           enum ipu_rotate_mode rot);
 325 int ipu_ic_enable(struct ipu_ic *ic);
 326 int ipu_ic_disable(struct ipu_ic *ic);
 327 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
 328 void ipu_ic_put(struct ipu_ic *ic);
 329 void ipu_ic_dump(struct ipu_ic *ic);
 330
 331 /*
 332  * IPU Sensor Multiple FIFO Controller (SMFC) functions
 333  */
 334 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
 335 void ipu_smfc_put(struct ipu_smfc *smfc);
 336 int ipu_smfc_enable(struct ipu_smfc *smfc);
 337 int ipu_smfc_disable(struct ipu_smfc *smfc);
 338 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
 339 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
 340 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
 341
 342 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
 343 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
 344 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
 345 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
 346 bool ipu_pixelformat_is_planar(u32 pixelformat);
 347 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 348                             bool hflip, bool vflip);
 349 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
 350                             bool hflip, bool vflip);
 351
 352 struct ipu_client_platformdata {
 353         int csi;
 354         int di;
 355         int dc;
 356         int dp;
 357         int dmfc;
 358         int dma[2];
 359 };
 360
 361 #endif /* __DRM_IPU_H__ */