arch/arm/mach-omap2/id.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * linux/arch/arm/mach-omap2/id.c
   4  *
   5  * OMAP2 CPU identification code
   6  *
   7  * Copyright (C) 2005 Nokia Corporation
   8  * Written by Tony Lindgren <tony@atomide.com>
   9  *
  10  * Copyright (C) 2009-11 Texas Instruments
  11  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/random.h>
  19 #include <linux/slab.h>
  20
  21 #ifdef CONFIG_SOC_BUS
  22 #include <linux/sys_soc.h>
  23 #endif
  24
  25 #include <asm/cputype.h>
  26
  27 #include "common.h"
  28
  29 #include "id.h"
  30
  31 #include "soc.h"
  32 #include "control.h"
  33
  34 #define OMAP4_SILICON_TYPE_STANDARD             0x01
  35 #define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
  36
  37 #define OMAP_SOC_MAX_NAME_LENGTH                16
  38
  39 static unsigned int omap_revision;
  40 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
  41 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
  42 u32 omap_features;
  43
  44 unsigned int omap_rev(void)
  45 {
  46         return omap_revision;
  47 }
  48 EXPORT_SYMBOL(omap_rev);
  49
  50 int omap_type(void)
  51 {
  52         static u32 val = OMAP2_DEVICETYPE_MASK;
  53
  54         if (val < OMAP2_DEVICETYPE_MASK)
  55                 return val;
  56
  57         if (soc_is_omap24xx()) {
  58                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  59         } else if (soc_is_ti81xx()) {
  60                 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
  61         } else if (soc_is_am33xx() || soc_is_am43xx()) {
  62                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
  63         } else if (soc_is_omap34xx()) {
  64                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  65         } else if (soc_is_omap44xx()) {
  66                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  67         } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
  68                 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
  69                 val &= OMAP5_DEVICETYPE_MASK;
  70                 val >>= 6;
  71                 goto out;
  72         } else {
  73                 pr_err("Cannot detect omap type!\n");
  74                 goto out;
  75         }
  76
  77         val &= OMAP2_DEVICETYPE_MASK;
  78         val >>= 8;
  79
  80 out:
  81         return val;
  82 }
  83 EXPORT_SYMBOL(omap_type);
  84
  85
  86 /*----------------------------------------------------------------------------*/
  87
  88 #define OMAP_TAP_IDCODE         0x0204
  89 #define OMAP_TAP_DIE_ID_0       0x0218
  90 #define OMAP_TAP_DIE_ID_1       0x021C
  91 #define OMAP_TAP_DIE_ID_2       0x0220
  92 #define OMAP_TAP_DIE_ID_3       0x0224
  93
  94 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  95 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  96 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
  97 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
  98
  99 #define read_tap_reg(reg)       readl_relaxed(tap_base  + (reg))
 100
 101 struct omap_id {
 102         u16     hawkeye;        /* Silicon type (Hawkeye id) */
 103         u8      dev;            /* Device type from production_id reg */
 104         u32     type;           /* Combined type id copied to omap_revision */
 105 };
 106
 107 /* Register values to detect the OMAP version */
 108 static struct omap_id omap_ids[] __initdata = {
 109         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
 110         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
 111         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
 112         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
 113         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
 114         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
 115 };
 116
 117 static void __iomem *tap_base;
 118 static u16 tap_prod_id;
 119
 120 void omap_get_die_id(struct omap_die_id *odi)
 121 {
 122         if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
 123                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 124                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 125                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 126                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 127
 128                 return;
 129         }
 130         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 131         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 132         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 133         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 134 }
 135
 136 static int __init omap_feed_randpool(void)
 137 {
 138         struct omap_die_id odi;
 139
 140         /* Throw the die ID into the entropy pool at boot */
 141         omap_get_die_id(&odi);
 142         add_device_randomness(&odi, sizeof(odi));
 143         return 0;
 144 }
 145 omap_device_initcall(omap_feed_randpool);
 146
 147 void __init omap2xxx_check_revision(void)
 148 {
 149         int i, j;
 150         u32 idcode, prod_id;
 151         u16 hawkeye;
 152         u8  dev_type, rev;
 153         struct omap_die_id odi;
 154
 155         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 156         prod_id = read_tap_reg(tap_prod_id);
 157         hawkeye = (idcode >> 12) & 0xffff;
 158         rev = (idcode >> 28) & 0x0f;
 159         dev_type = (prod_id >> 16) & 0x0f;
 160         omap_get_die_id(&odi);
 161
 162         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 163                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 164         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 165         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 166                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 167         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 168         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 169         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 170                  prod_id, dev_type);
 171
 172         /* Check hawkeye ids */
 173         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 174                 if (hawkeye == omap_ids[i].hawkeye)
 175                         break;
 176         }
 177
 178         if (i == ARRAY_SIZE(omap_ids)) {
 179                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 180                 return;
 181         }
 182
 183         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 184                 if (dev_type == omap_ids[j].dev)
 185                         break;
 186         }
 187
 188         if (j == ARRAY_SIZE(omap_ids)) {
 189                 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
 190                        omap_ids[i].type >> 16);
 191                 j = i;
 192         }
 193
 194         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 195         sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
 196
 197         pr_info("%s", soc_name);
 198         if ((omap_rev() >> 8) & 0x0f)
 199                 pr_cont("%s", soc_rev);
 200         pr_cont("\n");
 201 }
 202
 203 #define OMAP3_SHOW_FEATURE(feat)                \
 204         if (omap3_has_ ##feat())                \
 205                 n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
 206
 207 static void __init omap3_cpuinfo(void)
 208 {
 209         const char *cpu_name;
 210         char buf[64];
 211         int n = 0;
 212
 213         memset(buf, 0, sizeof(buf));
 214
 215         /*
 216          * OMAP3430 and OMAP3530 are assumed to be same.
 217          *
 218          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 219          * on available features. Upon detection, update the CPU id
 220          * and CPU class bits.
 221          */
 222         if (soc_is_omap3630()) {
 223                 if (omap3_has_iva() && omap3_has_sgx()) {
 224                         cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
 225                 } else if (omap3_has_iva()) {
 226                         cpu_name = "DM3725";
 227                 } else if (omap3_has_sgx()) {
 228                         cpu_name = "OMAP3615/AM3715";
 229                 } else {
 230                         cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
 231                 }
 232         } else if (soc_is_am35xx()) {
 233                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 234         } else if (soc_is_ti816x()) {
 235                 cpu_name = "TI816X";
 236         } else if (soc_is_am335x()) {
 237                 cpu_name =  "AM335X";
 238         } else if (soc_is_am437x()) {
 239                 cpu_name =  "AM437x";
 240         } else if (soc_is_ti814x()) {
 241                 cpu_name = "TI814X";
 242         } else if (omap3_has_iva() && omap3_has_sgx()) {
 243                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 244                 cpu_name = "OMAP3430/3530";
 245         } else if (omap3_has_iva()) {
 246                 cpu_name = "OMAP3525";
 247         } else if (omap3_has_sgx()) {
 248                 cpu_name = "OMAP3515";
 249         } else {
 250                 cpu_name = "OMAP3503";
 251         }
 252
 253         scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
 254
 255         /* Print verbose information */
 256         n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
 257
 258         OMAP3_SHOW_FEATURE(l2cache);
 259         OMAP3_SHOW_FEATURE(iva);
 260         OMAP3_SHOW_FEATURE(sgx);
 261         OMAP3_SHOW_FEATURE(neon);
 262         OMAP3_SHOW_FEATURE(isp);
 263         OMAP3_SHOW_FEATURE(192mhz_clk);
 264         if (*(buf + n - 1) == ' ')
 265                 n--;
 266         n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
 267         pr_info("%s", buf);
 268 }
 269
 270 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 271         if (((status & OMAP3_ ##feat## _MASK)                           \
 272                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 273                 omap_features |= OMAP3_HAS_ ##feat;                     \
 274         }
 275
 276 void __init omap3xxx_check_features(void)
 277 {
 278         u32 status;
 279
 280         omap_features = 0;
 281
 282         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 283
 284         OMAP3_CHECK_FEATURE(status, L2CACHE);
 285         OMAP3_CHECK_FEATURE(status, IVA);
 286         OMAP3_CHECK_FEATURE(status, SGX);
 287         OMAP3_CHECK_FEATURE(status, NEON);
 288         OMAP3_CHECK_FEATURE(status, ISP);
 289         if (soc_is_omap3630())
 290                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 291         if (soc_is_omap3430() || soc_is_omap3630())
 292                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 293         if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 294             omap_rev() == OMAP3430_REV_ES3_1_2)
 295                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 296
 297         omap_features |= OMAP3_HAS_SDRC;
 298
 299         /*
 300          * am35x fixups:
 301          * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
 302          *   reserved and therefore return 0 when read.  Unfortunately,
 303          *   OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
 304          *   mean that a feature is present even though it isn't so clear
 305          *   the incorrectly set feature bits.
 306          */
 307         if (soc_is_am35xx())
 308                 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
 309
 310         /*
 311          * TODO: Get additional info (where applicable)
 312          *       e.g. Size of L2 cache.
 313          */
 314
 315         omap3_cpuinfo();
 316 }
 317
 318 void __init omap4xxx_check_features(void)
 319 {
 320         u32 si_type;
 321
 322         si_type =
 323         (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
 324
 325         if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
 326                 omap_features = OMAP4_HAS_PERF_SILICON;
 327 }
 328
 329 void __init ti81xx_check_features(void)
 330 {
 331         omap_features = OMAP3_HAS_NEON;
 332         omap3_cpuinfo();
 333 }
 334
 335 void __init am33xx_check_features(void)
 336 {
 337         u32 status;
 338
 339         omap_features = OMAP3_HAS_NEON;
 340
 341         status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
 342         if (status & AM33XX_SGX_MASK)
 343                 omap_features |= OMAP3_HAS_SGX;
 344
 345         omap3_cpuinfo();
 346 }
 347
 348 void __init omap3xxx_check_revision(void)
 349 {
 350         const char *cpu_rev;
 351         u32 cpuid, idcode;
 352         u16 hawkeye;
 353         u8 rev;
 354
 355         /*
 356          * We cannot access revision registers on ES1.0.
 357          * If the processor type is Cortex-A8 and the revision is 0x0
 358          * it means its Cortex r0p0 which is 3430 ES1.0.
 359          */
 360         cpuid = read_cpuid_id();
 361         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 362                 omap_revision = OMAP3430_REV_ES1_0;
 363                 cpu_rev = "1.0";
 364                 return;
 365         }
 366
 367         /*
 368          * Detection for 34xx ES2.0 and above can be done with just
 369          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 370          * Note that rev does not map directly to our defined processor
 371          * revision numbers as ES1.0 uses value 0.
 372          */
 373         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 374         hawkeye = (idcode >> 12) & 0xffff;
 375         rev = (idcode >> 28) & 0xff;
 376
 377         switch (hawkeye) {
 378         case 0xb7ae:
 379                 /* Handle 34xx/35xx devices */
 380                 switch (rev) {
 381                 case 0: /* Take care of early samples */
 382                 case 1:
 383                         omap_revision = OMAP3430_REV_ES2_0;
 384                         cpu_rev = "2.0";
 385                         break;
 386                 case 2:
 387                         omap_revision = OMAP3430_REV_ES2_1;
 388                         cpu_rev = "2.1";
 389                         break;
 390                 case 3:
 391                         omap_revision = OMAP3430_REV_ES3_0;
 392                         cpu_rev = "3.0";
 393                         break;
 394                 case 4:
 395                         omap_revision = OMAP3430_REV_ES3_1;
 396                         cpu_rev = "3.1";
 397                         break;
 398                 case 7:
 399                 default:
 400                         /* Use the latest known revision as default */
 401                         omap_revision = OMAP3430_REV_ES3_1_2;
 402                         cpu_rev = "3.1.2";
 403                 }
 404                 break;
 405         case 0xb868:
 406                 /*
 407                  * Handle OMAP/AM 3505/3517 devices
 408                  *
 409                  * Set the device to be OMAP3517 here. Actual device
 410                  * is identified later based on the features.
 411                  */
 412                 switch (rev) {
 413                 case 0:
 414                         omap_revision = AM35XX_REV_ES1_0;
 415                         cpu_rev = "1.0";
 416                         break;
 417                 case 1:
 418                 default:
 419                         omap_revision = AM35XX_REV_ES1_1;
 420                         cpu_rev = "1.1";
 421                 }
 422                 break;
 423         case 0xb891:
 424                 /* Handle 36xx devices */
 425
 426                 switch(rev) {
 427                 case 0: /* Take care of early samples */
 428                         omap_revision = OMAP3630_REV_ES1_0;
 429                         cpu_rev = "1.0";
 430                         break;
 431                 case 1:
 432                         omap_revision = OMAP3630_REV_ES1_1;
 433                         cpu_rev = "1.1";
 434                         break;
 435                 case 2:
 436                 default:
 437                         omap_revision = OMAP3630_REV_ES1_2;
 438                         cpu_rev = "1.2";
 439                 }
 440                 break;
 441         case 0xb81e:
 442                 switch (rev) {
 443                 case 0:
 444                         omap_revision = TI8168_REV_ES1_0;
 445                         cpu_rev = "1.0";
 446                         break;
 447                 case 1:
 448                         omap_revision = TI8168_REV_ES1_1;
 449                         cpu_rev = "1.1";
 450                         break;
 451                 case 2:
 452                         omap_revision = TI8168_REV_ES2_0;
 453                         cpu_rev = "2.0";
 454                         break;
 455                 case 3:
 456                 default:
 457                         omap_revision = TI8168_REV_ES2_1;
 458                         cpu_rev = "2.1";
 459                 }
 460                 break;
 461         case 0xb944:
 462                 switch (rev) {
 463                 case 0:
 464                         omap_revision = AM335X_REV_ES1_0;
 465                         cpu_rev = "1.0";
 466                         break;
 467                 case 1:
 468                         omap_revision = AM335X_REV_ES2_0;
 469                         cpu_rev = "2.0";
 470                         break;
 471                 case 2:
 472                 default:
 473                         omap_revision = AM335X_REV_ES2_1;
 474                         cpu_rev = "2.1";
 475                         break;
 476                 }
 477                 break;
 478         case 0xb98c:
 479                 switch (rev) {
 480                 case 0:
 481                         omap_revision = AM437X_REV_ES1_0;
 482                         cpu_rev = "1.0";
 483                         break;
 484                 case 1:
 485                         omap_revision = AM437X_REV_ES1_1;
 486                         cpu_rev = "1.1";
 487                         break;
 488                 case 2:
 489                 default:
 490                         omap_revision = AM437X_REV_ES1_2;
 491                         cpu_rev = "1.2";
 492                         break;
 493                 }
 494                 break;
 495         case 0xb8f2:
 496         case 0xb968:
 497                 switch (rev) {
 498                 case 0:
 499                 case 1:
 500                         omap_revision = TI8148_REV_ES1_0;
 501                         cpu_rev = "1.0";
 502                         break;
 503                 case 2:
 504                         omap_revision = TI8148_REV_ES2_0;
 505                         cpu_rev = "2.0";
 506                         break;
 507                 case 3:
 508                 default:
 509                         omap_revision = TI8148_REV_ES2_1;
 510                         cpu_rev = "2.1";
 511                         break;
 512                 }
 513                 break;
 514         default:
 515                 /* Unknown default to latest silicon rev as default */
 516                 omap_revision = OMAP3630_REV_ES1_2;
 517                 cpu_rev = "1.2";
 518                 pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
 519                         hawkeye);
 520         }
 521         sprintf(soc_rev, "ES%s", cpu_rev);
 522 }
 523
 524 void __init omap4xxx_check_revision(void)
 525 {
 526         u32 idcode;
 527         u16 hawkeye;
 528         u8 rev;
 529
 530         /*
 531          * The IC rev detection is done with hawkeye and rev.
 532          * Note that rev does not map directly to defined processor
 533          * revision numbers as ES1.0 uses value 0.
 534          */
 535         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 536         hawkeye = (idcode >> 12) & 0xffff;
 537         rev = (idcode >> 28) & 0xf;
 538
 539         /*
 540          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 541          * Use ARM register to detect the correct ES version
 542          */
 543         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
 544                 idcode = read_cpuid_id();
 545                 rev = (idcode & 0xf) - 1;
 546         }
 547
 548         switch (hawkeye) {
 549         case 0xb852:
 550                 switch (rev) {
 551                 case 0:
 552                         omap_revision = OMAP4430_REV_ES1_0;
 553                         break;
 554                 case 1:
 555                 default:
 556                         omap_revision = OMAP4430_REV_ES2_0;
 557                 }
 558                 break;
 559         case 0xb95c:
 560                 switch (rev) {
 561                 case 3:
 562                         omap_revision = OMAP4430_REV_ES2_1;
 563                         break;
 564                 case 4:
 565                         omap_revision = OMAP4430_REV_ES2_2;
 566                         break;
 567                 case 6:
 568                 default:
 569                         omap_revision = OMAP4430_REV_ES2_3;
 570                 }
 571                 break;
 572         case 0xb94e:
 573                 switch (rev) {
 574                 case 0:
 575                         omap_revision = OMAP4460_REV_ES1_0;
 576                         break;
 577                 case 2:
 578                 default:
 579                         omap_revision = OMAP4460_REV_ES1_1;
 580                         break;
 581                 }
 582                 break;
 583         case 0xb975:
 584                 switch (rev) {
 585                 case 0:
 586                 default:
 587                         omap_revision = OMAP4470_REV_ES1_0;
 588                         break;
 589                 }
 590                 break;
 591         default:
 592                 /* Unknown default to latest silicon rev as default */
 593                 omap_revision = OMAP4430_REV_ES2_3;
 594         }
 595
 596         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 597         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 598                                                 (omap_rev() >> 8) & 0xf);
 599         pr_info("%s %s\n", soc_name, soc_rev);
 600 }
 601
 602 void __init omap5xxx_check_revision(void)
 603 {
 604         u32 idcode;
 605         u16 hawkeye;
 606         u8 rev;
 607
 608         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 609         hawkeye = (idcode >> 12) & 0xffff;
 610         rev = (idcode >> 28) & 0xff;
 611         switch (hawkeye) {
 612         case 0xb942:
 613                 switch (rev) {
 614                 case 0:
 615                         /* No support for ES1.0 Test chip */
 616                         BUG();
 617                 case 1:
 618                 default:
 619                         omap_revision = OMAP5430_REV_ES2_0;
 620                 }
 621                 break;
 622
 623         case 0xb998:
 624                 switch (rev) {
 625                 case 0:
 626                         /* No support for ES1.0 Test chip */
 627                         BUG();
 628                 case 1:
 629                 default:
 630                         omap_revision = OMAP5432_REV_ES2_0;
 631                 }
 632                 break;
 633
 634         default:
 635                 /* Unknown default to latest silicon rev as default*/
 636                 omap_revision = OMAP5430_REV_ES2_0;
 637         }
 638
 639         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 640         sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
 641
 642         pr_info("%s %s\n", soc_name, soc_rev);
 643 }
 644
 645 void __init dra7xxx_check_revision(void)
 646 {
 647         u32 idcode;
 648         u16 hawkeye;
 649         u8 rev, package;
 650         struct omap_die_id odi;
 651
 652         omap_get_die_id(&odi);
 653         package = (odi.id_2 >> 16) & 0x3;
 654         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 655         hawkeye = (idcode >> 12) & 0xffff;
 656         rev = (idcode >> 28) & 0xff;
 657         switch (hawkeye) {
 658         case 0xbb50:
 659                 switch (rev) {
 660                 case 0:
 661                 default:
 662                         switch (package) {
 663                         case 0x2:
 664                                 omap_revision = DRA762_ABZ_REV_ES1_0;
 665                                 break;
 666                         case 0x3:
 667                                 omap_revision = DRA762_ACD_REV_ES1_0;
 668                                 break;
 669                         default:
 670                                 omap_revision = DRA762_REV_ES1_0;
 671                                 break;
 672                         }
 673                         break;
 674                 }
 675                 break;
 676
 677         case 0xb990:
 678                 switch (rev) {
 679                 case 0:
 680                         omap_revision = DRA752_REV_ES1_0;
 681                         break;
 682                 case 1:
 683                         omap_revision = DRA752_REV_ES1_1;
 684                         break;
 685                 case 2:
 686                 default:
 687                         omap_revision = DRA752_REV_ES2_0;
 688                         break;
 689                 }
 690                 break;
 691
 692         case 0xb9bc:
 693                 switch (rev) {
 694                 case 0:
 695                         omap_revision = DRA722_REV_ES1_0;
 696                         break;
 697                 case 1:
 698                         omap_revision = DRA722_REV_ES2_0;
 699                         break;
 700                 case 2:
 701                 default:
 702                         omap_revision = DRA722_REV_ES2_1;
 703                         break;
 704                 }
 705                 break;
 706
 707         default:
 708                 /* Unknown default to latest silicon rev as default*/
 709                 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
 710                         __func__, idcode, hawkeye, rev);
 711                 omap_revision = DRA752_REV_ES2_0;
 712         }
 713
 714         sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
 715         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 716                 (omap_rev() >> 8) & 0xf);
 717
 718         pr_info("%s %s\n", soc_name, soc_rev);
 719 }
 720
 721 /*
 722  * Set up things for map_io and processor detection later on. Gets called
 723  * pretty much first thing from board init. For multi-omap, this gets
 724  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 725  * detect the exact revision later on in omap2_detect_revision() once map_io
 726  * is done.
 727  */
 728 void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
 729 {
 730         omap_revision = class;
 731         tap_base = tap;
 732
 733         /* XXX What is this intended to do? */
 734         if (soc_is_omap34xx())
 735                 tap_prod_id = 0x0210;
 736         else
 737                 tap_prod_id = 0x0208;
 738 }
 739
 740 #ifdef CONFIG_SOC_BUS
 741
 742 static const char * const omap_types[] = {
 743         [OMAP2_DEVICE_TYPE_TEST]        = "TST",
 744         [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
 745         [OMAP2_DEVICE_TYPE_SEC]         = "HS",
 746         [OMAP2_DEVICE_TYPE_GP]          = "GP",
 747         [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
 748 };
 749
 750 static const char * __init omap_get_family(void)
 751 {
 752         if (soc_is_omap24xx())
 753                 return kasprintf(GFP_KERNEL, "OMAP2");
 754         else if (soc_is_omap34xx())
 755                 return kasprintf(GFP_KERNEL, "OMAP3");
 756         else if (soc_is_omap44xx())
 757                 return kasprintf(GFP_KERNEL, "OMAP4");
 758         else if (soc_is_omap54xx())
 759                 return kasprintf(GFP_KERNEL, "OMAP5");
 760         else if (soc_is_am33xx() || soc_is_am335x())
 761                 return kasprintf(GFP_KERNEL, "AM33xx");
 762         else if (soc_is_am43xx())
 763                 return kasprintf(GFP_KERNEL, "AM43xx");
 764         else if (soc_is_dra7xx())
 765                 return kasprintf(GFP_KERNEL, "DRA7");
 766         else
 767                 return kasprintf(GFP_KERNEL, "Unknown");
 768 }
 769
 770 static ssize_t
 771 type_show(struct device *dev, struct device_attribute *attr, char *buf)
 772 {
 773         return sprintf(buf, "%s\n", omap_types[omap_type()]);
 774 }
 775
 776 static DEVICE_ATTR_RO(type);
 777
 778 static struct attribute *omap_soc_attrs[] = {
 779         &dev_attr_type.attr,
 780         NULL
 781 };
 782
 783 ATTRIBUTE_GROUPS(omap_soc);
 784
 785 void __init omap_soc_device_init(void)
 786 {
 787         struct soc_device *soc_dev;
 788         struct soc_device_attribute *soc_dev_attr;
 789
 790         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 791         if (!soc_dev_attr)
 792                 return;
 793
 794         soc_dev_attr->machine  = soc_name;
 795         soc_dev_attr->family   = omap_get_family();
 796         soc_dev_attr->revision = soc_rev;
 797         soc_dev_attr->custom_attr_group = omap_soc_groups[0];
 798
 799         soc_dev = soc_device_register(soc_dev_attr);
 800         if (IS_ERR(soc_dev)) {
 801                 kfree(soc_dev_attr);
 802                 return;
 803         }
 804 }
 805 #endif /* CONFIG_SOC_BUS */