arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP54xx chips
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/power/smartreflex.h>
  19
  20 #include "omap_hwmod.h"
  21 #include "omap_hwmod_common_data.h"
  22 #include "cm1_54xx.h"
  23 #include "cm2_54xx.h"
  24 #include "prm54xx.h"
  25
  26 /* Base offset for all OMAP5 interrupts external to MPUSS */
  27 #define OMAP54XX_IRQ_GIC_START  32
  28
  29 /*
  30  * IP blocks
  31  */
  32
  33 /*
  34  * 'dmm' class
  35  * instance(s): dmm
  36  */
  37 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  38         .name   = "dmm",
  39 };
  40
  41 /* dmm */
  42 static struct omap_hwmod omap54xx_dmm_hwmod = {
  43         .name           = "dmm",
  44         .class          = &omap54xx_dmm_hwmod_class,
  45         .clkdm_name     = "emif_clkdm",
  46         .prcm = {
  47                 .omap4 = {
  48                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  49                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  50                 },
  51         },
  52 };
  53
  54 /*
  55  * 'l3' class
  56  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  57  */
  58 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  59         .name   = "l3",
  60 };
  61
  62 /* l3_instr */
  63 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  64         .name           = "l3_instr",
  65         .class          = &omap54xx_l3_hwmod_class,
  66         .clkdm_name     = "l3instr_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  71                         .modulemode   = MODULEMODE_HWCTRL,
  72                 },
  73         },
  74 };
  75
  76 /* l3_main_1 */
  77 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  78         .name           = "l3_main_1",
  79         .class          = &omap54xx_l3_hwmod_class,
  80         .clkdm_name     = "l3main1_clkdm",
  81         .prcm = {
  82                 .omap4 = {
  83                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  84                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  85                 },
  86         },
  87 };
  88
  89 /* l3_main_2 */
  90 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
  91         .name           = "l3_main_2",
  92         .class          = &omap54xx_l3_hwmod_class,
  93         .clkdm_name     = "l3main2_clkdm",
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /* l3_main_3 */
 103 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 104         .name           = "l3_main_3",
 105         .class          = &omap54xx_l3_hwmod_class,
 106         .clkdm_name     = "l3instr_clkdm",
 107         .prcm = {
 108                 .omap4 = {
 109                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 110                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 111                         .modulemode   = MODULEMODE_HWCTRL,
 112                 },
 113         },
 114 };
 115
 116 /*
 117  * 'l4' class
 118  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 119  */
 120 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 121         .name   = "l4",
 122 };
 123
 124 /* l4_cfg */
 125 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 126         .name           = "l4_cfg",
 127         .class          = &omap54xx_l4_hwmod_class,
 128         .clkdm_name     = "l4cfg_clkdm",
 129         .prcm = {
 130                 .omap4 = {
 131                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 132                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 133                 },
 134         },
 135 };
 136
 137 /* l4_per */
 138 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 139         .name           = "l4_per",
 140         .class          = &omap54xx_l4_hwmod_class,
 141         .clkdm_name     = "l4per_clkdm",
 142         .prcm = {
 143                 .omap4 = {
 144                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 145                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 146                 },
 147         },
 148 };
 149
 150 /* l4_wkup */
 151 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 152         .name           = "l4_wkup",
 153         .class          = &omap54xx_l4_hwmod_class,
 154         .clkdm_name     = "wkupaon_clkdm",
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 158                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 159                 },
 160         },
 161 };
 162
 163 /*
 164  * 'mpu_bus' class
 165  * instance(s): mpu_private
 166  */
 167 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 168         .name   = "mpu_bus",
 169 };
 170
 171 /* mpu_private */
 172 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 173         .name           = "mpu_private",
 174         .class          = &omap54xx_mpu_bus_hwmod_class,
 175         .clkdm_name     = "mpu_clkdm",
 176         .prcm = {
 177                 .omap4 = {
 178                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 179                 },
 180         },
 181 };
 182
 183 /*
 184  * 'emif' class
 185  * external memory interface no1 (wrapper)
 186  */
 187
 188 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 189         .rev_offs       = 0x0000,
 190 };
 191
 192 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 193         .name   = "emif",
 194         .sysc   = &omap54xx_emif_sysc,
 195 };
 196
 197 /* emif1 */
 198 static struct omap_hwmod omap54xx_emif1_hwmod = {
 199         .name           = "emif1",
 200         .class          = &omap54xx_emif_hwmod_class,
 201         .clkdm_name     = "emif_clkdm",
 202         .flags          = HWMOD_INIT_NO_IDLE,
 203         .main_clk       = "dpll_core_h11x2_ck",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 207                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 208                         .modulemode   = MODULEMODE_HWCTRL,
 209                 },
 210         },
 211 };
 212
 213 /* emif2 */
 214 static struct omap_hwmod omap54xx_emif2_hwmod = {
 215         .name           = "emif2",
 216         .class          = &omap54xx_emif_hwmod_class,
 217         .clkdm_name     = "emif_clkdm",
 218         .flags          = HWMOD_INIT_NO_IDLE,
 219         .main_clk       = "dpll_core_h11x2_ck",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 224                         .modulemode   = MODULEMODE_HWCTRL,
 225                 },
 226         },
 227 };
 228
 229
 230
 231
 232 /*
 233  * 'mpu' class
 234  * mpu sub-system
 235  */
 236
 237 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
 238         .name   = "mpu",
 239 };
 240
 241 /* mpu */
 242 static struct omap_hwmod omap54xx_mpu_hwmod = {
 243         .name           = "mpu",
 244         .class          = &omap54xx_mpu_hwmod_class,
 245         .clkdm_name     = "mpu_clkdm",
 246         .flags          = HWMOD_INIT_NO_IDLE,
 247         .main_clk       = "dpll_mpu_m2_ck",
 248         .prcm = {
 249                 .omap4 = {
 250                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 251                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
 252                 },
 253         },
 254 };
 255
 256 /*
 257  * 'sata' class
 258  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
 259  */
 260
 261 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
 262         .rev_offs       = 0x00fc,
 263         .sysc_offs      = 0x0000,
 264         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 265         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 266                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 267                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 268         .sysc_fields    = &omap_hwmod_sysc_type2,
 269 };
 270
 271 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
 272         .name   = "sata",
 273         .sysc   = &omap54xx_sata_sysc,
 274 };
 275
 276 /* sata */
 277 static struct omap_hwmod omap54xx_sata_hwmod = {
 278         .name           = "sata",
 279         .class          = &omap54xx_sata_hwmod_class,
 280         .clkdm_name     = "l3init_clkdm",
 281         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 282         .main_clk       = "func_48m_fclk",
 283         .mpu_rt_idx     = 1,
 284         .prcm = {
 285                 .omap4 = {
 286                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
 287                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
 288                         .modulemode   = MODULEMODE_SWCTRL,
 289                 },
 290         },
 291 };
 292
 293 /* l4_cfg -> sata */
 294 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
 295         .master         = &omap54xx_l4_cfg_hwmod,
 296         .slave          = &omap54xx_sata_hwmod,
 297         .clk            = "l3_iclk_div",
 298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 299 };
 300
 301 /*
 302  * Interfaces
 303  */
 304
 305 /* l3_main_1 -> dmm */
 306 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
 307         .master         = &omap54xx_l3_main_1_hwmod,
 308         .slave          = &omap54xx_dmm_hwmod,
 309         .clk            = "l3_iclk_div",
 310         .user           = OCP_USER_SDMA,
 311 };
 312
 313 /* l3_main_3 -> l3_instr */
 314 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
 315         .master         = &omap54xx_l3_main_3_hwmod,
 316         .slave          = &omap54xx_l3_instr_hwmod,
 317         .clk            = "l3_iclk_div",
 318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 319 };
 320
 321 /* l3_main_2 -> l3_main_1 */
 322 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
 323         .master         = &omap54xx_l3_main_2_hwmod,
 324         .slave          = &omap54xx_l3_main_1_hwmod,
 325         .clk            = "l3_iclk_div",
 326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 327 };
 328
 329 /* l4_cfg -> l3_main_1 */
 330 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
 331         .master         = &omap54xx_l4_cfg_hwmod,
 332         .slave          = &omap54xx_l3_main_1_hwmod,
 333         .clk            = "l3_iclk_div",
 334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 335 };
 336
 337 /* mpu -> l3_main_1 */
 338 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
 339         .master         = &omap54xx_mpu_hwmod,
 340         .slave          = &omap54xx_l3_main_1_hwmod,
 341         .clk            = "l3_iclk_div",
 342         .user           = OCP_USER_MPU,
 343 };
 344
 345 /* l3_main_1 -> l3_main_2 */
 346 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
 347         .master         = &omap54xx_l3_main_1_hwmod,
 348         .slave          = &omap54xx_l3_main_2_hwmod,
 349         .clk            = "l3_iclk_div",
 350         .user           = OCP_USER_MPU,
 351 };
 352
 353 /* l4_cfg -> l3_main_2 */
 354 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
 355         .master         = &omap54xx_l4_cfg_hwmod,
 356         .slave          = &omap54xx_l3_main_2_hwmod,
 357         .clk            = "l3_iclk_div",
 358         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 359 };
 360
 361 /* l3_main_1 -> l3_main_3 */
 362 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
 363         .master         = &omap54xx_l3_main_1_hwmod,
 364         .slave          = &omap54xx_l3_main_3_hwmod,
 365         .clk            = "l3_iclk_div",
 366         .user           = OCP_USER_MPU,
 367 };
 368
 369 /* l3_main_2 -> l3_main_3 */
 370 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
 371         .master         = &omap54xx_l3_main_2_hwmod,
 372         .slave          = &omap54xx_l3_main_3_hwmod,
 373         .clk            = "l3_iclk_div",
 374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 375 };
 376
 377 /* l4_cfg -> l3_main_3 */
 378 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
 379         .master         = &omap54xx_l4_cfg_hwmod,
 380         .slave          = &omap54xx_l3_main_3_hwmod,
 381         .clk            = "l3_iclk_div",
 382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 383 };
 384
 385 /* l3_main_1 -> l4_cfg */
 386 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
 387         .master         = &omap54xx_l3_main_1_hwmod,
 388         .slave          = &omap54xx_l4_cfg_hwmod,
 389         .clk            = "l4_root_clk_div",
 390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 391 };
 392
 393 /* l3_main_2 -> l4_per */
 394 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
 395         .master         = &omap54xx_l3_main_2_hwmod,
 396         .slave          = &omap54xx_l4_per_hwmod,
 397         .clk            = "l4_root_clk_div",
 398         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 399 };
 400
 401 /* l3_main_1 -> l4_wkup */
 402 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
 403         .master         = &omap54xx_l3_main_1_hwmod,
 404         .slave          = &omap54xx_l4_wkup_hwmod,
 405         .clk            = "wkupaon_iclk_mux",
 406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 407 };
 408
 409 /* mpu -> mpu_private */
 410 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
 411         .master         = &omap54xx_mpu_hwmod,
 412         .slave          = &omap54xx_mpu_private_hwmod,
 413         .clk            = "l3_iclk_div",
 414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 415 };
 416
 417 /* mpu -> emif1 */
 418 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
 419         .master         = &omap54xx_mpu_hwmod,
 420         .slave          = &omap54xx_emif1_hwmod,
 421         .clk            = "dpll_core_h11x2_ck",
 422         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 423 };
 424
 425 /* mpu -> emif2 */
 426 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
 427         .master         = &omap54xx_mpu_hwmod,
 428         .slave          = &omap54xx_emif2_hwmod,
 429         .clk            = "dpll_core_h11x2_ck",
 430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 431 };
 432
 433 /* l4_cfg -> mpu */
 434 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
 435         .master         = &omap54xx_l4_cfg_hwmod,
 436         .slave          = &omap54xx_mpu_hwmod,
 437         .clk            = "l4_root_clk_div",
 438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 439 };
 440
 441 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
 442         &omap54xx_l3_main_1__dmm,
 443         &omap54xx_l3_main_3__l3_instr,
 444         &omap54xx_l3_main_2__l3_main_1,
 445         &omap54xx_l4_cfg__l3_main_1,
 446         &omap54xx_mpu__l3_main_1,
 447         &omap54xx_l3_main_1__l3_main_2,
 448         &omap54xx_l4_cfg__l3_main_2,
 449         &omap54xx_l3_main_1__l3_main_3,
 450         &omap54xx_l3_main_2__l3_main_3,
 451         &omap54xx_l4_cfg__l3_main_3,
 452         &omap54xx_l3_main_1__l4_cfg,
 453         &omap54xx_l3_main_2__l4_per,
 454         &omap54xx_l3_main_1__l4_wkup,
 455         &omap54xx_mpu__mpu_private,
 456         &omap54xx_mpu__emif1,
 457         &omap54xx_mpu__emif2,
 458         &omap54xx_l4_cfg__mpu,
 459         &omap54xx_l4_cfg__sata,
 460         NULL,
 461 };
 462
 463 int __init omap54xx_hwmod_init(void)
 464 {
 465         omap_hwmod_init();
 466         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
 467 }