arch/arm/mach-omap2/prcm_mpu7xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * DRA7xx PRCM MPU instance offset macros
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Generated by code originally written by:
   8  * Paul Walmsley (paul@pwsan.com)
   9  * Rajendra Nayak (rnayak@ti.com)
  10  * Benoit Cousson (b-cousson@ti.com)
  11  *
  12  * This file is automatically generated from the OMAP hardware databases.
  13  * We respectfully ask that any modifications to this file be coordinated
  14  * with the public linux-omap@vger.kernel.org mailing list and the
  15  * authors above to ensure that the autogeneration scripts are kept
  16  * up-to-date with the file contents.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
  21
  22 #include "prcm_mpu_44xx_54xx.h"
  23
  24 #define DRA7XX_PRCM_MPU_BASE                    0x48243000
  25
  26 #define DRA7XX_PRCM_MPU_REGADDR(inst, reg)                              \
  27         OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
  28
  29 /* MPU_PRCM instances */
  30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
  31 #define DRA7XX_MPU_PRCM_DEVICE_INST     0x0200
  32 #define DRA7XX_MPU_PRCM_PRM_C0_INST     0x0400
  33 #define DRA7XX_MPU_PRCM_CM_C0_INST      0x0600
  34 #define DRA7XX_MPU_PRCM_PRM_C1_INST     0x0800
  35 #define DRA7XX_MPU_PRCM_CM_C1_INST      0x0a00
  36
  37 /* PRCM_MPU clockdomain register offsets (from instance start) */
  38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS       0x0000
  39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS       0x0000
  40
  41
  42 /* MPU_PRCM */
  43
  44 /* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
  45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET                         0x0000
  46
  47 /* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
  48 #define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET            0x0010
  49 #define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET   0x0014
  50
  51 /* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
  52 #define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET                         0x0000
  53 #define DRA7XX_PM_CPU0_PWRSTST_OFFSET                           0x0004
  54 #define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET                      0x0010
  55 #define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET                        0x0014
  56 #define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET                      0x0024
  57
  58 /* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
  59 #define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET                         0x0000
  60 #define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET                      0x0020
  61 #define DRA7XX_CM_CPU0_CPU0_CLKCTRL                             DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
  62
  63 /* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
  64 #define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET                         0x0000
  65 #define DRA7XX_PM_CPU1_PWRSTST_OFFSET                           0x0004
  66 #define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET                      0x0010
  67 #define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET                        0x0014
  68 #define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET                      0x0024
  69
  70 /* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
  71 #define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET                         0x0000
  72 #define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET                      0x0020
  73 #define DRA7XX_CM_CPU1_CPU1_CLKCTRL                             DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
  74
  75 #endif