2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
10 #include <linux/init.h>
11 #include <linux/bitops.h>
12 #include <linux/memblock.h>
13 #include <linux/ioport.h>
14 #include <linux/kernel.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_fdt.h>
19 #include <linux/of_platform.h>
20 #include <linux/libfdt.h>
21 #include <linux/smp.h>
22 #include <asm/addrspace.h>
23 #include <asm/bmips.h>
24 #include <asm/bootinfo.h>
25 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
28 #include <asm/smp-ops.h>
30 #include <asm/traps.h>
32 #define RELO_NORMAL_VEC BIT(18)
34 #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
35 #define BCM6328_TP1_DISABLED BIT(9)
37 static const unsigned long kbase
= VMLINUX_LOAD_ADDRESS
& 0xfff00000;
40 const char *compatible
;
41 void (*quirk_fn
)(void);
44 static void kbase_setup(void)
46 __raw_writel(kbase
| RELO_NORMAL_VEC
,
47 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1
);
51 static void bcm3384_viper_quirks(void)
54 * Some experimental CM boxes are set up to let CM own the Viper TP0
55 * and let Linux own TP1. This requires moving the kernel
56 * load address to a non-conflicting region (e.g. via
57 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
58 * If we detect this condition, we need to move the MIPS exception
59 * vectors up to an area that we own.
61 * This is distinct from the OTHER special case mentioned in
62 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
63 * logical CPU#1). For the Viper TP1 case, SMP is off limits.
65 * Also note that many BMIPS435x CPUs do not have a
66 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
67 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
69 board_ebase_setup
= &kbase_setup
;
70 bmips_smp_enabled
= 0;
73 static void bcm63xx_fixup_cpu1(void)
76 * The bootloader has set up the CPU1 reset vector at
78 * This conflicts with the special interrupt vector (IV).
79 * The bootloader has also set up CPU1 to respond to the wrong
81 * Here we will start up CPU1 in the background and ask it to
82 * reconfigure itself then go back to sleep.
84 memcpy((void *)0xa0000200, &bmips_smp_movevec
, 0x20);
87 cpumask_set_cpu(1, &bmips_booted_mask
);
90 static void bcm6328_quirks(void)
92 /* Check CPU1 status in OTP (it is usually disabled) */
93 if (__raw_readl(REG_BCM6328_OTP
) & BCM6328_TP1_DISABLED
)
94 bmips_smp_enabled
= 0;
99 static void bcm6358_quirks(void)
102 * BCM3368/BCM6358 need special handling for their shared TLB, so
103 * disable SMP for now
105 bmips_smp_enabled
= 0;
108 static void bcm6368_quirks(void)
110 bcm63xx_fixup_cpu1();
113 static const struct bmips_quirk bmips_quirk_list
[] = {
114 { "brcm,bcm3368", &bcm6358_quirks
},
115 { "brcm,bcm3384-viper", &bcm3384_viper_quirks
},
116 { "brcm,bcm33843-viper", &bcm3384_viper_quirks
},
117 { "brcm,bcm6328", &bcm6328_quirks
},
118 { "brcm,bcm6358", &bcm6358_quirks
},
119 { "brcm,bcm6362", &bcm6368_quirks
},
120 { "brcm,bcm6368", &bcm6368_quirks
},
121 { "brcm,bcm63168", &bcm6368_quirks
},
122 { "brcm,bcm63268", &bcm6368_quirks
},
126 void __init
prom_init(void)
129 register_bmips_smp_ops();
132 void __init
prom_free_prom_memory(void)
136 const char *get_system_type(void)
138 return "Generic BMIPS kernel";
141 void __init
plat_time_init(void)
143 struct device_node
*np
;
146 np
= of_find_node_by_name(NULL
, "cpus");
148 panic("missing 'cpus' DT node");
149 if (of_property_read_u32(np
, "mips-hpt-frequency", &freq
) < 0)
150 panic("missing 'mips-hpt-frequency' property");
153 mips_hpt_frequency
= freq
;
156 void __init
plat_mem_setup(void)
159 const struct bmips_quirk
*q
;
162 ioport_resource
.start
= 0;
163 ioport_resource
.end
= ~0;
165 /* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */
166 if (fw_arg0
== 0 && fw_arg1
== 0xffffffff)
167 dtb
= phys_to_virt(fw_arg2
);
168 else if (fw_passed_dtb
) /* UHI interface or appended dtb */
169 dtb
= (void *)fw_passed_dtb
;
170 else if (__dtb_start
!= __dtb_end
)
171 dtb
= (void *)__dtb_start
;
173 panic("no dtb found");
175 __dt_setup_arch(dtb
);
177 for (q
= bmips_quirk_list
; q
->quirk_fn
; q
++) {
178 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
185 void __init
device_tree_init(void)
187 struct device_node
*np
;
189 unflatten_and_copy_device_tree();
191 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
192 np
= of_find_node_by_name(NULL
, "cpus");
193 if (np
&& of_get_available_child_count(np
) <= 1)
194 bmips_smp_enabled
= 0;
198 static int __init
plat_dev_init(void)
204 device_initcall(plat_dev_init
);