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Merge tag 'locking-urgent-2020-12-27' of git://git.kernel.org/pub/scm/linux/kernel...
[linux/fpc-iii.git] / drivers / gpio / gpio-omap.c
blob41952bb818ad5266520cefa8a23998708715a669
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Support functions for OMAP GPIO
4 *
5 * Copyright (C) 2003-2005 Nokia Corporation
6 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/syscore_ops.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/pm.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/gpio/driver.h>
26 #include <linux/bitops.h>
27 #include <linux/platform_data/gpio-omap.h>
28
29 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
30
31 struct gpio_regs {
32 u32 irqenable1;
33 u32 irqenable2;
34 u32 wake_en;
35 u32 ctrl;
36 u32 oe;
37 u32 leveldetect0;
38 u32 leveldetect1;
39 u32 risingdetect;
40 u32 fallingdetect;
41 u32 dataout;
42 u32 debounce;
43 u32 debounce_en;
44 };
45
46 struct gpio_bank {
47 void __iomem *base;
48 const struct omap_gpio_reg_offs *regs;
49
50 int irq;
51 u32 non_wakeup_gpios;
52 u32 enabled_non_wakeup_gpios;
53 struct gpio_regs context;
54 u32 saved_datain;
55 u32 level_mask;
56 u32 toggle_mask;
57 raw_spinlock_t lock;
58 raw_spinlock_t wa_lock;
59 struct gpio_chip chip;
60 struct clk *dbck;
61 struct notifier_block nb;
62 unsigned int is_suspended:1;
63 unsigned int needs_resume:1;
64 u32 mod_usage;
65 u32 irq_usage;
66 u32 dbck_enable_mask;
67 bool dbck_enabled;
68 bool is_mpuio;
69 bool dbck_flag;
70 bool loses_context;
71 bool context_valid;
72 int stride;
73 u32 width;
74 int context_loss_count;
75
76 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
77 int (*get_context_loss_count)(struct device *dev);
78 };
79
80 #define GPIO_MOD_CTRL_BIT BIT(0)
81
82 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
83 #define LINE_USED(line, offset) (line & (BIT(offset)))
84
85 static void omap_gpio_unmask_irq(struct irq_data *d);
86
87 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
88 {
89 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
90 return gpiochip_get_data(chip);
91 }
92
93 static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
94 {
95 u32 val = readl_relaxed(reg);
96
97 if (set)
98 val |= mask;
99 else
100 val &= ~mask;
101
102 writel_relaxed(val, reg);
103
104 return val;
105 }
106
107 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
108 int is_input)
109 {
110 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
111 BIT(gpio), is_input);
112 }
113
114
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 int enable)
118 {
119 void __iomem *reg = bank->base;
120 u32 l = BIT(offset);
121
122 if (enable) {
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
125 } else {
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
128 }
129
130 writel_relaxed(l, reg);
131 }
132
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 int enable)
136 {
137 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
138 BIT(offset), enable);
139 }
140
141 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
142 {
143 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
144 clk_enable(bank->dbck);
145 bank->dbck_enabled = true;
146
147 writel_relaxed(bank->dbck_enable_mask,
148 bank->base + bank->regs->debounce_en);
149 }
150 }
151
152 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
153 {
154 if (bank->dbck_enable_mask && bank->dbck_enabled) {
155 /*
156 * Disable debounce before cutting it's clock. If debounce is
157 * enabled but the clock is not, GPIO module seems to be unable
158 * to detect events and generate interrupts at least on OMAP3.
159 */
160 writel_relaxed(0, bank->base + bank->regs->debounce_en);
161
162 clk_disable(bank->dbck);
163 bank->dbck_enabled = false;
164 }
165 }
166
167 /**
168 * omap2_set_gpio_debounce - low level gpio debounce time
169 * @bank: the gpio bank we're acting upon
170 * @offset: the gpio number on this @bank
171 * @debounce: debounce time to use
172 *
173 * OMAP's debounce time is in 31us steps
174 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
175 * so we need to convert and round up to the closest unit.
176 *
177 * Return: 0 on success, negative error otherwise.
178 */
179 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
180 unsigned debounce)
181 {
182 u32 val;
183 u32 l;
184 bool enable = !!debounce;
185
186 if (!bank->dbck_flag)
187 return -ENOTSUPP;
188
189 if (enable) {
190 debounce = DIV_ROUND_UP(debounce, 31) - 1;
191 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
192 return -EINVAL;
193 }
194
195 l = BIT(offset);
196
197 clk_enable(bank->dbck);
198 writel_relaxed(debounce, bank->base + bank->regs->debounce);
199
200 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
201 bank->dbck_enable_mask = val;
202
203 clk_disable(bank->dbck);
204 /*
205 * Enable debounce clock per module.
206 * This call is mandatory because in omap_gpio_request() when
207 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
208 * runtime callbck fails to turn on dbck because dbck_enable_mask
209 * used within _gpio_dbck_enable() is still not initialized at
210 * that point. Therefore we have to enable dbck here.
211 */
212 omap_gpio_dbck_enable(bank);
213 if (bank->dbck_enable_mask) {
214 bank->context.debounce = debounce;
215 bank->context.debounce_en = val;
216 }
217
218 return 0;
219 }
220
221 /**
222 * omap_clear_gpio_debounce - clear debounce settings for a gpio
223 * @bank: the gpio bank we're acting upon
224 * @offset: the gpio number on this @bank
225 *
226 * If a gpio is using debounce, then clear the debounce enable bit and if
227 * this is the only gpio in this bank using debounce, then clear the debounce
228 * time too. The debounce clock will also be disabled when calling this function
229 * if this is the only gpio in the bank using debounce.
230 */
231 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
232 {
233 u32 gpio_bit = BIT(offset);
234
235 if (!bank->dbck_flag)
236 return;
237
238 if (!(bank->dbck_enable_mask & gpio_bit))
239 return;
240
241 bank->dbck_enable_mask &= ~gpio_bit;
242 bank->context.debounce_en &= ~gpio_bit;
243 writel_relaxed(bank->context.debounce_en,
244 bank->base + bank->regs->debounce_en);
245
246 if (!bank->dbck_enable_mask) {
247 bank->context.debounce = 0;
248 writel_relaxed(bank->context.debounce, bank->base +
249 bank->regs->debounce);
250 clk_disable(bank->dbck);
251 bank->dbck_enabled = false;
252 }
253 }
254
255 /*
256 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
257 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
258 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
259 * are capable waking up the system from off mode.
260 */
261 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
262 {
263 u32 no_wake = bank->non_wakeup_gpios;
264
265 if (no_wake)
266 return !!(~no_wake & gpio_mask);
267
268 return false;
269 }
270
271 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
272 unsigned trigger)
273 {
274 void __iomem *base = bank->base;
275 u32 gpio_bit = BIT(gpio);
276
277 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
278 trigger & IRQ_TYPE_LEVEL_LOW);
279 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
280 trigger & IRQ_TYPE_LEVEL_HIGH);
281
282 /*
283 * We need the edge detection enabled for to allow the GPIO block
284 * to be woken from idle state. Set the appropriate edge detection
285 * in addition to the level detection.
286 */
287 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
288 trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
289 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
290 trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
291
292 bank->context.leveldetect0 =
293 readl_relaxed(bank->base + bank->regs->leveldetect0);
294 bank->context.leveldetect1 =
295 readl_relaxed(bank->base + bank->regs->leveldetect1);
296 bank->context.risingdetect =
297 readl_relaxed(bank->base + bank->regs->risingdetect);
298 bank->context.fallingdetect =
299 readl_relaxed(bank->base + bank->regs->fallingdetect);
300
301 bank->level_mask = bank->context.leveldetect0 |
302 bank->context.leveldetect1;
303
304 /* This part needs to be executed always for OMAP{34xx, 44xx} */
305 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
306 /*
307 * Log the edge gpio and manually trigger the IRQ
308 * after resume if the input level changes
309 * to avoid irq lost during PER RET/OFF mode
310 * Applies for omap2 non-wakeup gpio and all omap3 gpios
311 */
312 if (trigger & IRQ_TYPE_EDGE_BOTH)
313 bank->enabled_non_wakeup_gpios |= gpio_bit;
314 else
315 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
316 }
317 }
318
319 /*
320 * This only applies to chips that can't do both rising and falling edge
321 * detection at once. For all other chips, this function is a noop.
322 */
323 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
324 {
325 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
326 void __iomem *reg = bank->base + bank->regs->irqctrl;
327
328 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
329 }
330 }
331
332 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
333 unsigned trigger)
334 {
335 void __iomem *reg = bank->base;
336 u32 l = 0;
337
338 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
339 omap_set_gpio_trigger(bank, gpio, trigger);
340 } else if (bank->regs->irqctrl) {
341 reg += bank->regs->irqctrl;
342
343 l = readl_relaxed(reg);
344 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
345 bank->toggle_mask |= BIT(gpio);
346 if (trigger & IRQ_TYPE_EDGE_RISING)
347 l |= BIT(gpio);
348 else if (trigger & IRQ_TYPE_EDGE_FALLING)
349 l &= ~(BIT(gpio));
350 else
351 return -EINVAL;
352
353 writel_relaxed(l, reg);
354 } else if (bank->regs->edgectrl1) {
355 if (gpio & 0x08)
356 reg += bank->regs->edgectrl2;
357 else
358 reg += bank->regs->edgectrl1;
359
360 gpio &= 0x07;
361 l = readl_relaxed(reg);
362 l &= ~(3 << (gpio << 1));
363 if (trigger & IRQ_TYPE_EDGE_RISING)
364 l |= 2 << (gpio << 1);
365 if (trigger & IRQ_TYPE_EDGE_FALLING)
366 l |= BIT(gpio << 1);
367 writel_relaxed(l, reg);
368 }
369 return 0;
370 }
371
372 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
373 {
374 if (bank->regs->pinctrl) {
375 void __iomem *reg = bank->base + bank->regs->pinctrl;
376
377 /* Claim the pin for MPU */
378 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
379 }
380
381 if (bank->regs->ctrl && !BANK_USED(bank)) {
382 void __iomem *reg = bank->base + bank->regs->ctrl;
383 u32 ctrl;
384
385 ctrl = readl_relaxed(reg);
386 /* Module is enabled, clocks are not gated */
387 ctrl &= ~GPIO_MOD_CTRL_BIT;
388 writel_relaxed(ctrl, reg);
389 bank->context.ctrl = ctrl;
390 }
391 }
392
393 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
394 {
395 if (bank->regs->ctrl && !BANK_USED(bank)) {
396 void __iomem *reg = bank->base + bank->regs->ctrl;
397 u32 ctrl;
398
399 ctrl = readl_relaxed(reg);
400 /* Module is disabled, clocks are gated */
401 ctrl |= GPIO_MOD_CTRL_BIT;
402 writel_relaxed(ctrl, reg);
403 bank->context.ctrl = ctrl;
404 }
405 }
406
407 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
408 {
409 void __iomem *reg = bank->base + bank->regs->direction;
410
411 return readl_relaxed(reg) & BIT(offset);
412 }
413
414 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
415 {
416 if (!LINE_USED(bank->mod_usage, offset)) {
417 omap_enable_gpio_module(bank, offset);
418 omap_set_gpio_direction(bank, offset, 1);
419 }
420 bank->irq_usage |= BIT(offset);
421 }
422
423 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
424 {
425 struct gpio_bank *bank = omap_irq_data_get_bank(d);
426 int retval;
427 unsigned long flags;
428 unsigned offset = d->hwirq;
429
430 if (type & ~IRQ_TYPE_SENSE_MASK)
431 return -EINVAL;
432
433 if (!bank->regs->leveldetect0 &&
434 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
435 return -EINVAL;
436
437 raw_spin_lock_irqsave(&bank->lock, flags);
438 retval = omap_set_gpio_triggering(bank, offset, type);
439 if (retval) {
440 raw_spin_unlock_irqrestore(&bank->lock, flags);
441 goto error;
442 }
443 omap_gpio_init_irq(bank, offset);
444 if (!omap_gpio_is_input(bank, offset)) {
445 raw_spin_unlock_irqrestore(&bank->lock, flags);
446 retval = -EINVAL;
447 goto error;
448 }
449 raw_spin_unlock_irqrestore(&bank->lock, flags);
450
451 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
452 irq_set_handler_locked(d, handle_level_irq);
453 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
454 /*
455 * Edge IRQs are already cleared/acked in irq_handler and
456 * not need to be masked, as result handle_edge_irq()
457 * logic is excessed here and may cause lose of interrupts.
458 * So just use handle_simple_irq.
459 */
460 irq_set_handler_locked(d, handle_simple_irq);
461
462 return 0;
463
464 error:
465 return retval;
466 }
467
468 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
469 {
470 void __iomem *reg = bank->base;
471
472 reg += bank->regs->irqstatus;
473 writel_relaxed(gpio_mask, reg);
474
475 /* Workaround for clearing DSP GPIO interrupts to allow retention */
476 if (bank->regs->irqstatus2) {
477 reg = bank->base + bank->regs->irqstatus2;
478 writel_relaxed(gpio_mask, reg);
479 }
480
481 /* Flush posted write for the irq status to avoid spurious interrupts */
482 readl_relaxed(reg);
483 }
484
485 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
486 unsigned offset)
487 {
488 omap_clear_gpio_irqbank(bank, BIT(offset));
489 }
490
491 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
492 {
493 void __iomem *reg = bank->base;
494 u32 l;
495 u32 mask = (BIT(bank->width)) - 1;
496
497 reg += bank->regs->irqenable;
498 l = readl_relaxed(reg);
499 if (bank->regs->irqenable_inv)
500 l = ~l;
501 l &= mask;
502 return l;
503 }
504
505 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
506 unsigned offset, int enable)
507 {
508 void __iomem *reg = bank->base;
509 u32 gpio_mask = BIT(offset);
510
511 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
512 if (enable) {
513 reg += bank->regs->set_irqenable;
514 bank->context.irqenable1 |= gpio_mask;
515 } else {
516 reg += bank->regs->clr_irqenable;
517 bank->context.irqenable1 &= ~gpio_mask;
518 }
519 writel_relaxed(gpio_mask, reg);
520 } else {
521 bank->context.irqenable1 =
522 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
523 enable ^ bank->regs->irqenable_inv);
524 }
525
526 /*
527 * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
528 * note requiring correlation between the IRQ enable registers and
529 * the wakeup registers. In any case, we want wakeup from idle
530 * enabled for the GPIOs which support this feature.
531 */
532 if (bank->regs->wkup_en &&
533 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
534 bank->context.wake_en =
535 omap_gpio_rmw(bank->base + bank->regs->wkup_en,
536 gpio_mask, enable);
537 }
538 }
539
540 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
541 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
542 {
543 struct gpio_bank *bank = omap_irq_data_get_bank(d);
544
545 return irq_set_irq_wake(bank->irq, enable);
546 }
547
548 /*
549 * We need to unmask the GPIO bank interrupt as soon as possible to
550 * avoid missing GPIO interrupts for other lines in the bank.
551 * Then we need to mask-read-clear-unmask the triggered GPIO lines
552 * in the bank to avoid missing nested interrupts for a GPIO line.
553 * If we wait to unmask individual GPIO lines in the bank after the
554 * line's interrupt handler has been run, we may miss some nested
555 * interrupts.
556 */
557 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
558 {
559 void __iomem *isr_reg = NULL;
560 u32 enabled, isr, edge;
561 unsigned int bit;
562 struct gpio_bank *bank = gpiobank;
563 unsigned long wa_lock_flags;
564 unsigned long lock_flags;
565
566 isr_reg = bank->base + bank->regs->irqstatus;
567 if (WARN_ON(!isr_reg))
568 goto exit;
569
570 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
571 "gpio irq%i while runtime suspended?\n", irq))
572 return IRQ_NONE;
573
574 while (1) {
575 raw_spin_lock_irqsave(&bank->lock, lock_flags);
576
577 enabled = omap_get_gpio_irqbank_mask(bank);
578 isr = readl_relaxed(isr_reg) & enabled;
579
580 /*
581 * Clear edge sensitive interrupts before calling handler(s)
582 * so subsequent edge transitions are not missed while the
583 * handlers are running.
584 */
585 edge = isr & ~bank->level_mask;
586 if (edge)
587 omap_clear_gpio_irqbank(bank, edge);
588
589 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
590
591 if (!isr)
592 break;
593
594 while (isr) {
595 bit = __ffs(isr);
596 isr &= ~(BIT(bit));
597
598 raw_spin_lock_irqsave(&bank->lock, lock_flags);
599 /*
600 * Some chips can't respond to both rising and falling
601 * at the same time. If this irq was requested with
602 * both flags, we need to flip the ICR data for the IRQ
603 * to respond to the IRQ for the opposite direction.
604 * This will be indicated in the bank toggle_mask.
605 */
606 if (bank->toggle_mask & (BIT(bit)))
607 omap_toggle_gpio_edge_triggering(bank, bit);
608
609 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
610
611 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
612
613 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
614 bit));
615
616 raw_spin_unlock_irqrestore(&bank->wa_lock,
617 wa_lock_flags);
618 }
619 }
620 exit:
621 return IRQ_HANDLED;
622 }
623
624 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
625 {
626 struct gpio_bank *bank = omap_irq_data_get_bank(d);
627 unsigned long flags;
628 unsigned offset = d->hwirq;
629
630 raw_spin_lock_irqsave(&bank->lock, flags);
631
632 if (!LINE_USED(bank->mod_usage, offset))
633 omap_set_gpio_direction(bank, offset, 1);
634 omap_enable_gpio_module(bank, offset);
635 bank->irq_usage |= BIT(offset);
636
637 raw_spin_unlock_irqrestore(&bank->lock, flags);
638 omap_gpio_unmask_irq(d);
639
640 return 0;
641 }
642
643 static void omap_gpio_irq_shutdown(struct irq_data *d)
644 {
645 struct gpio_bank *bank = omap_irq_data_get_bank(d);
646 unsigned long flags;
647 unsigned offset = d->hwirq;
648
649 raw_spin_lock_irqsave(&bank->lock, flags);
650 bank->irq_usage &= ~(BIT(offset));
651 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
652 omap_clear_gpio_irqstatus(bank, offset);
653 omap_set_gpio_irqenable(bank, offset, 0);
654 if (!LINE_USED(bank->mod_usage, offset))
655 omap_clear_gpio_debounce(bank, offset);
656 omap_disable_gpio_module(bank, offset);
657 raw_spin_unlock_irqrestore(&bank->lock, flags);
658 }
659
660 static void omap_gpio_irq_bus_lock(struct irq_data *data)
661 {
662 struct gpio_bank *bank = omap_irq_data_get_bank(data);
663
664 pm_runtime_get_sync(bank->chip.parent);
665 }
666
667 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
668 {
669 struct gpio_bank *bank = omap_irq_data_get_bank(data);
670
671 pm_runtime_put(bank->chip.parent);
672 }
673
674 static void omap_gpio_mask_irq(struct irq_data *d)
675 {
676 struct gpio_bank *bank = omap_irq_data_get_bank(d);
677 unsigned offset = d->hwirq;
678 unsigned long flags;
679
680 raw_spin_lock_irqsave(&bank->lock, flags);
681 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
682 omap_set_gpio_irqenable(bank, offset, 0);
683 raw_spin_unlock_irqrestore(&bank->lock, flags);
684 }
685
686 static void omap_gpio_unmask_irq(struct irq_data *d)
687 {
688 struct gpio_bank *bank = omap_irq_data_get_bank(d);
689 unsigned offset = d->hwirq;
690 u32 trigger = irqd_get_trigger_type(d);
691 unsigned long flags;
692
693 raw_spin_lock_irqsave(&bank->lock, flags);
694 omap_set_gpio_irqenable(bank, offset, 1);
695
696 /*
697 * For level-triggered GPIOs, clearing must be done after the source
698 * is cleared, thus after the handler has run. OMAP4 needs this done
699 * after enabing the interrupt to clear the wakeup status.
700 */
701 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
702 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
703 omap_clear_gpio_irqstatus(bank, offset);
704
705 if (trigger)
706 omap_set_gpio_triggering(bank, offset, trigger);
707
708 raw_spin_unlock_irqrestore(&bank->lock, flags);
709 }
710
711 /*---------------------------------------------------------------------*/
712
713 static int omap_mpuio_suspend_noirq(struct device *dev)
714 {
715 struct gpio_bank *bank = dev_get_drvdata(dev);
716 void __iomem *mask_reg = bank->base +
717 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
718 unsigned long flags;
719
720 raw_spin_lock_irqsave(&bank->lock, flags);
721 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
722 raw_spin_unlock_irqrestore(&bank->lock, flags);
723
724 return 0;
725 }
726
727 static int omap_mpuio_resume_noirq(struct device *dev)
728 {
729 struct gpio_bank *bank = dev_get_drvdata(dev);
730 void __iomem *mask_reg = bank->base +
731 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
732 unsigned long flags;
733
734 raw_spin_lock_irqsave(&bank->lock, flags);
735 writel_relaxed(bank->context.wake_en, mask_reg);
736 raw_spin_unlock_irqrestore(&bank->lock, flags);
737
738 return 0;
739 }
740
741 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
742 .suspend_noirq = omap_mpuio_suspend_noirq,
743 .resume_noirq = omap_mpuio_resume_noirq,
744 };
745
746 /* use platform_driver for this. */
747 static struct platform_driver omap_mpuio_driver = {
748 .driver = {
749 .name = "mpuio",
750 .pm = &omap_mpuio_dev_pm_ops,
751 },
752 };
753
754 static struct platform_device omap_mpuio_device = {
755 .name = "mpuio",
756 .id = -1,
757 .dev = {
758 .driver = &omap_mpuio_driver.driver,
759 }
760 /* could list the /proc/iomem resources */
761 };
762
763 static inline void omap_mpuio_init(struct gpio_bank *bank)
764 {
765 platform_set_drvdata(&omap_mpuio_device, bank);
766
767 if (platform_driver_register(&omap_mpuio_driver) == 0)
768 (void) platform_device_register(&omap_mpuio_device);
769 }
770
771 /*---------------------------------------------------------------------*/
772
773 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
774 {
775 struct gpio_bank *bank = gpiochip_get_data(chip);
776 unsigned long flags;
777
778 pm_runtime_get_sync(chip->parent);
779
780 raw_spin_lock_irqsave(&bank->lock, flags);
781 omap_enable_gpio_module(bank, offset);
782 bank->mod_usage |= BIT(offset);
783 raw_spin_unlock_irqrestore(&bank->lock, flags);
784
785 return 0;
786 }
787
788 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
789 {
790 struct gpio_bank *bank = gpiochip_get_data(chip);
791 unsigned long flags;
792
793 raw_spin_lock_irqsave(&bank->lock, flags);
794 bank->mod_usage &= ~(BIT(offset));
795 if (!LINE_USED(bank->irq_usage, offset)) {
796 omap_set_gpio_direction(bank, offset, 1);
797 omap_clear_gpio_debounce(bank, offset);
798 }
799 omap_disable_gpio_module(bank, offset);
800 raw_spin_unlock_irqrestore(&bank->lock, flags);
801
802 pm_runtime_put(chip->parent);
803 }
804
805 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
806 {
807 struct gpio_bank *bank = gpiochip_get_data(chip);
808
809 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
810 return GPIO_LINE_DIRECTION_IN;
811
812 return GPIO_LINE_DIRECTION_OUT;
813 }
814
815 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
816 {
817 struct gpio_bank *bank;
818 unsigned long flags;
819
820 bank = gpiochip_get_data(chip);
821 raw_spin_lock_irqsave(&bank->lock, flags);
822 omap_set_gpio_direction(bank, offset, 1);
823 raw_spin_unlock_irqrestore(&bank->lock, flags);
824 return 0;
825 }
826
827 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
828 {
829 struct gpio_bank *bank = gpiochip_get_data(chip);
830 void __iomem *reg;
831
832 if (omap_gpio_is_input(bank, offset))
833 reg = bank->base + bank->regs->datain;
834 else
835 reg = bank->base + bank->regs->dataout;
836
837 return (readl_relaxed(reg) & BIT(offset)) != 0;
838 }
839
840 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
841 {
842 struct gpio_bank *bank;
843 unsigned long flags;
844
845 bank = gpiochip_get_data(chip);
846 raw_spin_lock_irqsave(&bank->lock, flags);
847 bank->set_dataout(bank, offset, value);
848 omap_set_gpio_direction(bank, offset, 0);
849 raw_spin_unlock_irqrestore(&bank->lock, flags);
850 return 0;
851 }
852
853 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
854 unsigned long *bits)
855 {
856 struct gpio_bank *bank = gpiochip_get_data(chip);
857 void __iomem *base = bank->base;
858 u32 direction, m, val = 0;
859
860 direction = readl_relaxed(base + bank->regs->direction);
861
862 m = direction & *mask;
863 if (m)
864 val |= readl_relaxed(base + bank->regs->datain) & m;
865
866 m = ~direction & *mask;
867 if (m)
868 val |= readl_relaxed(base + bank->regs->dataout) & m;
869
870 *bits = val;
871
872 return 0;
873 }
874
875 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
876 unsigned debounce)
877 {
878 struct gpio_bank *bank;
879 unsigned long flags;
880 int ret;
881
882 bank = gpiochip_get_data(chip);
883
884 raw_spin_lock_irqsave(&bank->lock, flags);
885 ret = omap2_set_gpio_debounce(bank, offset, debounce);
886 raw_spin_unlock_irqrestore(&bank->lock, flags);
887
888 if (ret)
889 dev_info(chip->parent,
890 "Could not set line %u debounce to %u microseconds (%d)",
891 offset, debounce, ret);
892
893 return ret;
894 }
895
896 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
897 unsigned long config)
898 {
899 u32 debounce;
900 int ret = -ENOTSUPP;
901
902 switch (pinconf_to_config_param(config)) {
903 case PIN_CONFIG_BIAS_DISABLE:
904 case PIN_CONFIG_BIAS_PULL_UP:
905 case PIN_CONFIG_BIAS_PULL_DOWN:
906 ret = gpiochip_generic_config(chip, offset, config);
907 break;
908 case PIN_CONFIG_INPUT_DEBOUNCE:
909 debounce = pinconf_to_config_argument(config);
910 ret = omap_gpio_debounce(chip, offset, debounce);
911 break;
912 default:
913 break;
914 }
915
916 return ret;
917 }
918
919 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
920 {
921 struct gpio_bank *bank;
922 unsigned long flags;
923
924 bank = gpiochip_get_data(chip);
925 raw_spin_lock_irqsave(&bank->lock, flags);
926 bank->set_dataout(bank, offset, value);
927 raw_spin_unlock_irqrestore(&bank->lock, flags);
928 }
929
930 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
931 unsigned long *bits)
932 {
933 struct gpio_bank *bank = gpiochip_get_data(chip);
934 void __iomem *reg = bank->base + bank->regs->dataout;
935 unsigned long flags;
936 u32 l;
937
938 raw_spin_lock_irqsave(&bank->lock, flags);
939 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
940 writel_relaxed(l, reg);
941 bank->context.dataout = l;
942 raw_spin_unlock_irqrestore(&bank->lock, flags);
943 }
944
945 /*---------------------------------------------------------------------*/
946
947 static void omap_gpio_show_rev(struct gpio_bank *bank)
948 {
949 static bool called;
950 u32 rev;
951
952 if (called || bank->regs->revision == USHRT_MAX)
953 return;
954
955 rev = readw_relaxed(bank->base + bank->regs->revision);
956 pr_info("OMAP GPIO hardware version %d.%d\n",
957 (rev >> 4) & 0x0f, rev & 0x0f);
958
959 called = true;
960 }
961
962 static void omap_gpio_mod_init(struct gpio_bank *bank)
963 {
964 void __iomem *base = bank->base;
965 u32 l = 0xffffffff;
966
967 if (bank->width == 16)
968 l = 0xffff;
969
970 if (bank->is_mpuio) {
971 writel_relaxed(l, bank->base + bank->regs->irqenable);
972 return;
973 }
974
975 omap_gpio_rmw(base + bank->regs->irqenable, l,
976 bank->regs->irqenable_inv);
977 omap_gpio_rmw(base + bank->regs->irqstatus, l,
978 !bank->regs->irqenable_inv);
979 if (bank->regs->debounce_en)
980 writel_relaxed(0, base + bank->regs->debounce_en);
981
982 /* Save OE default value (0xffffffff) in the context */
983 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
984 /* Initialize interface clk ungated, module enabled */
985 if (bank->regs->ctrl)
986 writel_relaxed(0, base + bank->regs->ctrl);
987 }
988
989 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
990 {
991 struct gpio_irq_chip *irq;
992 static int gpio;
993 const char *label;
994 int irq_base = 0;
995 int ret;
996
997 /*
998 * REVISIT eventually switch from OMAP-specific gpio structs
999 * over to the generic ones
1000 */
1001 bank->chip.request = omap_gpio_request;
1002 bank->chip.free = omap_gpio_free;
1003 bank->chip.get_direction = omap_gpio_get_direction;
1004 bank->chip.direction_input = omap_gpio_input;
1005 bank->chip.get = omap_gpio_get;
1006 bank->chip.get_multiple = omap_gpio_get_multiple;
1007 bank->chip.direction_output = omap_gpio_output;
1008 bank->chip.set_config = omap_gpio_set_config;
1009 bank->chip.set = omap_gpio_set;
1010 bank->chip.set_multiple = omap_gpio_set_multiple;
1011 if (bank->is_mpuio) {
1012 bank->chip.label = "mpuio";
1013 if (bank->regs->wkup_en)
1014 bank->chip.parent = &omap_mpuio_device.dev;
1015 bank->chip.base = OMAP_MPUIO(0);
1016 } else {
1017 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1018 gpio, gpio + bank->width - 1);
1019 if (!label)
1020 return -ENOMEM;
1021 bank->chip.label = label;
1022 bank->chip.base = gpio;
1023 }
1024 bank->chip.ngpio = bank->width;
1025
1026 #ifdef CONFIG_ARCH_OMAP1
1027 /*
1028 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1029 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1030 */
1031 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1032 -1, 0, bank->width, 0);
1033 if (irq_base < 0) {
1034 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1035 return -ENODEV;
1036 }
1037 #endif
1038
1039 /* MPUIO is a bit different, reading IRQ status clears it */
1040 if (bank->is_mpuio && !bank->regs->wkup_en)
1041 irqc->irq_set_wake = NULL;
1042
1043 irq = &bank->chip.irq;
1044 irq->chip = irqc;
1045 irq->handler = handle_bad_irq;
1046 irq->default_type = IRQ_TYPE_NONE;
1047 irq->num_parents = 1;
1048 irq->parents = &bank->irq;
1049 irq->first = irq_base;
1050
1051 ret = gpiochip_add_data(&bank->chip, bank);
1052 if (ret)
1053 return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");
1054
1055 ret = devm_request_irq(bank->chip.parent, bank->irq,
1056 omap_gpio_irq_handler,
1057 0, dev_name(bank->chip.parent), bank);
1058 if (ret)
1059 gpiochip_remove(&bank->chip);
1060
1061 if (!bank->is_mpuio)
1062 gpio += bank->width;
1063
1064 return ret;
1065 }
1066
1067 static void omap_gpio_init_context(struct gpio_bank *p)
1068 {
1069 const struct omap_gpio_reg_offs *regs = p->regs;
1070 void __iomem *base = p->base;
1071
1072 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1073 p->context.oe = readl_relaxed(base + regs->direction);
1074 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1075 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1076 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1077 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1078 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1079 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1080 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1081 p->context.dataout = readl_relaxed(base + regs->dataout);
1082
1083 p->context_valid = true;
1084 }
1085
1086 static void omap_gpio_restore_context(struct gpio_bank *bank)
1087 {
1088 const struct omap_gpio_reg_offs *regs = bank->regs;
1089 void __iomem *base = bank->base;
1090
1091 writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1092 writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1093 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1094 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1095 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1096 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1097 writel_relaxed(bank->context.dataout, base + regs->dataout);
1098 writel_relaxed(bank->context.oe, base + regs->direction);
1099
1100 if (bank->dbck_enable_mask) {
1101 writel_relaxed(bank->context.debounce, base + regs->debounce);
1102 writel_relaxed(bank->context.debounce_en,
1103 base + regs->debounce_en);
1104 }
1105
1106 writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1107 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1108 }
1109
1110 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1111 {
1112 struct device *dev = bank->chip.parent;
1113 void __iomem *base = bank->base;
1114 u32 mask, nowake;
1115
1116 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1117
1118 if (!bank->enabled_non_wakeup_gpios)
1119 goto update_gpio_context_count;
1120
1121 /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
1122 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
1123 mask &= ~bank->context.risingdetect;
1124 bank->saved_datain |= mask;
1125
1126 /* Check for pending EDGE_RISING, ignore EDGE_BOTH */
1127 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
1128 mask &= ~bank->context.fallingdetect;
1129 bank->saved_datain &= ~mask;
1130
1131 if (!may_lose_context)
1132 goto update_gpio_context_count;
1133
1134 /*
1135 * If going to OFF, remove triggering for all wkup domain
1136 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1137 * generated. See OMAP2420 Errata item 1.101.
1138 */
1139 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1140 nowake = bank->enabled_non_wakeup_gpios;
1141 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1142 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1143 }
1144
1145 update_gpio_context_count:
1146 if (bank->get_context_loss_count)
1147 bank->context_loss_count =
1148 bank->get_context_loss_count(dev);
1149
1150 omap_gpio_dbck_disable(bank);
1151 }
1152
1153 static void omap_gpio_unidle(struct gpio_bank *bank)
1154 {
1155 struct device *dev = bank->chip.parent;
1156 u32 l = 0, gen, gen0, gen1;
1157 int c;
1158
1159 /*
1160 * On the first resume during the probe, the context has not
1161 * been initialised and so initialise it now. Also initialise
1162 * the context loss count.
1163 */
1164 if (bank->loses_context && !bank->context_valid) {
1165 omap_gpio_init_context(bank);
1166
1167 if (bank->get_context_loss_count)
1168 bank->context_loss_count =
1169 bank->get_context_loss_count(dev);
1170 }
1171
1172 omap_gpio_dbck_enable(bank);
1173
1174 if (bank->loses_context) {
1175 if (!bank->get_context_loss_count) {
1176 omap_gpio_restore_context(bank);
1177 } else {
1178 c = bank->get_context_loss_count(dev);
1179 if (c != bank->context_loss_count) {
1180 omap_gpio_restore_context(bank);
1181 } else {
1182 return;
1183 }
1184 }
1185 } else {
1186 /* Restore changes done for OMAP2420 errata 1.101 */
1187 writel_relaxed(bank->context.fallingdetect,
1188 bank->base + bank->regs->fallingdetect);
1189 writel_relaxed(bank->context.risingdetect,
1190 bank->base + bank->regs->risingdetect);
1191 }
1192
1193 l = readl_relaxed(bank->base + bank->regs->datain);
1194
1195 /*
1196 * Check if any of the non-wakeup interrupt GPIOs have changed
1197 * state. If so, generate an IRQ by software. This is
1198 * horribly racy, but it's the best we can do to work around
1199 * this silicon bug.
1200 */
1201 l ^= bank->saved_datain;
1202 l &= bank->enabled_non_wakeup_gpios;
1203
1204 /*
1205 * No need to generate IRQs for the rising edge for gpio IRQs
1206 * configured with falling edge only; and vice versa.
1207 */
1208 gen0 = l & bank->context.fallingdetect;
1209 gen0 &= bank->saved_datain;
1210
1211 gen1 = l & bank->context.risingdetect;
1212 gen1 &= ~(bank->saved_datain);
1213
1214 /* FIXME: Consider GPIO IRQs with level detections properly! */
1215 gen = l & (~(bank->context.fallingdetect) &
1216 ~(bank->context.risingdetect));
1217 /* Consider all GPIO IRQs needed to be updated */
1218 gen |= gen0 | gen1;
1219
1220 if (gen) {
1221 u32 old0, old1;
1222
1223 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1224 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1225
1226 if (!bank->regs->irqstatus_raw0) {
1227 writel_relaxed(old0 | gen, bank->base +
1228 bank->regs->leveldetect0);
1229 writel_relaxed(old1 | gen, bank->base +
1230 bank->regs->leveldetect1);
1231 }
1232
1233 if (bank->regs->irqstatus_raw0) {
1234 writel_relaxed(old0 | l, bank->base +
1235 bank->regs->leveldetect0);
1236 writel_relaxed(old1 | l, bank->base +
1237 bank->regs->leveldetect1);
1238 }
1239 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1240 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1241 }
1242 }
1243
1244 static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1245 unsigned long cmd, void *v)
1246 {
1247 struct gpio_bank *bank;
1248 unsigned long flags;
1249 int ret = NOTIFY_OK;
1250 u32 isr, mask;
1251
1252 bank = container_of(nb, struct gpio_bank, nb);
1253
1254 raw_spin_lock_irqsave(&bank->lock, flags);
1255 if (bank->is_suspended)
1256 goto out_unlock;
1257
1258 switch (cmd) {
1259 case CPU_CLUSTER_PM_ENTER:
1260 mask = omap_get_gpio_irqbank_mask(bank);
1261 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
1262 if (isr) {
1263 ret = NOTIFY_BAD;
1264 break;
1265 }
1266 omap_gpio_idle(bank, true);
1267 break;
1268 case CPU_CLUSTER_PM_ENTER_FAILED:
1269 case CPU_CLUSTER_PM_EXIT:
1270 omap_gpio_unidle(bank);
1271 break;
1272 }
1273
1274 out_unlock:
1275 raw_spin_unlock_irqrestore(&bank->lock, flags);
1276
1277 return ret;
1278 }
1279
1280 static const struct omap_gpio_reg_offs omap2_gpio_regs = {
1281 .revision = OMAP24XX_GPIO_REVISION,
1282 .direction = OMAP24XX_GPIO_OE,
1283 .datain = OMAP24XX_GPIO_DATAIN,
1284 .dataout = OMAP24XX_GPIO_DATAOUT,
1285 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1286 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1287 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1288 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1289 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1290 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1291 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1292 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1293 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1294 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1295 .ctrl = OMAP24XX_GPIO_CTRL,
1296 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1297 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1298 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1299 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1300 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1301 };
1302
1303 static const struct omap_gpio_reg_offs omap4_gpio_regs = {
1304 .revision = OMAP4_GPIO_REVISION,
1305 .direction = OMAP4_GPIO_OE,
1306 .datain = OMAP4_GPIO_DATAIN,
1307 .dataout = OMAP4_GPIO_DATAOUT,
1308 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1309 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1310 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1311 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1312 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
1313 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
1314 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1315 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1316 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1317 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1318 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1319 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1320 .ctrl = OMAP4_GPIO_CTRL,
1321 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1322 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1323 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1324 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1325 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1326 };
1327
1328 static const struct omap_gpio_platform_data omap2_pdata = {
1329 .regs = &omap2_gpio_regs,
1330 .bank_width = 32,
1331 .dbck_flag = false,
1332 };
1333
1334 static const struct omap_gpio_platform_data omap3_pdata = {
1335 .regs = &omap2_gpio_regs,
1336 .bank_width = 32,
1337 .dbck_flag = true,
1338 };
1339
1340 static const struct omap_gpio_platform_data omap4_pdata = {
1341 .regs = &omap4_gpio_regs,
1342 .bank_width = 32,
1343 .dbck_flag = true,
1344 };
1345
1346 static const struct of_device_id omap_gpio_match[] = {
1347 {
1348 .compatible = "ti,omap4-gpio",
1349 .data = &omap4_pdata,
1350 },
1351 {
1352 .compatible = "ti,omap3-gpio",
1353 .data = &omap3_pdata,
1354 },
1355 {
1356 .compatible = "ti,omap2-gpio",
1357 .data = &omap2_pdata,
1358 },
1359 { },
1360 };
1361 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1362
1363 static int omap_gpio_probe(struct platform_device *pdev)
1364 {
1365 struct device *dev = &pdev->dev;
1366 struct device_node *node = dev->of_node;
1367 const struct of_device_id *match;
1368 const struct omap_gpio_platform_data *pdata;
1369 struct gpio_bank *bank;
1370 struct irq_chip *irqc;
1371 int ret;
1372
1373 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1374
1375 pdata = match ? match->data : dev_get_platdata(dev);
1376 if (!pdata)
1377 return -EINVAL;
1378
1379 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1380 if (!bank)
1381 return -ENOMEM;
1382
1383 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1384 if (!irqc)
1385 return -ENOMEM;
1386
1387 irqc->irq_startup = omap_gpio_irq_startup,
1388 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1389 irqc->irq_ack = dummy_irq_chip.irq_ack,
1390 irqc->irq_mask = omap_gpio_mask_irq,
1391 irqc->irq_unmask = omap_gpio_unmask_irq,
1392 irqc->irq_set_type = omap_gpio_irq_type,
1393 irqc->irq_set_wake = omap_gpio_wake_enable,
1394 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1395 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1396 irqc->name = dev_name(&pdev->dev);
1397 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1398 irqc->parent_device = dev;
1399
1400 bank->irq = platform_get_irq(pdev, 0);
1401 if (bank->irq <= 0) {
1402 if (!bank->irq)
1403 bank->irq = -ENXIO;
1404 return dev_err_probe(dev, bank->irq, "can't get irq resource\n");
1405 }
1406
1407 bank->chip.parent = dev;
1408 bank->chip.owner = THIS_MODULE;
1409 bank->dbck_flag = pdata->dbck_flag;
1410 bank->stride = pdata->bank_stride;
1411 bank->width = pdata->bank_width;
1412 bank->is_mpuio = pdata->is_mpuio;
1413 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1414 bank->regs = pdata->regs;
1415 #ifdef CONFIG_OF_GPIO
1416 bank->chip.of_node = of_node_get(node);
1417 #endif
1418
1419 if (node) {
1420 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1421 bank->loses_context = true;
1422 } else {
1423 bank->loses_context = pdata->loses_context;
1424
1425 if (bank->loses_context)
1426 bank->get_context_loss_count =
1427 pdata->get_context_loss_count;
1428 }
1429
1430 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1431 bank->set_dataout = omap_set_gpio_dataout_reg;
1432 else
1433 bank->set_dataout = omap_set_gpio_dataout_mask;
1434
1435 raw_spin_lock_init(&bank->lock);
1436 raw_spin_lock_init(&bank->wa_lock);
1437
1438 /* Static mapping, never released */
1439 bank->base = devm_platform_ioremap_resource(pdev, 0);
1440 if (IS_ERR(bank->base)) {
1441 return PTR_ERR(bank->base);
1442 }
1443
1444 if (bank->dbck_flag) {
1445 bank->dbck = devm_clk_get(dev, "dbclk");
1446 if (IS_ERR(bank->dbck)) {
1447 dev_err(dev,
1448 "Could not get gpio dbck. Disable debounce\n");
1449 bank->dbck_flag = false;
1450 } else {
1451 clk_prepare(bank->dbck);
1452 }
1453 }
1454
1455 platform_set_drvdata(pdev, bank);
1456
1457 pm_runtime_enable(dev);
1458 pm_runtime_get_sync(dev);
1459
1460 if (bank->is_mpuio)
1461 omap_mpuio_init(bank);
1462
1463 omap_gpio_mod_init(bank);
1464
1465 ret = omap_gpio_chip_init(bank, irqc);
1466 if (ret) {
1467 pm_runtime_put_sync(dev);
1468 pm_runtime_disable(dev);
1469 if (bank->dbck_flag)
1470 clk_unprepare(bank->dbck);
1471 return ret;
1472 }
1473
1474 omap_gpio_show_rev(bank);
1475
1476 bank->nb.notifier_call = gpio_omap_cpu_notifier;
1477 cpu_pm_register_notifier(&bank->nb);
1478
1479 pm_runtime_put(dev);
1480
1481 return 0;
1482 }
1483
1484 static int omap_gpio_remove(struct platform_device *pdev)
1485 {
1486 struct gpio_bank *bank = platform_get_drvdata(pdev);
1487
1488 cpu_pm_unregister_notifier(&bank->nb);
1489 gpiochip_remove(&bank->chip);
1490 pm_runtime_disable(&pdev->dev);
1491 if (bank->dbck_flag)
1492 clk_unprepare(bank->dbck);
1493
1494 return 0;
1495 }
1496
1497 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1498 {
1499 struct gpio_bank *bank = dev_get_drvdata(dev);
1500 unsigned long flags;
1501
1502 raw_spin_lock_irqsave(&bank->lock, flags);
1503 omap_gpio_idle(bank, true);
1504 bank->is_suspended = true;
1505 raw_spin_unlock_irqrestore(&bank->lock, flags);
1506
1507 return 0;
1508 }
1509
1510 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1511 {
1512 struct gpio_bank *bank = dev_get_drvdata(dev);
1513 unsigned long flags;
1514
1515 raw_spin_lock_irqsave(&bank->lock, flags);
1516 omap_gpio_unidle(bank);
1517 bank->is_suspended = false;
1518 raw_spin_unlock_irqrestore(&bank->lock, flags);
1519
1520 return 0;
1521 }
1522
1523 static int __maybe_unused omap_gpio_suspend(struct device *dev)
1524 {
1525 struct gpio_bank *bank = dev_get_drvdata(dev);
1526
1527 if (bank->is_suspended)
1528 return 0;
1529
1530 bank->needs_resume = 1;
1531
1532 return omap_gpio_runtime_suspend(dev);
1533 }
1534
1535 static int __maybe_unused omap_gpio_resume(struct device *dev)
1536 {
1537 struct gpio_bank *bank = dev_get_drvdata(dev);
1538
1539 if (!bank->needs_resume)
1540 return 0;
1541
1542 bank->needs_resume = 0;
1543
1544 return omap_gpio_runtime_resume(dev);
1545 }
1546
1547 static const struct dev_pm_ops gpio_pm_ops = {
1548 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1549 NULL)
1550 SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1551 };
1552
1553 static struct platform_driver omap_gpio_driver = {
1554 .probe = omap_gpio_probe,
1555 .remove = omap_gpio_remove,
1556 .driver = {
1557 .name = "omap_gpio",
1558 .pm = &gpio_pm_ops,
1559 .of_match_table = omap_gpio_match,
1560 },
1561 };
1562
1563 /*
1564 * gpio driver register needs to be done before
1565 * machine_init functions access gpio APIs.
1566 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1567 */
1568 static int __init omap_gpio_drv_reg(void)
1569 {
1570 return platform_driver_register(&omap_gpio_driver);
1571 }
1572 postcore_initcall(omap_gpio_drv_reg);
1573
1574 static void __exit omap_gpio_exit(void)
1575 {
1576 platform_driver_unregister(&omap_gpio_driver);
1577 }
1578 module_exit(omap_gpio_exit);
1579
1580 MODULE_DESCRIPTION("omap gpio driver");
1581 MODULE_ALIAS("platform:gpio-omap");
1582 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support