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Merge tag 'locking-urgent-2020-12-27' of git://git.kernel.org/pub/scm/linux/kernel...
[linux/fpc-iii.git] / drivers / video / fbdev / controlfb.c
blob2df56bd303d25d125c6a7813ed0bf2787abc1ec9
1 /*
2 * controlfb.c -- frame buffer device for the PowerMac 'control' display
3 *
4 * Created 12 July 1998 by Dan Jacobowitz <dan@debian.org>
5 * Copyright (C) 1998 Dan Jacobowitz
6 * Copyright (C) 2001 Takashi Oe
7 *
8 * Mmap code by Michel Lanners <mlan@cpu.lu>
9 *
10 * Frame buffer structure from:
11 * drivers/video/chipsfb.c -- frame buffer device for
12 * Chips & Technologies 65550 chip.
13 *
14 * Copyright (C) 1998 Paul Mackerras
15 *
16 * This file is derived from the Powermac "chips" driver:
17 * Copyright (C) 1997 Fabio Riccardi.
18 * And from the frame buffer device for Open Firmware-initialized devices:
19 * Copyright (C) 1997 Geert Uytterhoeven.
20 *
21 * Hardware information from:
22 * control.c: Console support for PowerMac "control" display adaptor.
23 * Copyright (C) 1996 Paul Mackerras
24 *
25 * Updated to 2.5 framebuffer API by Ben Herrenschmidt
26 * <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>,
27 * and James Simmons <jsimmons@infradead.org>.
28 *
29 * This file is subject to the terms and conditions of the GNU General Public
30 * License. See the file COPYING in the main directory of this archive for
31 * more details.
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
37 #include <linux/mm.h>
38 #include <linux/slab.h>
39 #include <linux/vmalloc.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/of.h>
43 #include <linux/of_address.h>
44 #include <linux/fb.h>
45 #include <linux/init.h>
46 #include <linux/pci.h>
47 #include <linux/nvram.h>
48 #include <linux/adb.h>
49 #include <linux/cuda.h>
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/prom.h>
52 #endif
53 #ifdef CONFIG_BOOTX_TEXT
54 #include <asm/btext.h>
55 #endif
56
57 #include "macmodes.h"
58 #include "controlfb.h"
59
60 #if !defined(CONFIG_PPC_PMAC) || !defined(CONFIG_PPC32)
61 #define invalid_vram_cache(addr)
62 #undef in_8
63 #undef out_8
64 #undef in_le32
65 #undef out_le32
66 #define in_8(addr) 0
67 #define out_8(addr, val)
68 #define in_le32(addr) 0
69 #define out_le32(addr, val)
70 #define pgprot_cached_wthru(prot) (prot)
71 #else
72 static void invalid_vram_cache(void __force *addr)
73 {
74 eieio();
75 dcbf(addr);
76 mb();
77 eieio();
78 dcbf(addr);
79 mb();
80 }
81 #endif
82
83 struct fb_par_control {
84 int vmode, cmode;
85 int xres, yres;
86 int vxres, vyres;
87 int xoffset, yoffset;
88 int pitch;
89 struct control_regvals regvals;
90 unsigned long sync;
91 unsigned char ctrl;
92 };
93
94 #define DIRTY(z) ((x)->z != (y)->z)
95 #define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z)))
96 static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y)
97 {
98 int i, results;
99
100 results = 1;
101 for (i = 0; i < 3; i++)
102 results &= !DIRTY(regvals.clock_params[i]);
103 if (!results)
104 return 0;
105 for (i = 0; i < 16; i++)
106 results &= !DIRTY(regvals.regs[i]);
107 if (!results)
108 return 0;
109 return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres)
110 && !DIRTY(vxres) && !DIRTY(vyres));
111 }
112 static inline int VAR_MATCH(struct fb_var_screeninfo *x, struct fb_var_screeninfo *y)
113 {
114 return (!DIRTY(bits_per_pixel) && !DIRTY(xres)
115 && !DIRTY(yres) && !DIRTY(xres_virtual)
116 && !DIRTY(yres_virtual)
117 && !DIRTY_CMAP(red) && !DIRTY_CMAP(green) && !DIRTY_CMAP(blue));
118 }
119
120 struct fb_info_control {
121 struct fb_info info;
122 struct fb_par_control par;
123 u32 pseudo_palette[16];
124
125 struct cmap_regs __iomem *cmap_regs;
126 unsigned long cmap_regs_phys;
127
128 struct control_regs __iomem *control_regs;
129 unsigned long control_regs_phys;
130 unsigned long control_regs_size;
131
132 __u8 __iomem *frame_buffer;
133 unsigned long frame_buffer_phys;
134 unsigned long fb_orig_base;
135 unsigned long fb_orig_size;
136
137 int control_use_bank2;
138 unsigned long total_vram;
139 unsigned char vram_attr;
140 };
141
142 /* control register access macro */
143 #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
144
145
146 /************************** Internal variables *******************************/
147
148 static struct fb_info_control *control_fb;
149
150 static int default_vmode __initdata = VMODE_NVRAM;
151 static int default_cmode __initdata = CMODE_NVRAM;
152
153
154 static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
155 u_int transp, struct fb_info *info)
156 {
157 struct fb_info_control *p =
158 container_of(info, struct fb_info_control, info);
159 __u8 r, g, b;
160
161 if (regno > 255)
162 return 1;
163
164 r = red >> 8;
165 g = green >> 8;
166 b = blue >> 8;
167
168 out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */
169 out_8(&p->cmap_regs->lut, r); /* send one color channel at */
170 out_8(&p->cmap_regs->lut, g); /* a time... */
171 out_8(&p->cmap_regs->lut, b);
172
173 if (regno < 16) {
174 int i;
175 switch (p->par.cmode) {
176 case CMODE_16:
177 p->pseudo_palette[regno] =
178 (regno << 10) | (regno << 5) | regno;
179 break;
180 case CMODE_32:
181 i = (regno << 8) | regno;
182 p->pseudo_palette[regno] = (i << 16) | i;
183 break;
184 }
185 }
186
187 return 0;
188 }
189
190
191 /******************** End of controlfb_ops implementation ******************/
192
193
194
195 static void set_control_clock(unsigned char *params)
196 {
197 #ifdef CONFIG_ADB_CUDA
198 struct adb_request req;
199 int i;
200
201 for (i = 0; i < 3; ++i) {
202 cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
203 0x50, i + 1, params[i]);
204 while (!req.complete)
205 cuda_poll();
206 }
207 #endif
208 }
209
210 /*
211 * Set screen start address according to var offset values
212 */
213 static inline void set_screen_start(int xoffset, int yoffset,
214 struct fb_info_control *p)
215 {
216 struct fb_par_control *par = &p->par;
217
218 par->xoffset = xoffset;
219 par->yoffset = yoffset;
220 out_le32(CNTRL_REG(p,start_addr),
221 par->yoffset * par->pitch + (par->xoffset << par->cmode));
222 }
223
224 #define RADACAL_WRITE(a,d) \
225 out_8(&p->cmap_regs->addr, (a)); \
226 out_8(&p->cmap_regs->dat, (d))
227
228 /* Now how about actually saying, Make it so! */
229 /* Some things in here probably don't need to be done each time. */
230 static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par)
231 {
232 struct control_regvals *r;
233 volatile struct preg __iomem *rp;
234 int i, cmode;
235
236 if (PAR_EQUAL(&p->par, par)) {
237 /*
238 * check if only xoffset or yoffset differs.
239 * this prevents flickers in typical VT switch case.
240 */
241 if (p->par.xoffset != par->xoffset ||
242 p->par.yoffset != par->yoffset)
243 set_screen_start(par->xoffset, par->yoffset, p);
244
245 return;
246 }
247
248 p->par = *par;
249 cmode = p->par.cmode;
250 r = &par->regvals;
251
252 /* Turn off display */
253 out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl);
254
255 set_control_clock(r->clock_params);
256
257 RADACAL_WRITE(0x20, r->radacal_ctrl);
258 RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1);
259 RADACAL_WRITE(0x10, 0);
260 RADACAL_WRITE(0x11, 0);
261
262 rp = &p->control_regs->vswin;
263 for (i = 0; i < 16; ++i, ++rp)
264 out_le32(&rp->r, r->regs[i]);
265
266 out_le32(CNTRL_REG(p,pitch), par->pitch);
267 out_le32(CNTRL_REG(p,mode), r->mode);
268 out_le32(CNTRL_REG(p,vram_attr), p->vram_attr);
269 out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch
270 + (par->xoffset << cmode));
271 out_le32(CNTRL_REG(p,rfrcnt), 0x1e5);
272 out_le32(CNTRL_REG(p,intr_ena), 0);
273
274 /* Turn on display */
275 out_le32(CNTRL_REG(p,ctrl), par->ctrl);
276
277 #ifdef CONFIG_BOOTX_TEXT
278 btext_update_display(p->frame_buffer_phys + CTRLFB_OFF,
279 p->par.xres, p->par.yres,
280 (cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8),
281 p->par.pitch);
282 #endif /* CONFIG_BOOTX_TEXT */
283 }
284
285 /* Work out which banks of VRAM we have installed. */
286 /* danj: I guess the card just ignores writes to nonexistant VRAM... */
287
288 static void __init find_vram_size(struct fb_info_control *p)
289 {
290 int bank1, bank2;
291
292 /*
293 * Set VRAM in 2MB (bank 1) mode
294 * VRAM Bank 2 will be accessible through offset 0x600000 if present
295 * and VRAM Bank 1 will not respond at that offset even if present
296 */
297 out_le32(CNTRL_REG(p,vram_attr), 0x31);
298
299 out_8(&p->frame_buffer[0x600000], 0xb3);
300 out_8(&p->frame_buffer[0x600001], 0x71);
301 invalid_vram_cache(&p->frame_buffer[0x600000]);
302
303 bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3)
304 && (in_8(&p->frame_buffer[0x600001]) == 0x71);
305
306 /*
307 * Set VRAM in 2MB (bank 2) mode
308 * VRAM Bank 1 will be accessible through offset 0x000000 if present
309 * and VRAM Bank 2 will not respond at that offset even if present
310 */
311 out_le32(CNTRL_REG(p,vram_attr), 0x39);
312
313 out_8(&p->frame_buffer[0], 0x5a);
314 out_8(&p->frame_buffer[1], 0xc7);
315 invalid_vram_cache(&p->frame_buffer[0]);
316
317 bank1 = (in_8(&p->frame_buffer[0]) == 0x5a)
318 && (in_8(&p->frame_buffer[1]) == 0xc7);
319
320 if (bank2) {
321 if (!bank1) {
322 /*
323 * vram bank 2 only
324 */
325 p->control_use_bank2 = 1;
326 p->vram_attr = 0x39;
327 p->frame_buffer += 0x600000;
328 p->frame_buffer_phys += 0x600000;
329 } else {
330 /*
331 * 4 MB vram
332 */
333 p->vram_attr = 0x51;
334 }
335 } else {
336 /*
337 * vram bank 1 only
338 */
339 p->vram_attr = 0x31;
340 }
341
342 p->total_vram = (bank1 + bank2) * 0x200000;
343
344 printk(KERN_INFO "controlfb: VRAM Total = %dMB "
345 "(%dMB @ bank 1, %dMB @ bank 2)\n",
346 (bank1 + bank2) << 1, bank1 << 1, bank2 << 1);
347 }
348
349 /*
350 * Get the monitor sense value.
351 * Note that this can be called before calibrate_delay,
352 * so we can't use udelay.
353 */
354 static int read_control_sense(struct fb_info_control *p)
355 {
356 int sense;
357
358 out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */
359 __delay(200);
360 out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
361 __delay(2000);
362 sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
363
364 /* drive each sense line low in turn and collect the other 2 */
365 out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */
366 __delay(2000);
367 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
368 out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */
369 __delay(2000);
370 sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
371 | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
372 out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */
373 __delay(2000);
374 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
375
376 out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
377
378 return sense;
379 }
380
381 /********************** Various translation functions **********************/
382
383 #define CONTROL_PIXCLOCK_BASE 256016
384 #define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */
385
386 /*
387 * calculate the clock paramaters to be sent to CUDA according to given
388 * pixclock in pico second.
389 */
390 static int calc_clock_params(unsigned long clk, unsigned char *param)
391 {
392 unsigned long p0, p1, p2, k, l, m, n, min;
393
394 if (clk > (CONTROL_PIXCLOCK_BASE << 3))
395 return 1;
396
397 p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2;
398 l = clk << p2;
399 p0 = 0;
400 p1 = 0;
401 for (k = 1, min = l; k < 32; k++) {
402 unsigned long rem;
403
404 m = CONTROL_PIXCLOCK_BASE * k;
405 n = m / l;
406 rem = m % l;
407 if (n && (n < 128) && rem < min) {
408 p0 = k;
409 p1 = n;
410 min = rem;
411 }
412 }
413 if (!p0 || !p1)
414 return 1;
415
416 param[0] = p0;
417 param[1] = p1;
418 param[2] = p2;
419
420 return 0;
421 }
422
423
424 /*
425 * This routine takes a user-supplied var, and picks the best vmode/cmode
426 * from it.
427 */
428
429 static int control_var_to_par(struct fb_var_screeninfo *var,
430 struct fb_par_control *par, const struct fb_info *fb_info)
431 {
432 int cmode, piped_diff, hstep;
433 unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln,
434 hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin;
435 unsigned long pixclock;
436 struct fb_info_control *p =
437 container_of(fb_info, struct fb_info_control, info);
438 struct control_regvals *r = &par->regvals;
439
440 switch (var->bits_per_pixel) {
441 case 8:
442 par->cmode = CMODE_8;
443 if (p->total_vram > 0x200000) {
444 r->mode = 3;
445 r->radacal_ctrl = 0x20;
446 piped_diff = 13;
447 } else {
448 r->mode = 2;
449 r->radacal_ctrl = 0x10;
450 piped_diff = 9;
451 }
452 break;
453 case 15:
454 case 16:
455 par->cmode = CMODE_16;
456 if (p->total_vram > 0x200000) {
457 r->mode = 2;
458 r->radacal_ctrl = 0x24;
459 piped_diff = 5;
460 } else {
461 r->mode = 1;
462 r->radacal_ctrl = 0x14;
463 piped_diff = 3;
464 }
465 break;
466 case 32:
467 par->cmode = CMODE_32;
468 if (p->total_vram > 0x200000) {
469 r->mode = 1;
470 r->radacal_ctrl = 0x28;
471 } else {
472 r->mode = 0;
473 r->radacal_ctrl = 0x18;
474 }
475 piped_diff = 1;
476 break;
477 default:
478 return -EINVAL;
479 }
480
481 /*
482 * adjust xres and vxres so that the corresponding memory widths are
483 * 32-byte aligned
484 */
485 hstep = 31 >> par->cmode;
486 par->xres = (var->xres + hstep) & ~hstep;
487 par->vxres = (var->xres_virtual + hstep) & ~hstep;
488 par->xoffset = (var->xoffset + hstep) & ~hstep;
489 if (par->vxres < par->xres)
490 par->vxres = par->xres;
491 par->pitch = par->vxres << par->cmode;
492
493 par->yres = var->yres;
494 par->vyres = var->yres_virtual;
495 par->yoffset = var->yoffset;
496 if (par->vyres < par->yres)
497 par->vyres = par->yres;
498
499 par->sync = var->sync;
500
501 if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram)
502 return -EINVAL;
503
504 if (par->xoffset + par->xres > par->vxres)
505 par->xoffset = par->vxres - par->xres;
506 if (par->yoffset + par->yres > par->vyres)
507 par->yoffset = par->vyres - par->yres;
508
509 pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN:
510 var->pixclock;
511 if (calc_clock_params(pixclock, r->clock_params))
512 return -EINVAL;
513
514 hperiod = ((var->left_margin + par->xres + var->right_margin
515 + var->hsync_len) >> 1) - 2;
516 hssync = hperiod + 1;
517 hsblank = hssync - (var->right_margin >> 1);
518 hesync = (var->hsync_len >> 1) - 1;
519 heblank = (var->left_margin >> 1) + hesync;
520 piped = heblank - piped_diff;
521 heq = var->hsync_len >> 2;
522 hlfln = (hperiod+2) >> 1;
523 hserr = hssync-hesync;
524 vperiod = (var->vsync_len + var->lower_margin + par->yres
525 + var->upper_margin) << 1;
526 vssync = vperiod - 2;
527 vesync = (var->vsync_len << 1) - vperiod + vssync;
528 veblank = (var->upper_margin << 1) + vesync;
529 vsblank = vssync - (var->lower_margin << 1);
530 vswin = (vsblank+vssync) >> 1;
531 vewin = (vesync+veblank) >> 1;
532
533 r->regs[0] = vswin;
534 r->regs[1] = vsblank;
535 r->regs[2] = veblank;
536 r->regs[3] = vewin;
537 r->regs[4] = vesync;
538 r->regs[5] = vssync;
539 r->regs[6] = vperiod;
540 r->regs[7] = piped;
541 r->regs[8] = hperiod;
542 r->regs[9] = hsblank;
543 r->regs[10] = heblank;
544 r->regs[11] = hesync;
545 r->regs[12] = hssync;
546 r->regs[13] = heq;
547 r->regs[14] = hlfln;
548 r->regs[15] = hserr;
549
550 if (par->xres >= 1280 && par->cmode >= CMODE_16)
551 par->ctrl = 0x7f;
552 else
553 par->ctrl = 0x3b;
554
555 if (mac_var_to_vmode(var, &par->vmode, &cmode))
556 par->vmode = 0;
557
558 return 0;
559 }
560
561
562 /*
563 * Convert hardware data in par to an fb_var_screeninfo
564 */
565
566 static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var)
567 {
568 struct control_regints *rv;
569
570 rv = (struct control_regints *) par->regvals.regs;
571
572 memset(var, 0, sizeof(*var));
573 var->xres = par->xres;
574 var->yres = par->yres;
575 var->xres_virtual = par->vxres;
576 var->yres_virtual = par->vyres;
577 var->xoffset = par->xoffset;
578 var->yoffset = par->yoffset;
579
580 switch(par->cmode) {
581 default:
582 case CMODE_8:
583 var->bits_per_pixel = 8;
584 var->red.length = 8;
585 var->green.length = 8;
586 var->blue.length = 8;
587 break;
588 case CMODE_16: /* RGB 555 */
589 var->bits_per_pixel = 16;
590 var->red.offset = 10;
591 var->red.length = 5;
592 var->green.offset = 5;
593 var->green.length = 5;
594 var->blue.length = 5;
595 break;
596 case CMODE_32: /* RGB 888 */
597 var->bits_per_pixel = 32;
598 var->red.offset = 16;
599 var->red.length = 8;
600 var->green.offset = 8;
601 var->green.length = 8;
602 var->blue.length = 8;
603 var->transp.offset = 24;
604 var->transp.length = 8;
605 break;
606 }
607 var->height = -1;
608 var->width = -1;
609 var->vmode = FB_VMODE_NONINTERLACED;
610
611 var->left_margin = (rv->heblank - rv->hesync) << 1;
612 var->right_margin = (rv->hssync - rv->hsblank) << 1;
613 var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1;
614
615 var->upper_margin = (rv->veblank - rv->vesync) >> 1;
616 var->lower_margin = (rv->vssync - rv->vsblank) >> 1;
617 var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1;
618
619 var->sync = par->sync;
620
621 /*
622 * 10^12 * clock_params[0] / (3906400 * clock_params[1]
623 * * 2^clock_params[2])
624 * (10^12 * clock_params[0] / (3906400 * clock_params[1]))
625 * >> clock_params[2]
626 */
627 /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */
628 var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0];
629 var->pixclock /= par->regvals.clock_params[1];
630 var->pixclock >>= par->regvals.clock_params[2];
631 }
632
633 /******************** The functions for controlfb_ops ********************/
634
635 /*
636 * Checks a var structure
637 */
638 static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
639 {
640 struct fb_par_control par;
641 int err;
642
643 err = control_var_to_par(var, &par, info);
644 if (err)
645 return err;
646 control_par_to_var(&par, var);
647
648 return 0;
649 }
650
651 /*
652 * Applies current var to display
653 */
654 static int controlfb_set_par (struct fb_info *info)
655 {
656 struct fb_info_control *p =
657 container_of(info, struct fb_info_control, info);
658 struct fb_par_control par;
659 int err;
660
661 if((err = control_var_to_par(&info->var, &par, info))) {
662 printk (KERN_ERR "controlfb_set_par: error calling"
663 " control_var_to_par: %d.\n", err);
664 return err;
665 }
666
667 control_set_hardware(p, &par);
668
669 info->fix.visual = (p->par.cmode == CMODE_8) ?
670 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
671 info->fix.line_length = p->par.pitch;
672 info->fix.xpanstep = 32 >> p->par.cmode;
673 info->fix.ypanstep = 1;
674
675 return 0;
676 }
677
678 static int controlfb_pan_display(struct fb_var_screeninfo *var,
679 struct fb_info *info)
680 {
681 unsigned int xoffset, hstep;
682 struct fb_info_control *p =
683 container_of(info, struct fb_info_control, info);
684 struct fb_par_control *par = &p->par;
685
686 /*
687 * make sure start addr will be 32-byte aligned
688 */
689 hstep = 0x1f >> par->cmode;
690 xoffset = (var->xoffset + hstep) & ~hstep;
691
692 if (xoffset+par->xres > par->vxres ||
693 var->yoffset+par->yres > par->vyres)
694 return -EINVAL;
695
696 set_screen_start(xoffset, var->yoffset, p);
697
698 return 0;
699 }
700
701 static int controlfb_blank(int blank_mode, struct fb_info *info)
702 {
703 struct fb_info_control __maybe_unused *p =
704 container_of(info, struct fb_info_control, info);
705 unsigned ctrl;
706
707 ctrl = in_le32(CNTRL_REG(p, ctrl));
708 if (blank_mode > 0)
709 switch (blank_mode) {
710 case FB_BLANK_VSYNC_SUSPEND:
711 ctrl &= ~3;
712 break;
713 case FB_BLANK_HSYNC_SUSPEND:
714 ctrl &= ~0x30;
715 break;
716 case FB_BLANK_POWERDOWN:
717 ctrl &= ~0x33;
718 fallthrough;
719 case FB_BLANK_NORMAL:
720 ctrl |= 0x400;
721 break;
722 default:
723 break;
724 }
725 else {
726 ctrl &= ~0x400;
727 ctrl |= 0x33;
728 }
729 out_le32(CNTRL_REG(p,ctrl), ctrl);
730
731 return 0;
732 }
733
734 /*
735 * Private mmap since we want to have a different caching on the framebuffer
736 * for controlfb.
737 * Note there's no locking in here; it's done in fb_mmap() in fbmem.c.
738 */
739 static int controlfb_mmap(struct fb_info *info,
740 struct vm_area_struct *vma)
741 {
742 unsigned long mmio_pgoff;
743 unsigned long start;
744 u32 len;
745
746 start = info->fix.smem_start;
747 len = info->fix.smem_len;
748 mmio_pgoff = PAGE_ALIGN((start & ~PAGE_MASK) + len) >> PAGE_SHIFT;
749 if (vma->vm_pgoff >= mmio_pgoff) {
750 if (info->var.accel_flags)
751 return -EINVAL;
752 vma->vm_pgoff -= mmio_pgoff;
753 start = info->fix.mmio_start;
754 len = info->fix.mmio_len;
755 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
756 } else {
757 /* framebuffer */
758 vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot);
759 }
760
761 return vm_iomap_memory(vma, start, len);
762 }
763
764 static const struct fb_ops controlfb_ops = {
765 .owner = THIS_MODULE,
766 .fb_check_var = controlfb_check_var,
767 .fb_set_par = controlfb_set_par,
768 .fb_setcolreg = controlfb_setcolreg,
769 .fb_pan_display = controlfb_pan_display,
770 .fb_blank = controlfb_blank,
771 .fb_mmap = controlfb_mmap,
772 .fb_fillrect = cfb_fillrect,
773 .fb_copyarea = cfb_copyarea,
774 .fb_imageblit = cfb_imageblit,
775 };
776
777 /*
778 * Set misc info vars for this driver
779 */
780 static void __init control_init_info(struct fb_info *info, struct fb_info_control *p)
781 {
782 /* Fill fb_info */
783 info->par = &p->par;
784 info->fbops = &controlfb_ops;
785 info->pseudo_palette = p->pseudo_palette;
786 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
787 info->screen_base = p->frame_buffer + CTRLFB_OFF;
788
789 fb_alloc_cmap(&info->cmap, 256, 0);
790
791 /* Fill fix common fields */
792 strcpy(info->fix.id, "control");
793 info->fix.mmio_start = p->control_regs_phys;
794 info->fix.mmio_len = sizeof(struct control_regs);
795 info->fix.type = FB_TYPE_PACKED_PIXELS;
796 info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF;
797 info->fix.smem_len = p->total_vram - CTRLFB_OFF;
798 info->fix.ywrapstep = 0;
799 info->fix.type_aux = 0;
800 info->fix.accel = FB_ACCEL_NONE;
801 }
802
803 /*
804 * Parse user specified options (`video=controlfb:')
805 */
806 static void __init control_setup(char *options)
807 {
808 char *this_opt;
809
810 if (!options || !*options)
811 return;
812
813 while ((this_opt = strsep(&options, ",")) != NULL) {
814 if (!strncmp(this_opt, "vmode:", 6)) {
815 int vmode = simple_strtoul(this_opt+6, NULL, 0);
816 if (vmode > 0 && vmode <= VMODE_MAX &&
817 control_mac_modes[vmode - 1].m[1] >= 0)
818 default_vmode = vmode;
819 } else if (!strncmp(this_opt, "cmode:", 6)) {
820 int depth = simple_strtoul(this_opt+6, NULL, 0);
821 switch (depth) {
822 case CMODE_8:
823 case CMODE_16:
824 case CMODE_32:
825 default_cmode = depth;
826 break;
827 case 8:
828 default_cmode = CMODE_8;
829 break;
830 case 15:
831 case 16:
832 default_cmode = CMODE_16;
833 break;
834 case 24:
835 case 32:
836 default_cmode = CMODE_32;
837 break;
838 }
839 }
840 }
841 }
842
843 /*
844 * finish off the driver initialization and register
845 */
846 static int __init init_control(struct fb_info_control *p)
847 {
848 int full, sense, vmode, cmode, vyres;
849 struct fb_var_screeninfo var;
850 int rc;
851
852 printk(KERN_INFO "controlfb: ");
853
854 full = p->total_vram == 0x400000;
855
856 /* Try to pick a video mode out of NVRAM if we have one. */
857 cmode = default_cmode;
858 if (IS_REACHABLE(CONFIG_NVRAM) && cmode == CMODE_NVRAM)
859 cmode = nvram_read_byte(NV_CMODE);
860 if (cmode < CMODE_8 || cmode > CMODE_32)
861 cmode = CMODE_8;
862
863 vmode = default_vmode;
864 if (IS_REACHABLE(CONFIG_NVRAM) && vmode == VMODE_NVRAM)
865 vmode = nvram_read_byte(NV_VMODE);
866 if (vmode < 1 || vmode > VMODE_MAX ||
867 control_mac_modes[vmode - 1].m[full] < cmode) {
868 sense = read_control_sense(p);
869 printk(KERN_CONT "Monitor sense value = 0x%x, ", sense);
870 vmode = mac_map_monitor_sense(sense);
871 if (control_mac_modes[vmode - 1].m[full] < 0)
872 vmode = VMODE_640_480_60;
873 cmode = min(cmode, control_mac_modes[vmode - 1].m[full]);
874 }
875
876 /* Initialize info structure */
877 control_init_info(&p->info, p);
878
879 /* Setup default var */
880 if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
881 /* This shouldn't happen! */
882 printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode);
883 try_again:
884 vmode = VMODE_640_480_60;
885 cmode = CMODE_8;
886 if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
887 printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n");
888 return -ENXIO;
889 }
890 printk(KERN_INFO "controlfb: ");
891 }
892 printk("using video mode %d and color mode %d.\n", vmode, cmode);
893
894 vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode);
895 if (vyres > var.yres)
896 var.yres_virtual = vyres;
897
898 /* Apply default var */
899 var.activate = FB_ACTIVATE_NOW;
900 rc = fb_set_var(&p->info, &var);
901 if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8))
902 goto try_again;
903
904 /* Register with fbdev layer */
905 if (register_framebuffer(&p->info) < 0)
906 return -ENXIO;
907
908 fb_info(&p->info, "control display adapter\n");
909
910 return 0;
911 }
912
913 static void control_cleanup(void)
914 {
915 struct fb_info_control *p = control_fb;
916
917 if (!p)
918 return;
919
920 if (p->cmap_regs)
921 iounmap(p->cmap_regs);
922 if (p->control_regs)
923 iounmap(p->control_regs);
924 if (p->frame_buffer) {
925 if (p->control_use_bank2)
926 p->frame_buffer -= 0x600000;
927 iounmap(p->frame_buffer);
928 }
929 if (p->cmap_regs_phys)
930 release_mem_region(p->cmap_regs_phys, 0x1000);
931 if (p->control_regs_phys)
932 release_mem_region(p->control_regs_phys, p->control_regs_size);
933 if (p->fb_orig_base)
934 release_mem_region(p->fb_orig_base, p->fb_orig_size);
935 kfree(p);
936 }
937
938 /*
939 * find "control" and initialize
940 */
941 static int __init control_of_init(struct device_node *dp)
942 {
943 struct fb_info_control *p;
944 struct resource fb_res, reg_res;
945
946 if (control_fb) {
947 printk(KERN_ERR "controlfb: only one control is supported\n");
948 return -ENXIO;
949 }
950
951 if (of_pci_address_to_resource(dp, 2, &fb_res) ||
952 of_pci_address_to_resource(dp, 1, &reg_res)) {
953 printk(KERN_ERR "can't get 2 addresses for control\n");
954 return -ENXIO;
955 }
956 p = kzalloc(sizeof(*p), GFP_KERNEL);
957 if (!p)
958 return -ENOMEM;
959 control_fb = p; /* save it for cleanups */
960
961 /* Map in frame buffer and registers */
962 p->fb_orig_base = fb_res.start;
963 p->fb_orig_size = resource_size(&fb_res);
964 /* use the big-endian aperture (??) */
965 p->frame_buffer_phys = fb_res.start + 0x800000;
966 p->control_regs_phys = reg_res.start;
967 p->control_regs_size = resource_size(&reg_res);
968
969 if (!p->fb_orig_base ||
970 !request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) {
971 p->fb_orig_base = 0;
972 goto error_out;
973 }
974 /* map at most 8MB for the frame buffer */
975 p->frame_buffer = ioremap_wt(p->frame_buffer_phys, 0x800000);
976
977 if (!p->control_regs_phys ||
978 !request_mem_region(p->control_regs_phys, p->control_regs_size,
979 "controlfb regs")) {
980 p->control_regs_phys = 0;
981 goto error_out;
982 }
983 p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size);
984
985 p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
986 if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) {
987 p->cmap_regs_phys = 0;
988 goto error_out;
989 }
990 p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
991
992 if (!p->cmap_regs || !p->control_regs || !p->frame_buffer)
993 goto error_out;
994
995 find_vram_size(p);
996 if (!p->total_vram)
997 goto error_out;
998
999 if (init_control(p) < 0)
1000 goto error_out;
1001
1002 return 0;
1003
1004 error_out:
1005 control_cleanup();
1006 return -ENXIO;
1007 }
1008
1009 static int __init control_init(void)
1010 {
1011 struct device_node *dp;
1012 char *option = NULL;
1013 int ret = -ENXIO;
1014
1015 if (fb_get_options("controlfb", &option))
1016 return -ENODEV;
1017 control_setup(option);
1018
1019 dp = of_find_node_by_name(NULL, "control");
1020 if (dp && !control_of_init(dp))
1021 ret = 0;
1022 of_node_put(dp);
1023
1024 return ret;
1025 }
1026
1027 device_initcall(control_init);
Linux with added FPC-III support