?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19-rc5
[linux/fpc-iii.git] / drivers / tty / serial / mvebu-uart.c
blobd04b5eeea3c6989e9313c00d1085bbd801ffe9cd
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ***************************************************************************
4 * Marvell Armada-3700 Serial Driver
5 * Author: Wilson Ding <dingwei@marvell.com>
6 * Copyright (C) 2015 Marvell International Ltd.
7 * ***************************************************************************
8 */
9
10 #include <linux/clk.h>
11 #include <linux/console.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/iopoll.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28
29 /* Register Map */
30 #define UART_STD_RBR 0x00
31 #define UART_EXT_RBR 0x18
32
33 #define UART_STD_TSH 0x04
34 #define UART_EXT_TSH 0x1C
35
36 #define UART_STD_CTRL1 0x08
37 #define UART_EXT_CTRL1 0x04
38 #define CTRL_SOFT_RST BIT(31)
39 #define CTRL_TXFIFO_RST BIT(15)
40 #define CTRL_RXFIFO_RST BIT(14)
41 #define CTRL_SND_BRK_SEQ BIT(11)
42 #define CTRL_BRK_DET_INT BIT(3)
43 #define CTRL_FRM_ERR_INT BIT(2)
44 #define CTRL_PAR_ERR_INT BIT(1)
45 #define CTRL_OVR_ERR_INT BIT(0)
46 #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
47 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
48
49 #define UART_STD_CTRL2 UART_STD_CTRL1
50 #define UART_EXT_CTRL2 0x20
51 #define CTRL_STD_TX_RDY_INT BIT(5)
52 #define CTRL_EXT_TX_RDY_INT BIT(6)
53 #define CTRL_STD_RX_RDY_INT BIT(4)
54 #define CTRL_EXT_RX_RDY_INT BIT(5)
55
56 #define UART_STAT 0x0C
57 #define STAT_TX_FIFO_EMP BIT(13)
58 #define STAT_TX_FIFO_FUL BIT(11)
59 #define STAT_TX_EMP BIT(6)
60 #define STAT_STD_TX_RDY BIT(5)
61 #define STAT_EXT_TX_RDY BIT(15)
62 #define STAT_STD_RX_RDY BIT(4)
63 #define STAT_EXT_RX_RDY BIT(14)
64 #define STAT_BRK_DET BIT(3)
65 #define STAT_FRM_ERR BIT(2)
66 #define STAT_PAR_ERR BIT(1)
67 #define STAT_OVR_ERR BIT(0)
68 #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \
69 | STAT_PAR_ERR | STAT_OVR_ERR)
70
71 #define UART_BRDV 0x10
72 #define BRDV_BAUD_MASK 0x3FF
73
74 #define UART_OSAMP 0x14
75
76 #define MVEBU_NR_UARTS 2
77
78 #define MVEBU_UART_TYPE "mvebu-uart"
79 #define DRIVER_NAME "mvebu_serial"
80
81 enum {
82 /* Either there is only one summed IRQ... */
83 UART_IRQ_SUM = 0,
84 /* ...or there are two separate IRQ for RX and TX */
85 UART_RX_IRQ = 0,
86 UART_TX_IRQ,
87 UART_IRQ_COUNT
88 };
89
90 /* Diverging register offsets */
91 struct uart_regs_layout {
92 unsigned int rbr;
93 unsigned int tsh;
94 unsigned int ctrl;
95 unsigned int intr;
96 };
97
98 /* Diverging flags */
99 struct uart_flags {
100 unsigned int ctrl_tx_rdy_int;
101 unsigned int ctrl_rx_rdy_int;
102 unsigned int stat_tx_rdy;
103 unsigned int stat_rx_rdy;
104 };
105
106 /* Driver data, a structure for each UART port */
107 struct mvebu_uart_driver_data {
108 bool is_ext;
109 struct uart_regs_layout regs;
110 struct uart_flags flags;
111 };
112
113 /* Saved registers during suspend */
114 struct mvebu_uart_pm_regs {
115 unsigned int rbr;
116 unsigned int tsh;
117 unsigned int ctrl;
118 unsigned int intr;
119 unsigned int stat;
120 unsigned int brdv;
121 unsigned int osamp;
122 };
123
124 /* MVEBU UART driver structure */
125 struct mvebu_uart {
126 struct uart_port *port;
127 struct clk *clk;
128 int irq[UART_IRQ_COUNT];
129 unsigned char __iomem *nb;
130 struct mvebu_uart_driver_data *data;
131 #if defined(CONFIG_PM)
132 struct mvebu_uart_pm_regs pm_regs;
133 #endif /* CONFIG_PM */
134 };
135
136 static struct mvebu_uart *to_mvuart(struct uart_port *port)
137 {
138 return (struct mvebu_uart *)port->private_data;
139 }
140
141 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
142
143 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
144 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
145 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
146 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
147
148 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
149 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
150 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
151 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
152
153 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
154
155 /* Core UART Driver Operations */
156 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
157 {
158 unsigned long flags;
159 unsigned int st;
160
161 spin_lock_irqsave(&port->lock, flags);
162 st = readl(port->membase + UART_STAT);
163 spin_unlock_irqrestore(&port->lock, flags);
164
165 return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
166 }
167
168 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
169 {
170 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
171 }
172
173 static void mvebu_uart_set_mctrl(struct uart_port *port,
174 unsigned int mctrl)
175 {
176 /*
177 * Even if we do not support configuring the modem control lines, this
178 * function must be proided to the serial core
179 */
180 }
181
182 static void mvebu_uart_stop_tx(struct uart_port *port)
183 {
184 unsigned int ctl = readl(port->membase + UART_INTR(port));
185
186 ctl &= ~CTRL_TX_RDY_INT(port);
187 writel(ctl, port->membase + UART_INTR(port));
188 }
189
190 static void mvebu_uart_start_tx(struct uart_port *port)
191 {
192 unsigned int ctl;
193 struct circ_buf *xmit = &port->state->xmit;
194
195 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
196 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
197 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
198 port->icount.tx++;
199 }
200
201 ctl = readl(port->membase + UART_INTR(port));
202 ctl |= CTRL_TX_RDY_INT(port);
203 writel(ctl, port->membase + UART_INTR(port));
204 }
205
206 static void mvebu_uart_stop_rx(struct uart_port *port)
207 {
208 unsigned int ctl;
209
210 ctl = readl(port->membase + UART_CTRL(port));
211 ctl &= ~CTRL_BRK_INT;
212 writel(ctl, port->membase + UART_CTRL(port));
213
214 ctl = readl(port->membase + UART_INTR(port));
215 ctl &= ~CTRL_RX_RDY_INT(port);
216 writel(ctl, port->membase + UART_INTR(port));
217 }
218
219 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
220 {
221 unsigned int ctl;
222 unsigned long flags;
223
224 spin_lock_irqsave(&port->lock, flags);
225 ctl = readl(port->membase + UART_CTRL(port));
226 if (brk == -1)
227 ctl |= CTRL_SND_BRK_SEQ;
228 else
229 ctl &= ~CTRL_SND_BRK_SEQ;
230 writel(ctl, port->membase + UART_CTRL(port));
231 spin_unlock_irqrestore(&port->lock, flags);
232 }
233
234 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
235 {
236 struct tty_port *tport = &port->state->port;
237 unsigned char ch = 0;
238 char flag = 0;
239
240 do {
241 if (status & STAT_RX_RDY(port)) {
242 ch = readl(port->membase + UART_RBR(port));
243 ch &= 0xff;
244 flag = TTY_NORMAL;
245 port->icount.rx++;
246
247 if (status & STAT_PAR_ERR)
248 port->icount.parity++;
249 }
250
251 if (status & STAT_BRK_DET) {
252 port->icount.brk++;
253 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
254 if (uart_handle_break(port))
255 goto ignore_char;
256 }
257
258 if (status & STAT_OVR_ERR)
259 port->icount.overrun++;
260
261 if (status & STAT_FRM_ERR)
262 port->icount.frame++;
263
264 if (uart_handle_sysrq_char(port, ch))
265 goto ignore_char;
266
267 if (status & port->ignore_status_mask & STAT_PAR_ERR)
268 status &= ~STAT_RX_RDY(port);
269
270 status &= port->read_status_mask;
271
272 if (status & STAT_PAR_ERR)
273 flag = TTY_PARITY;
274
275 status &= ~port->ignore_status_mask;
276
277 if (status & STAT_RX_RDY(port))
278 tty_insert_flip_char(tport, ch, flag);
279
280 if (status & STAT_BRK_DET)
281 tty_insert_flip_char(tport, 0, TTY_BREAK);
282
283 if (status & STAT_FRM_ERR)
284 tty_insert_flip_char(tport, 0, TTY_FRAME);
285
286 if (status & STAT_OVR_ERR)
287 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
288
289 ignore_char:
290 status = readl(port->membase + UART_STAT);
291 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
292
293 tty_flip_buffer_push(tport);
294 }
295
296 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
297 {
298 struct circ_buf *xmit = &port->state->xmit;
299 unsigned int count;
300 unsigned int st;
301
302 if (port->x_char) {
303 writel(port->x_char, port->membase + UART_TSH(port));
304 port->icount.tx++;
305 port->x_char = 0;
306 return;
307 }
308
309 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
310 mvebu_uart_stop_tx(port);
311 return;
312 }
313
314 for (count = 0; count < port->fifosize; count++) {
315 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
316 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
317 port->icount.tx++;
318
319 if (uart_circ_empty(xmit))
320 break;
321
322 st = readl(port->membase + UART_STAT);
323 if (st & STAT_TX_FIFO_FUL)
324 break;
325 }
326
327 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
328 uart_write_wakeup(port);
329
330 if (uart_circ_empty(xmit))
331 mvebu_uart_stop_tx(port);
332 }
333
334 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
335 {
336 struct uart_port *port = (struct uart_port *)dev_id;
337 unsigned int st = readl(port->membase + UART_STAT);
338
339 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
340 STAT_BRK_DET))
341 mvebu_uart_rx_chars(port, st);
342
343 if (st & STAT_TX_RDY(port))
344 mvebu_uart_tx_chars(port, st);
345
346 return IRQ_HANDLED;
347 }
348
349 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
350 {
351 struct uart_port *port = (struct uart_port *)dev_id;
352 unsigned int st = readl(port->membase + UART_STAT);
353
354 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
355 STAT_BRK_DET))
356 mvebu_uart_rx_chars(port, st);
357
358 return IRQ_HANDLED;
359 }
360
361 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
362 {
363 struct uart_port *port = (struct uart_port *)dev_id;
364 unsigned int st = readl(port->membase + UART_STAT);
365
366 if (st & STAT_TX_RDY(port))
367 mvebu_uart_tx_chars(port, st);
368
369 return IRQ_HANDLED;
370 }
371
372 static int mvebu_uart_startup(struct uart_port *port)
373 {
374 struct mvebu_uart *mvuart = to_mvuart(port);
375 unsigned int ctl;
376 int ret;
377
378 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
379 port->membase + UART_CTRL(port));
380 udelay(1);
381
382 /* Clear the error bits of state register before IRQ request */
383 ret = readl(port->membase + UART_STAT);
384 ret |= STAT_BRK_ERR;
385 writel(ret, port->membase + UART_STAT);
386
387 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
388
389 ctl = readl(port->membase + UART_INTR(port));
390 ctl |= CTRL_RX_RDY_INT(port);
391 writel(ctl, port->membase + UART_INTR(port));
392
393 if (!mvuart->irq[UART_TX_IRQ]) {
394 /* Old bindings with just one interrupt (UART0 only) */
395 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
396 mvebu_uart_isr, port->irqflags,
397 dev_name(port->dev), port);
398 if (ret) {
399 dev_err(port->dev, "unable to request IRQ %d\n",
400 mvuart->irq[UART_IRQ_SUM]);
401 return ret;
402 }
403 } else {
404 /* New bindings with an IRQ for RX and TX (both UART) */
405 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
406 mvebu_uart_rx_isr, port->irqflags,
407 dev_name(port->dev), port);
408 if (ret) {
409 dev_err(port->dev, "unable to request IRQ %d\n",
410 mvuart->irq[UART_RX_IRQ]);
411 return ret;
412 }
413
414 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
415 mvebu_uart_tx_isr, port->irqflags,
416 dev_name(port->dev),
417 port);
418 if (ret) {
419 dev_err(port->dev, "unable to request IRQ %d\n",
420 mvuart->irq[UART_TX_IRQ]);
421 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
422 port);
423 return ret;
424 }
425 }
426
427 return 0;
428 }
429
430 static void mvebu_uart_shutdown(struct uart_port *port)
431 {
432 struct mvebu_uart *mvuart = to_mvuart(port);
433
434 writel(0, port->membase + UART_INTR(port));
435
436 if (!mvuart->irq[UART_TX_IRQ]) {
437 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
438 } else {
439 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
440 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
441 }
442 }
443
444 static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
445 {
446 struct mvebu_uart *mvuart = to_mvuart(port);
447 unsigned int baud_rate_div;
448 u32 brdv;
449
450 if (IS_ERR(mvuart->clk))
451 return -PTR_ERR(mvuart->clk);
452
453 /*
454 * The UART clock is divided by the value of the divisor to generate
455 * UCLK_OUT clock, which is 16 times faster than the baudrate.
456 * This prescaler can achieve all standard baudrates until 230400.
457 * Higher baudrates could be achieved for the extended UART by using the
458 * programmable oversampling stack (also called fractional divisor).
459 */
460 baud_rate_div = DIV_ROUND_UP(port->uartclk, baud * 16);
461 brdv = readl(port->membase + UART_BRDV);
462 brdv &= ~BRDV_BAUD_MASK;
463 brdv |= baud_rate_div;
464 writel(brdv, port->membase + UART_BRDV);
465
466 return 0;
467 }
468
469 static void mvebu_uart_set_termios(struct uart_port *port,
470 struct ktermios *termios,
471 struct ktermios *old)
472 {
473 unsigned long flags;
474 unsigned int baud;
475
476 spin_lock_irqsave(&port->lock, flags);
477
478 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
479 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
480
481 if (termios->c_iflag & INPCK)
482 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
483
484 port->ignore_status_mask = 0;
485 if (termios->c_iflag & IGNPAR)
486 port->ignore_status_mask |=
487 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
488
489 if ((termios->c_cflag & CREAD) == 0)
490 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
491
492 /*
493 * Maximum achievable frequency with simple baudrate divisor is 230400.
494 * Since the error per bit frame would be of more than 15%, achieving
495 * higher frequencies would require to implement the fractional divisor
496 * feature.
497 */
498 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
499 if (mvebu_uart_baud_rate_set(port, baud)) {
500 /* No clock available, baudrate cannot be changed */
501 if (old)
502 baud = uart_get_baud_rate(port, old, NULL, 0, 230400);
503 } else {
504 tty_termios_encode_baud_rate(termios, baud, baud);
505 uart_update_timeout(port, termios->c_cflag, baud);
506 }
507
508 /* Only the following flag changes are supported */
509 if (old) {
510 termios->c_iflag &= INPCK | IGNPAR;
511 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
512 termios->c_cflag &= CREAD | CBAUD;
513 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
514 }
515
516 spin_unlock_irqrestore(&port->lock, flags);
517 }
518
519 static const char *mvebu_uart_type(struct uart_port *port)
520 {
521 return MVEBU_UART_TYPE;
522 }
523
524 static void mvebu_uart_release_port(struct uart_port *port)
525 {
526 /* Nothing to do here */
527 }
528
529 static int mvebu_uart_request_port(struct uart_port *port)
530 {
531 return 0;
532 }
533
534 #ifdef CONFIG_CONSOLE_POLL
535 static int mvebu_uart_get_poll_char(struct uart_port *port)
536 {
537 unsigned int st = readl(port->membase + UART_STAT);
538
539 if (!(st & STAT_RX_RDY(port)))
540 return NO_POLL_CHAR;
541
542 return readl(port->membase + UART_RBR(port));
543 }
544
545 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
546 {
547 unsigned int st;
548
549 for (;;) {
550 st = readl(port->membase + UART_STAT);
551
552 if (!(st & STAT_TX_FIFO_FUL))
553 break;
554
555 udelay(1);
556 }
557
558 writel(c, port->membase + UART_TSH(port));
559 }
560 #endif
561
562 static const struct uart_ops mvebu_uart_ops = {
563 .tx_empty = mvebu_uart_tx_empty,
564 .set_mctrl = mvebu_uart_set_mctrl,
565 .get_mctrl = mvebu_uart_get_mctrl,
566 .stop_tx = mvebu_uart_stop_tx,
567 .start_tx = mvebu_uart_start_tx,
568 .stop_rx = mvebu_uart_stop_rx,
569 .break_ctl = mvebu_uart_break_ctl,
570 .startup = mvebu_uart_startup,
571 .shutdown = mvebu_uart_shutdown,
572 .set_termios = mvebu_uart_set_termios,
573 .type = mvebu_uart_type,
574 .release_port = mvebu_uart_release_port,
575 .request_port = mvebu_uart_request_port,
576 #ifdef CONFIG_CONSOLE_POLL
577 .poll_get_char = mvebu_uart_get_poll_char,
578 .poll_put_char = mvebu_uart_put_poll_char,
579 #endif
580 };
581
582 /* Console Driver Operations */
583
584 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
585 /* Early Console */
586 static void mvebu_uart_putc(struct uart_port *port, int c)
587 {
588 unsigned int st;
589
590 for (;;) {
591 st = readl(port->membase + UART_STAT);
592 if (!(st & STAT_TX_FIFO_FUL))
593 break;
594 }
595
596 /* At early stage, DT is not parsed yet, only use UART0 */
597 writel(c, port->membase + UART_STD_TSH);
598
599 for (;;) {
600 st = readl(port->membase + UART_STAT);
601 if (st & STAT_TX_FIFO_EMP)
602 break;
603 }
604 }
605
606 static void mvebu_uart_putc_early_write(struct console *con,
607 const char *s,
608 unsigned n)
609 {
610 struct earlycon_device *dev = con->data;
611
612 uart_console_write(&dev->port, s, n, mvebu_uart_putc);
613 }
614
615 static int __init
616 mvebu_uart_early_console_setup(struct earlycon_device *device,
617 const char *opt)
618 {
619 if (!device->port.membase)
620 return -ENODEV;
621
622 device->con->write = mvebu_uart_putc_early_write;
623
624 return 0;
625 }
626
627 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
628 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
629 mvebu_uart_early_console_setup);
630
631 static void wait_for_xmitr(struct uart_port *port)
632 {
633 u32 val;
634
635 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
636 (val & STAT_TX_RDY(port)), 1, 10000);
637 }
638
639 static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
640 {
641 wait_for_xmitr(port);
642 writel(ch, port->membase + UART_TSH(port));
643 }
644
645 static void mvebu_uart_console_write(struct console *co, const char *s,
646 unsigned int count)
647 {
648 struct uart_port *port = &mvebu_uart_ports[co->index];
649 unsigned long flags;
650 unsigned int ier, intr, ctl;
651 int locked = 1;
652
653 if (oops_in_progress)
654 locked = spin_trylock_irqsave(&port->lock, flags);
655 else
656 spin_lock_irqsave(&port->lock, flags);
657
658 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
659 intr = readl(port->membase + UART_INTR(port)) &
660 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
661 writel(0, port->membase + UART_CTRL(port));
662 writel(0, port->membase + UART_INTR(port));
663
664 uart_console_write(port, s, count, mvebu_uart_console_putchar);
665
666 wait_for_xmitr(port);
667
668 if (ier)
669 writel(ier, port->membase + UART_CTRL(port));
670
671 if (intr) {
672 ctl = intr | readl(port->membase + UART_INTR(port));
673 writel(ctl, port->membase + UART_INTR(port));
674 }
675
676 if (locked)
677 spin_unlock_irqrestore(&port->lock, flags);
678 }
679
680 static int mvebu_uart_console_setup(struct console *co, char *options)
681 {
682 struct uart_port *port;
683 int baud = 9600;
684 int bits = 8;
685 int parity = 'n';
686 int flow = 'n';
687
688 if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
689 return -EINVAL;
690
691 port = &mvebu_uart_ports[co->index];
692
693 if (!port->mapbase || !port->membase) {
694 pr_debug("console on ttyMV%i not present\n", co->index);
695 return -ENODEV;
696 }
697
698 if (options)
699 uart_parse_options(options, &baud, &parity, &bits, &flow);
700
701 return uart_set_options(port, co, baud, parity, bits, flow);
702 }
703
704 static struct uart_driver mvebu_uart_driver;
705
706 static struct console mvebu_uart_console = {
707 .name = "ttyMV",
708 .write = mvebu_uart_console_write,
709 .device = uart_console_device,
710 .setup = mvebu_uart_console_setup,
711 .flags = CON_PRINTBUFFER,
712 .index = -1,
713 .data = &mvebu_uart_driver,
714 };
715
716 static int __init mvebu_uart_console_init(void)
717 {
718 register_console(&mvebu_uart_console);
719 return 0;
720 }
721
722 console_initcall(mvebu_uart_console_init);
723
724
725 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
726
727 static struct uart_driver mvebu_uart_driver = {
728 .owner = THIS_MODULE,
729 .driver_name = DRIVER_NAME,
730 .dev_name = "ttyMV",
731 .nr = MVEBU_NR_UARTS,
732 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
733 .cons = &mvebu_uart_console,
734 #endif
735 };
736
737 #if defined(CONFIG_PM)
738 static int mvebu_uart_suspend(struct device *dev)
739 {
740 struct mvebu_uart *mvuart = dev_get_drvdata(dev);
741 struct uart_port *port = mvuart->port;
742
743 uart_suspend_port(&mvebu_uart_driver, port);
744
745 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
746 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
747 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
748 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
749 mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
750 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
751 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
752
753 device_set_wakeup_enable(dev, true);
754
755 return 0;
756 }
757
758 static int mvebu_uart_resume(struct device *dev)
759 {
760 struct mvebu_uart *mvuart = dev_get_drvdata(dev);
761 struct uart_port *port = mvuart->port;
762
763 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
764 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
765 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
766 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
767 writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
768 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
769 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
770
771 uart_resume_port(&mvebu_uart_driver, port);
772
773 return 0;
774 }
775
776 static const struct dev_pm_ops mvebu_uart_pm_ops = {
777 .suspend = mvebu_uart_suspend,
778 .resume = mvebu_uart_resume,
779 };
780 #endif /* CONFIG_PM */
781
782 static const struct of_device_id mvebu_uart_of_match[];
783
784 /* Counter to keep track of each UART port id when not using CONFIG_OF */
785 static int uart_num_counter;
786
787 static int mvebu_uart_probe(struct platform_device *pdev)
788 {
789 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
790 const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
791 &pdev->dev);
792 struct uart_port *port;
793 struct mvebu_uart *mvuart;
794 int ret, id, irq;
795
796 if (!reg) {
797 dev_err(&pdev->dev, "no registers defined\n");
798 return -EINVAL;
799 }
800
801 /* Assume that all UART ports have a DT alias or none has */
802 id = of_alias_get_id(pdev->dev.of_node, "serial");
803 if (!pdev->dev.of_node || id < 0)
804 pdev->id = uart_num_counter++;
805 else
806 pdev->id = id;
807
808 if (pdev->id >= MVEBU_NR_UARTS) {
809 dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
810 MVEBU_NR_UARTS);
811 return -EINVAL;
812 }
813
814 port = &mvebu_uart_ports[pdev->id];
815
816 spin_lock_init(&port->lock);
817
818 port->dev = &pdev->dev;
819 port->type = PORT_MVEBU;
820 port->ops = &mvebu_uart_ops;
821 port->regshift = 0;
822
823 port->fifosize = 32;
824 port->iotype = UPIO_MEM32;
825 port->flags = UPF_FIXED_PORT;
826 port->line = pdev->id;
827
828 /*
829 * IRQ number is not stored in this structure because we may have two of
830 * them per port (RX and TX). Instead, use the driver UART structure
831 * array so called ->irq[].
832 */
833 port->irq = 0;
834 port->irqflags = 0;
835 port->mapbase = reg->start;
836
837 port->membase = devm_ioremap_resource(&pdev->dev, reg);
838 if (IS_ERR(port->membase))
839 return -PTR_ERR(port->membase);
840
841 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
842 GFP_KERNEL);
843 if (!mvuart)
844 return -ENOMEM;
845
846 /* Get controller data depending on the compatible string */
847 mvuart->data = (struct mvebu_uart_driver_data *)match->data;
848 mvuart->port = port;
849
850 port->private_data = mvuart;
851 platform_set_drvdata(pdev, mvuart);
852
853 /* Get fixed clock frequency */
854 mvuart->clk = devm_clk_get(&pdev->dev, NULL);
855 if (IS_ERR(mvuart->clk)) {
856 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
857 return PTR_ERR(mvuart->clk);
858
859 if (IS_EXTENDED(port)) {
860 dev_err(&pdev->dev, "unable to get UART clock\n");
861 return PTR_ERR(mvuart->clk);
862 }
863 } else {
864 if (!clk_prepare_enable(mvuart->clk))
865 port->uartclk = clk_get_rate(mvuart->clk);
866 }
867
868 /* Manage interrupts */
869 if (platform_irq_count(pdev) == 1) {
870 /* Old bindings: no name on the single unamed UART0 IRQ */
871 irq = platform_get_irq(pdev, 0);
872 if (irq < 0) {
873 dev_err(&pdev->dev, "unable to get UART IRQ\n");
874 return irq;
875 }
876
877 mvuart->irq[UART_IRQ_SUM] = irq;
878 } else {
879 /*
880 * New bindings: named interrupts (RX, TX) for both UARTS,
881 * only make use of uart-rx and uart-tx interrupts, do not use
882 * uart-sum of UART0 port.
883 */
884 irq = platform_get_irq_byname(pdev, "uart-rx");
885 if (irq < 0) {
886 dev_err(&pdev->dev, "unable to get 'uart-rx' IRQ\n");
887 return irq;
888 }
889
890 mvuart->irq[UART_RX_IRQ] = irq;
891
892 irq = platform_get_irq_byname(pdev, "uart-tx");
893 if (irq < 0) {
894 dev_err(&pdev->dev, "unable to get 'uart-tx' IRQ\n");
895 return irq;
896 }
897
898 mvuart->irq[UART_TX_IRQ] = irq;
899 }
900
901 /* UART Soft Reset*/
902 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
903 udelay(1);
904 writel(0, port->membase + UART_CTRL(port));
905
906 ret = uart_add_one_port(&mvebu_uart_driver, port);
907 if (ret)
908 return ret;
909 return 0;
910 }
911
912 static struct mvebu_uart_driver_data uart_std_driver_data = {
913 .is_ext = false,
914 .regs.rbr = UART_STD_RBR,
915 .regs.tsh = UART_STD_TSH,
916 .regs.ctrl = UART_STD_CTRL1,
917 .regs.intr = UART_STD_CTRL2,
918 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
919 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
920 .flags.stat_tx_rdy = STAT_STD_TX_RDY,
921 .flags.stat_rx_rdy = STAT_STD_RX_RDY,
922 };
923
924 static struct mvebu_uart_driver_data uart_ext_driver_data = {
925 .is_ext = true,
926 .regs.rbr = UART_EXT_RBR,
927 .regs.tsh = UART_EXT_TSH,
928 .regs.ctrl = UART_EXT_CTRL1,
929 .regs.intr = UART_EXT_CTRL2,
930 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
931 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
932 .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
933 .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
934 };
935
936 /* Match table for of_platform binding */
937 static const struct of_device_id mvebu_uart_of_match[] = {
938 {
939 .compatible = "marvell,armada-3700-uart",
940 .data = (void *)&uart_std_driver_data,
941 },
942 {
943 .compatible = "marvell,armada-3700-uart-ext",
944 .data = (void *)&uart_ext_driver_data,
945 },
946 {}
947 };
948
949 static struct platform_driver mvebu_uart_platform_driver = {
950 .probe = mvebu_uart_probe,
951 .driver = {
952 .name = "mvebu-uart",
953 .of_match_table = of_match_ptr(mvebu_uart_of_match),
954 .suppress_bind_attrs = true,
955 #if defined(CONFIG_PM)
956 .pm = &mvebu_uart_pm_ops,
957 #endif /* CONFIG_PM */
958 },
959 };
960
961 static int __init mvebu_uart_init(void)
962 {
963 int ret;
964
965 ret = uart_register_driver(&mvebu_uart_driver);
966 if (ret)
967 return ret;
968
969 ret = platform_driver_register(&mvebu_uart_platform_driver);
970 if (ret)
971 uart_unregister_driver(&mvebu_uart_driver);
972
973 return ret;
974 }
975 arch_initcall(mvebu_uart_init);
Linux with added FPC-III support