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Linux 4.9.243
[linux/fpc-iii.git] / drivers / gpu / drm / exynos / exynos_drm_gsc.c
blob4c81c79b15ea172232d66fc3917fc4a306605c9f
1 /*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Authors:
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20
21 #include <drm/drmP.h>
22 #include <drm/exynos_drm.h>
23 #include "regs-gsc.h"
24 #include "exynos_drm_drv.h"
25 #include "exynos_drm_ipp.h"
26 #include "exynos_drm_gsc.h"
27
28 /*
29 * GSC stands for General SCaler and
30 * supports image scaler/rotator and input/output DMA operations.
31 * input DMA reads image data from the memory.
32 * output DMA writes image data to memory.
33 * GSC supports image rotation and image effect functions.
34 *
35 * M2M operation : supports crop/scale/rotation/csc so on.
36 * Memory ----> GSC H/W ----> Memory.
37 * Writeback operation : supports cloned screen with FIMD.
38 * FIMD ----> GSC H/W ----> Memory.
39 * Output operation : supports direct display using local path.
40 * Memory ----> GSC H/W ----> FIMD, Mixer.
41 */
42
43 /*
44 * TODO
45 * 1. check suspend/resume api if needed.
46 * 2. need to check use case platform_device_id.
47 * 3. check src/dst size with, height.
48 * 4. added check_prepare api for right register.
49 * 5. need to add supported list in prop_list.
50 * 6. check prescaler/scaler optimization.
51 */
52
53 #define GSC_MAX_DEVS 4
54 #define GSC_MAX_SRC 4
55 #define GSC_MAX_DST 16
56 #define GSC_RESET_TIMEOUT 50
57 #define GSC_BUF_STOP 1
58 #define GSC_BUF_START 2
59 #define GSC_REG_SZ 16
60 #define GSC_WIDTH_ITU_709 1280
61 #define GSC_SC_UP_MAX_RATIO 65536
62 #define GSC_SC_DOWN_RATIO_7_8 74898
63 #define GSC_SC_DOWN_RATIO_6_8 87381
64 #define GSC_SC_DOWN_RATIO_5_8 104857
65 #define GSC_SC_DOWN_RATIO_4_8 131072
66 #define GSC_SC_DOWN_RATIO_3_8 174762
67 #define GSC_SC_DOWN_RATIO_2_8 262144
68 #define GSC_REFRESH_MIN 12
69 #define GSC_REFRESH_MAX 60
70 #define GSC_CROP_MAX 8192
71 #define GSC_CROP_MIN 32
72 #define GSC_SCALE_MAX 4224
73 #define GSC_SCALE_MIN 32
74 #define GSC_COEF_RATIO 7
75 #define GSC_COEF_PHASE 9
76 #define GSC_COEF_ATTR 16
77 #define GSC_COEF_H_8T 8
78 #define GSC_COEF_V_4T 4
79 #define GSC_COEF_DEPTH 3
80
81 #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev))
82 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
83 struct gsc_context, ippdrv);
84 #define gsc_read(offset) readl(ctx->regs + (offset))
85 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
86
87 /*
88 * A structure of scaler.
89 *
90 * @range: narrow, wide.
91 * @pre_shfactor: pre sclaer shift factor.
92 * @pre_hratio: horizontal ratio of the prescaler.
93 * @pre_vratio: vertical ratio of the prescaler.
94 * @main_hratio: the main scaler's horizontal ratio.
95 * @main_vratio: the main scaler's vertical ratio.
96 */
97 struct gsc_scaler {
98 bool range;
99 u32 pre_shfactor;
100 u32 pre_hratio;
101 u32 pre_vratio;
102 unsigned long main_hratio;
103 unsigned long main_vratio;
104 };
105
106 /*
107 * A structure of scaler capability.
108 *
109 * find user manual 49.2 features.
110 * @tile_w: tile mode or rotation width.
111 * @tile_h: tile mode or rotation height.
112 * @w: other cases width.
113 * @h: other cases height.
114 */
115 struct gsc_capability {
116 /* tile or rotation */
117 u32 tile_w;
118 u32 tile_h;
119 /* other cases */
120 u32 w;
121 u32 h;
122 };
123
124 /*
125 * A structure of gsc context.
126 *
127 * @ippdrv: prepare initialization using ippdrv.
128 * @regs_res: register resources.
129 * @regs: memory mapped io registers.
130 * @sysreg: handle to SYSREG block regmap.
131 * @lock: locking of operations.
132 * @gsc_clk: gsc gate clock.
133 * @sc: scaler infomations.
134 * @id: gsc id.
135 * @irq: irq number.
136 * @rotation: supports rotation of src.
137 * @suspended: qos operations.
138 */
139 struct gsc_context {
140 struct exynos_drm_ippdrv ippdrv;
141 struct resource *regs_res;
142 void __iomem *regs;
143 struct regmap *sysreg;
144 struct mutex lock;
145 struct clk *gsc_clk;
146 struct gsc_scaler sc;
147 int id;
148 int irq;
149 bool rotation;
150 bool suspended;
151 };
152
153 /* 8-tap Filter Coefficient */
154 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
155 { /* Ratio <= 65536 (~8:8) */
156 { 0, 0, 0, 128, 0, 0, 0, 0 },
157 { -1, 2, -6, 127, 7, -2, 1, 0 },
158 { -1, 4, -12, 125, 16, -5, 1, 0 },
159 { -1, 5, -15, 120, 25, -8, 2, 0 },
160 { -1, 6, -18, 114, 35, -10, 3, -1 },
161 { -1, 6, -20, 107, 46, -13, 4, -1 },
162 { -2, 7, -21, 99, 57, -16, 5, -1 },
163 { -1, 6, -20, 89, 68, -18, 5, -1 },
164 { -1, 6, -20, 79, 79, -20, 6, -1 },
165 { -1, 5, -18, 68, 89, -20, 6, -1 },
166 { -1, 5, -16, 57, 99, -21, 7, -2 },
167 { -1, 4, -13, 46, 107, -20, 6, -1 },
168 { -1, 3, -10, 35, 114, -18, 6, -1 },
169 { 0, 2, -8, 25, 120, -15, 5, -1 },
170 { 0, 1, -5, 16, 125, -12, 4, -1 },
171 { 0, 1, -2, 7, 127, -6, 2, -1 }
172 }, { /* 65536 < Ratio <= 74898 (~8:7) */
173 { 3, -8, 14, 111, 13, -8, 3, 0 },
174 { 2, -6, 7, 112, 21, -10, 3, -1 },
175 { 2, -4, 1, 110, 28, -12, 4, -1 },
176 { 1, -2, -3, 106, 36, -13, 4, -1 },
177 { 1, -1, -7, 103, 44, -15, 4, -1 },
178 { 1, 1, -11, 97, 53, -16, 4, -1 },
179 { 0, 2, -13, 91, 61, -16, 4, -1 },
180 { 0, 3, -15, 85, 69, -17, 4, -1 },
181 { 0, 3, -16, 77, 77, -16, 3, 0 },
182 { -1, 4, -17, 69, 85, -15, 3, 0 },
183 { -1, 4, -16, 61, 91, -13, 2, 0 },
184 { -1, 4, -16, 53, 97, -11, 1, 1 },
185 { -1, 4, -15, 44, 103, -7, -1, 1 },
186 { -1, 4, -13, 36, 106, -3, -2, 1 },
187 { -1, 4, -12, 28, 110, 1, -4, 2 },
188 { -1, 3, -10, 21, 112, 7, -6, 2 }
189 }, { /* 74898 < Ratio <= 87381 (~8:6) */
190 { 2, -11, 25, 96, 25, -11, 2, 0 },
191 { 2, -10, 19, 96, 31, -12, 2, 0 },
192 { 2, -9, 14, 94, 37, -12, 2, 0 },
193 { 2, -8, 10, 92, 43, -12, 1, 0 },
194 { 2, -7, 5, 90, 49, -12, 1, 0 },
195 { 2, -5, 1, 86, 55, -12, 0, 1 },
196 { 2, -4, -2, 82, 61, -11, -1, 1 },
197 { 1, -3, -5, 77, 67, -9, -1, 1 },
198 { 1, -2, -7, 72, 72, -7, -2, 1 },
199 { 1, -1, -9, 67, 77, -5, -3, 1 },
200 { 1, -1, -11, 61, 82, -2, -4, 2 },
201 { 1, 0, -12, 55, 86, 1, -5, 2 },
202 { 0, 1, -12, 49, 90, 5, -7, 2 },
203 { 0, 1, -12, 43, 92, 10, -8, 2 },
204 { 0, 2, -12, 37, 94, 14, -9, 2 },
205 { 0, 2, -12, 31, 96, 19, -10, 2 }
206 }, { /* 87381 < Ratio <= 104857 (~8:5) */
207 { -1, -8, 33, 80, 33, -8, -1, 0 },
208 { -1, -8, 28, 80, 37, -7, -2, 1 },
209 { 0, -8, 24, 79, 41, -7, -2, 1 },
210 { 0, -8, 20, 78, 46, -6, -3, 1 },
211 { 0, -8, 16, 76, 50, -4, -3, 1 },
212 { 0, -7, 13, 74, 54, -3, -4, 1 },
213 { 1, -7, 10, 71, 58, -1, -5, 1 },
214 { 1, -6, 6, 68, 62, 1, -5, 1 },
215 { 1, -6, 4, 65, 65, 4, -6, 1 },
216 { 1, -5, 1, 62, 68, 6, -6, 1 },
217 { 1, -5, -1, 58, 71, 10, -7, 1 },
218 { 1, -4, -3, 54, 74, 13, -7, 0 },
219 { 1, -3, -4, 50, 76, 16, -8, 0 },
220 { 1, -3, -6, 46, 78, 20, -8, 0 },
221 { 1, -2, -7, 41, 79, 24, -8, 0 },
222 { 1, -2, -7, 37, 80, 28, -8, -1 }
223 }, { /* 104857 < Ratio <= 131072 (~8:4) */
224 { -3, 0, 35, 64, 35, 0, -3, 0 },
225 { -3, -1, 32, 64, 38, 1, -3, 0 },
226 { -2, -2, 29, 63, 41, 2, -3, 0 },
227 { -2, -3, 27, 63, 43, 4, -4, 0 },
228 { -2, -3, 24, 61, 46, 6, -4, 0 },
229 { -2, -3, 21, 60, 49, 7, -4, 0 },
230 { -1, -4, 19, 59, 51, 9, -4, -1 },
231 { -1, -4, 16, 57, 53, 12, -4, -1 },
232 { -1, -4, 14, 55, 55, 14, -4, -1 },
233 { -1, -4, 12, 53, 57, 16, -4, -1 },
234 { -1, -4, 9, 51, 59, 19, -4, -1 },
235 { 0, -4, 7, 49, 60, 21, -3, -2 },
236 { 0, -4, 6, 46, 61, 24, -3, -2 },
237 { 0, -4, 4, 43, 63, 27, -3, -2 },
238 { 0, -3, 2, 41, 63, 29, -2, -2 },
239 { 0, -3, 1, 38, 64, 32, -1, -3 }
240 }, { /* 131072 < Ratio <= 174762 (~8:3) */
241 { -1, 8, 33, 48, 33, 8, -1, 0 },
242 { -1, 7, 31, 49, 35, 9, -1, -1 },
243 { -1, 6, 30, 49, 36, 10, -1, -1 },
244 { -1, 5, 28, 48, 38, 12, -1, -1 },
245 { -1, 4, 26, 48, 39, 13, 0, -1 },
246 { -1, 3, 24, 47, 41, 15, 0, -1 },
247 { -1, 2, 23, 47, 42, 16, 0, -1 },
248 { -1, 2, 21, 45, 43, 18, 1, -1 },
249 { -1, 1, 19, 45, 45, 19, 1, -1 },
250 { -1, 1, 18, 43, 45, 21, 2, -1 },
251 { -1, 0, 16, 42, 47, 23, 2, -1 },
252 { -1, 0, 15, 41, 47, 24, 3, -1 },
253 { -1, 0, 13, 39, 48, 26, 4, -1 },
254 { -1, -1, 12, 38, 48, 28, 5, -1 },
255 { -1, -1, 10, 36, 49, 30, 6, -1 },
256 { -1, -1, 9, 35, 49, 31, 7, -1 }
257 }, { /* 174762 < Ratio <= 262144 (~8:2) */
258 { 2, 13, 30, 38, 30, 13, 2, 0 },
259 { 2, 12, 29, 38, 30, 14, 3, 0 },
260 { 2, 11, 28, 38, 31, 15, 3, 0 },
261 { 2, 10, 26, 38, 32, 16, 4, 0 },
262 { 1, 10, 26, 37, 33, 17, 4, 0 },
263 { 1, 9, 24, 37, 34, 18, 5, 0 },
264 { 1, 8, 24, 37, 34, 19, 5, 0 },
265 { 1, 7, 22, 36, 35, 20, 6, 1 },
266 { 1, 6, 21, 36, 36, 21, 6, 1 },
267 { 1, 6, 20, 35, 36, 22, 7, 1 },
268 { 0, 5, 19, 34, 37, 24, 8, 1 },
269 { 0, 5, 18, 34, 37, 24, 9, 1 },
270 { 0, 4, 17, 33, 37, 26, 10, 1 },
271 { 0, 4, 16, 32, 38, 26, 10, 2 },
272 { 0, 3, 15, 31, 38, 28, 11, 2 },
273 { 0, 3, 14, 30, 38, 29, 12, 2 }
274 }
275 };
276
277 /* 4-tap Filter Coefficient */
278 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
279 { /* Ratio <= 65536 (~8:8) */
280 { 0, 128, 0, 0 },
281 { -4, 127, 5, 0 },
282 { -6, 124, 11, -1 },
283 { -8, 118, 19, -1 },
284 { -8, 111, 27, -2 },
285 { -8, 102, 37, -3 },
286 { -8, 92, 48, -4 },
287 { -7, 81, 59, -5 },
288 { -6, 70, 70, -6 },
289 { -5, 59, 81, -7 },
290 { -4, 48, 92, -8 },
291 { -3, 37, 102, -8 },
292 { -2, 27, 111, -8 },
293 { -1, 19, 118, -8 },
294 { -1, 11, 124, -6 },
295 { 0, 5, 127, -4 }
296 }, { /* 65536 < Ratio <= 74898 (~8:7) */
297 { 8, 112, 8, 0 },
298 { 4, 111, 14, -1 },
299 { 1, 109, 20, -2 },
300 { -2, 105, 27, -2 },
301 { -3, 100, 34, -3 },
302 { -5, 93, 43, -3 },
303 { -5, 86, 51, -4 },
304 { -5, 77, 60, -4 },
305 { -5, 69, 69, -5 },
306 { -4, 60, 77, -5 },
307 { -4, 51, 86, -5 },
308 { -3, 43, 93, -5 },
309 { -3, 34, 100, -3 },
310 { -2, 27, 105, -2 },
311 { -2, 20, 109, 1 },
312 { -1, 14, 111, 4 }
313 }, { /* 74898 < Ratio <= 87381 (~8:6) */
314 { 16, 96, 16, 0 },
315 { 12, 97, 21, -2 },
316 { 8, 96, 26, -2 },
317 { 5, 93, 32, -2 },
318 { 2, 89, 39, -2 },
319 { 0, 84, 46, -2 },
320 { -1, 79, 53, -3 },
321 { -2, 73, 59, -2 },
322 { -2, 66, 66, -2 },
323 { -2, 59, 73, -2 },
324 { -3, 53, 79, -1 },
325 { -2, 46, 84, 0 },
326 { -2, 39, 89, 2 },
327 { -2, 32, 93, 5 },
328 { -2, 26, 96, 8 },
329 { -2, 21, 97, 12 }
330 }, { /* 87381 < Ratio <= 104857 (~8:5) */
331 { 22, 84, 22, 0 },
332 { 18, 85, 26, -1 },
333 { 14, 84, 31, -1 },
334 { 11, 82, 36, -1 },
335 { 8, 79, 42, -1 },
336 { 6, 76, 47, -1 },
337 { 4, 72, 52, 0 },
338 { 2, 68, 58, 0 },
339 { 1, 63, 63, 1 },
340 { 0, 58, 68, 2 },
341 { 0, 52, 72, 4 },
342 { -1, 47, 76, 6 },
343 { -1, 42, 79, 8 },
344 { -1, 36, 82, 11 },
345 { -1, 31, 84, 14 },
346 { -1, 26, 85, 18 }
347 }, { /* 104857 < Ratio <= 131072 (~8:4) */
348 { 26, 76, 26, 0 },
349 { 22, 76, 30, 0 },
350 { 19, 75, 34, 0 },
351 { 16, 73, 38, 1 },
352 { 13, 71, 43, 1 },
353 { 10, 69, 47, 2 },
354 { 8, 66, 51, 3 },
355 { 6, 63, 55, 4 },
356 { 5, 59, 59, 5 },
357 { 4, 55, 63, 6 },
358 { 3, 51, 66, 8 },
359 { 2, 47, 69, 10 },
360 { 1, 43, 71, 13 },
361 { 1, 38, 73, 16 },
362 { 0, 34, 75, 19 },
363 { 0, 30, 76, 22 }
364 }, { /* 131072 < Ratio <= 174762 (~8:3) */
365 { 29, 70, 29, 0 },
366 { 26, 68, 32, 2 },
367 { 23, 67, 36, 2 },
368 { 20, 66, 39, 3 },
369 { 17, 65, 43, 3 },
370 { 15, 63, 46, 4 },
371 { 12, 61, 50, 5 },
372 { 10, 58, 53, 7 },
373 { 8, 56, 56, 8 },
374 { 7, 53, 58, 10 },
375 { 5, 50, 61, 12 },
376 { 4, 46, 63, 15 },
377 { 3, 43, 65, 17 },
378 { 3, 39, 66, 20 },
379 { 2, 36, 67, 23 },
380 { 2, 32, 68, 26 }
381 }, { /* 174762 < Ratio <= 262144 (~8:2) */
382 { 32, 64, 32, 0 },
383 { 28, 63, 34, 3 },
384 { 25, 62, 37, 4 },
385 { 22, 62, 40, 4 },
386 { 19, 61, 43, 5 },
387 { 17, 59, 46, 6 },
388 { 15, 58, 48, 7 },
389 { 13, 55, 51, 9 },
390 { 11, 53, 53, 11 },
391 { 9, 51, 55, 13 },
392 { 7, 48, 58, 15 },
393 { 6, 46, 59, 17 },
394 { 5, 43, 61, 19 },
395 { 4, 40, 62, 22 },
396 { 4, 37, 62, 25 },
397 { 3, 34, 63, 28 }
398 }
399 };
400
401 static int gsc_sw_reset(struct gsc_context *ctx)
402 {
403 u32 cfg;
404 int count = GSC_RESET_TIMEOUT;
405
406 /* s/w reset */
407 cfg = (GSC_SW_RESET_SRESET);
408 gsc_write(cfg, GSC_SW_RESET);
409
410 /* wait s/w reset complete */
411 while (count--) {
412 cfg = gsc_read(GSC_SW_RESET);
413 if (!cfg)
414 break;
415 usleep_range(1000, 2000);
416 }
417
418 if (cfg) {
419 DRM_ERROR("failed to reset gsc h/w.\n");
420 return -EBUSY;
421 }
422
423 /* reset sequence */
424 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
425 cfg |= (GSC_IN_BASE_ADDR_MASK |
426 GSC_IN_BASE_ADDR_PINGPONG(0));
427 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
428 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
429 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
430
431 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
432 cfg |= (GSC_OUT_BASE_ADDR_MASK |
433 GSC_OUT_BASE_ADDR_PINGPONG(0));
434 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
435 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
436 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
437
438 return 0;
439 }
440
441 static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable)
442 {
443 unsigned int gscblk_cfg;
444
445 if (!ctx->sysreg)
446 return;
447
448 regmap_read(ctx->sysreg, SYSREG_GSCBLK_CFG1, &gscblk_cfg);
449
450 if (enable)
451 gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) |
452 GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) |
453 GSC_BLK_SW_RESET_WB_DEST(ctx->id);
454 else
455 gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id);
456
457 regmap_write(ctx->sysreg, SYSREG_GSCBLK_CFG1, gscblk_cfg);
458 }
459
460 static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
461 bool overflow, bool done)
462 {
463 u32 cfg;
464
465 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
466 enable, overflow, done);
467
468 cfg = gsc_read(GSC_IRQ);
469 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
470
471 if (enable)
472 cfg |= GSC_IRQ_ENABLE;
473 else
474 cfg &= ~GSC_IRQ_ENABLE;
475
476 if (overflow)
477 cfg &= ~GSC_IRQ_OR_MASK;
478 else
479 cfg |= GSC_IRQ_OR_MASK;
480
481 if (done)
482 cfg &= ~GSC_IRQ_FRMDONE_MASK;
483 else
484 cfg |= GSC_IRQ_FRMDONE_MASK;
485
486 gsc_write(cfg, GSC_IRQ);
487 }
488
489
490 static int gsc_src_set_fmt(struct device *dev, u32 fmt)
491 {
492 struct gsc_context *ctx = get_gsc_context(dev);
493 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
494 u32 cfg;
495
496 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
497
498 cfg = gsc_read(GSC_IN_CON);
499 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
500 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
501 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
502 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
503
504 switch (fmt) {
505 case DRM_FORMAT_RGB565:
506 cfg |= GSC_IN_RGB565;
507 break;
508 case DRM_FORMAT_XRGB8888:
509 cfg |= GSC_IN_XRGB8888;
510 break;
511 case DRM_FORMAT_BGRX8888:
512 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
513 break;
514 case DRM_FORMAT_YUYV:
515 cfg |= (GSC_IN_YUV422_1P |
516 GSC_IN_YUV422_1P_ORDER_LSB_Y |
517 GSC_IN_CHROMA_ORDER_CBCR);
518 break;
519 case DRM_FORMAT_YVYU:
520 cfg |= (GSC_IN_YUV422_1P |
521 GSC_IN_YUV422_1P_ORDER_LSB_Y |
522 GSC_IN_CHROMA_ORDER_CRCB);
523 break;
524 case DRM_FORMAT_UYVY:
525 cfg |= (GSC_IN_YUV422_1P |
526 GSC_IN_YUV422_1P_OEDER_LSB_C |
527 GSC_IN_CHROMA_ORDER_CBCR);
528 break;
529 case DRM_FORMAT_VYUY:
530 cfg |= (GSC_IN_YUV422_1P |
531 GSC_IN_YUV422_1P_OEDER_LSB_C |
532 GSC_IN_CHROMA_ORDER_CRCB);
533 break;
534 case DRM_FORMAT_NV21:
535 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
536 break;
537 case DRM_FORMAT_NV61:
538 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
539 break;
540 case DRM_FORMAT_YUV422:
541 cfg |= GSC_IN_YUV422_3P;
542 break;
543 case DRM_FORMAT_YUV420:
544 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
545 break;
546 case DRM_FORMAT_YVU420:
547 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
548 break;
549 case DRM_FORMAT_NV12:
550 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
551 break;
552 case DRM_FORMAT_NV16:
553 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
554 break;
555 default:
556 dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt);
557 return -EINVAL;
558 }
559
560 gsc_write(cfg, GSC_IN_CON);
561
562 return 0;
563 }
564
565 static int gsc_src_set_transf(struct device *dev,
566 enum drm_exynos_degree degree,
567 enum drm_exynos_flip flip, bool *swap)
568 {
569 struct gsc_context *ctx = get_gsc_context(dev);
570 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
571 u32 cfg;
572
573 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
574
575 cfg = gsc_read(GSC_IN_CON);
576 cfg &= ~GSC_IN_ROT_MASK;
577
578 switch (degree) {
579 case EXYNOS_DRM_DEGREE_0:
580 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
581 cfg |= GSC_IN_ROT_XFLIP;
582 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
583 cfg |= GSC_IN_ROT_YFLIP;
584 break;
585 case EXYNOS_DRM_DEGREE_90:
586 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
587 cfg |= GSC_IN_ROT_90_XFLIP;
588 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
589 cfg |= GSC_IN_ROT_90_YFLIP;
590 else
591 cfg |= GSC_IN_ROT_90;
592 break;
593 case EXYNOS_DRM_DEGREE_180:
594 cfg |= GSC_IN_ROT_180;
595 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
596 cfg &= ~GSC_IN_ROT_XFLIP;
597 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
598 cfg &= ~GSC_IN_ROT_YFLIP;
599 break;
600 case EXYNOS_DRM_DEGREE_270:
601 cfg |= GSC_IN_ROT_270;
602 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
603 cfg &= ~GSC_IN_ROT_XFLIP;
604 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
605 cfg &= ~GSC_IN_ROT_YFLIP;
606 break;
607 default:
608 dev_err(ippdrv->dev, "invalid degree value %d.\n", degree);
609 return -EINVAL;
610 }
611
612 gsc_write(cfg, GSC_IN_CON);
613
614 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
615 *swap = ctx->rotation;
616
617 return 0;
618 }
619
620 static int gsc_src_set_size(struct device *dev, int swap,
621 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
622 {
623 struct gsc_context *ctx = get_gsc_context(dev);
624 struct drm_exynos_pos img_pos = *pos;
625 struct gsc_scaler *sc = &ctx->sc;
626 u32 cfg;
627
628 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
629 swap, pos->x, pos->y, pos->w, pos->h);
630
631 if (swap) {
632 img_pos.w = pos->h;
633 img_pos.h = pos->w;
634 }
635
636 /* pixel offset */
637 cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) |
638 GSC_SRCIMG_OFFSET_Y(img_pos.y));
639 gsc_write(cfg, GSC_SRCIMG_OFFSET);
640
641 /* cropped size */
642 cfg = (GSC_CROPPED_WIDTH(img_pos.w) |
643 GSC_CROPPED_HEIGHT(img_pos.h));
644 gsc_write(cfg, GSC_CROPPED_SIZE);
645
646 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
647
648 /* original size */
649 cfg = gsc_read(GSC_SRCIMG_SIZE);
650 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
651 GSC_SRCIMG_WIDTH_MASK);
652
653 cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) |
654 GSC_SRCIMG_HEIGHT(sz->vsize));
655
656 gsc_write(cfg, GSC_SRCIMG_SIZE);
657
658 cfg = gsc_read(GSC_IN_CON);
659 cfg &= ~GSC_IN_RGB_TYPE_MASK;
660
661 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
662
663 if (pos->w >= GSC_WIDTH_ITU_709)
664 if (sc->range)
665 cfg |= GSC_IN_RGB_HD_WIDE;
666 else
667 cfg |= GSC_IN_RGB_HD_NARROW;
668 else
669 if (sc->range)
670 cfg |= GSC_IN_RGB_SD_WIDE;
671 else
672 cfg |= GSC_IN_RGB_SD_NARROW;
673
674 gsc_write(cfg, GSC_IN_CON);
675
676 return 0;
677 }
678
679 static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
680 enum drm_exynos_ipp_buf_type buf_type)
681 {
682 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
683 bool masked;
684 u32 cfg;
685 u32 mask = 0x00000001 << buf_id;
686
687 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
688
689 /* mask register set */
690 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
691
692 switch (buf_type) {
693 case IPP_BUF_ENQUEUE:
694 masked = false;
695 break;
696 case IPP_BUF_DEQUEUE:
697 masked = true;
698 break;
699 default:
700 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
701 return -EINVAL;
702 }
703
704 /* sequence id */
705 cfg &= ~mask;
706 cfg |= masked << buf_id;
707 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
708 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
709 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
710
711 return 0;
712 }
713
714 static int gsc_src_set_addr(struct device *dev,
715 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
716 enum drm_exynos_ipp_buf_type buf_type)
717 {
718 struct gsc_context *ctx = get_gsc_context(dev);
719 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
720 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
721 struct drm_exynos_ipp_property *property;
722
723 if (!c_node) {
724 DRM_ERROR("failed to get c_node.\n");
725 return -EFAULT;
726 }
727
728 property = &c_node->property;
729
730 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
731 property->prop_id, buf_id, buf_type);
732
733 if (buf_id > GSC_MAX_SRC) {
734 dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id);
735 return -EINVAL;
736 }
737
738 /* address register set */
739 switch (buf_type) {
740 case IPP_BUF_ENQUEUE:
741 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
742 GSC_IN_BASE_ADDR_Y(buf_id));
743 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
744 GSC_IN_BASE_ADDR_CB(buf_id));
745 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
746 GSC_IN_BASE_ADDR_CR(buf_id));
747 break;
748 case IPP_BUF_DEQUEUE:
749 gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
750 gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
751 gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
752 break;
753 default:
754 /* bypass */
755 break;
756 }
757
758 return gsc_src_set_buf_seq(ctx, buf_id, buf_type);
759 }
760
761 static struct exynos_drm_ipp_ops gsc_src_ops = {
762 .set_fmt = gsc_src_set_fmt,
763 .set_transf = gsc_src_set_transf,
764 .set_size = gsc_src_set_size,
765 .set_addr = gsc_src_set_addr,
766 };
767
768 static int gsc_dst_set_fmt(struct device *dev, u32 fmt)
769 {
770 struct gsc_context *ctx = get_gsc_context(dev);
771 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
772 u32 cfg;
773
774 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
775
776 cfg = gsc_read(GSC_OUT_CON);
777 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
778 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
779 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
780 GSC_OUT_GLOBAL_ALPHA_MASK);
781
782 switch (fmt) {
783 case DRM_FORMAT_RGB565:
784 cfg |= GSC_OUT_RGB565;
785 break;
786 case DRM_FORMAT_XRGB8888:
787 cfg |= GSC_OUT_XRGB8888;
788 break;
789 case DRM_FORMAT_BGRX8888:
790 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
791 break;
792 case DRM_FORMAT_YUYV:
793 cfg |= (GSC_OUT_YUV422_1P |
794 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
795 GSC_OUT_CHROMA_ORDER_CBCR);
796 break;
797 case DRM_FORMAT_YVYU:
798 cfg |= (GSC_OUT_YUV422_1P |
799 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
800 GSC_OUT_CHROMA_ORDER_CRCB);
801 break;
802 case DRM_FORMAT_UYVY:
803 cfg |= (GSC_OUT_YUV422_1P |
804 GSC_OUT_YUV422_1P_OEDER_LSB_C |
805 GSC_OUT_CHROMA_ORDER_CBCR);
806 break;
807 case DRM_FORMAT_VYUY:
808 cfg |= (GSC_OUT_YUV422_1P |
809 GSC_OUT_YUV422_1P_OEDER_LSB_C |
810 GSC_OUT_CHROMA_ORDER_CRCB);
811 break;
812 case DRM_FORMAT_NV21:
813 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
814 break;
815 case DRM_FORMAT_NV61:
816 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
817 break;
818 case DRM_FORMAT_YUV422:
819 cfg |= GSC_OUT_YUV422_3P;
820 break;
821 case DRM_FORMAT_YUV420:
822 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
823 break;
824 case DRM_FORMAT_YVU420:
825 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
826 break;
827 case DRM_FORMAT_NV12:
828 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
829 break;
830 case DRM_FORMAT_NV16:
831 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
832 break;
833 default:
834 dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt);
835 return -EINVAL;
836 }
837
838 gsc_write(cfg, GSC_OUT_CON);
839
840 return 0;
841 }
842
843 static int gsc_dst_set_transf(struct device *dev,
844 enum drm_exynos_degree degree,
845 enum drm_exynos_flip flip, bool *swap)
846 {
847 struct gsc_context *ctx = get_gsc_context(dev);
848 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
849 u32 cfg;
850
851 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
852
853 cfg = gsc_read(GSC_IN_CON);
854 cfg &= ~GSC_IN_ROT_MASK;
855
856 switch (degree) {
857 case EXYNOS_DRM_DEGREE_0:
858 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
859 cfg |= GSC_IN_ROT_XFLIP;
860 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
861 cfg |= GSC_IN_ROT_YFLIP;
862 break;
863 case EXYNOS_DRM_DEGREE_90:
864 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
865 cfg |= GSC_IN_ROT_90_XFLIP;
866 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
867 cfg |= GSC_IN_ROT_90_YFLIP;
868 else
869 cfg |= GSC_IN_ROT_90;
870 break;
871 case EXYNOS_DRM_DEGREE_180:
872 cfg |= GSC_IN_ROT_180;
873 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
874 cfg &= ~GSC_IN_ROT_XFLIP;
875 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
876 cfg &= ~GSC_IN_ROT_YFLIP;
877 break;
878 case EXYNOS_DRM_DEGREE_270:
879 cfg |= GSC_IN_ROT_270;
880 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
881 cfg &= ~GSC_IN_ROT_XFLIP;
882 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
883 cfg &= ~GSC_IN_ROT_YFLIP;
884 break;
885 default:
886 dev_err(ippdrv->dev, "invalid degree value %d.\n", degree);
887 return -EINVAL;
888 }
889
890 gsc_write(cfg, GSC_IN_CON);
891
892 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
893 *swap = ctx->rotation;
894
895 return 0;
896 }
897
898 static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio)
899 {
900 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst);
901
902 if (src >= dst * 8) {
903 DRM_ERROR("failed to make ratio and shift.\n");
904 return -EINVAL;
905 } else if (src >= dst * 4)
906 *ratio = 4;
907 else if (src >= dst * 2)
908 *ratio = 2;
909 else
910 *ratio = 1;
911
912 return 0;
913 }
914
915 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
916 {
917 if (hratio == 4 && vratio == 4)
918 *shfactor = 4;
919 else if ((hratio == 4 && vratio == 2) ||
920 (hratio == 2 && vratio == 4))
921 *shfactor = 3;
922 else if ((hratio == 4 && vratio == 1) ||
923 (hratio == 1 && vratio == 4) ||
924 (hratio == 2 && vratio == 2))
925 *shfactor = 2;
926 else if (hratio == 1 && vratio == 1)
927 *shfactor = 0;
928 else
929 *shfactor = 1;
930 }
931
932 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
933 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
934 {
935 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
936 u32 cfg;
937 u32 src_w, src_h, dst_w, dst_h;
938 int ret = 0;
939
940 src_w = src->w;
941 src_h = src->h;
942
943 if (ctx->rotation) {
944 dst_w = dst->h;
945 dst_h = dst->w;
946 } else {
947 dst_w = dst->w;
948 dst_h = dst->h;
949 }
950
951 ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio);
952 if (ret) {
953 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
954 return ret;
955 }
956
957 ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio);
958 if (ret) {
959 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
960 return ret;
961 }
962
963 DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n",
964 sc->pre_hratio, sc->pre_vratio);
965
966 sc->main_hratio = (src_w << 16) / dst_w;
967 sc->main_vratio = (src_h << 16) / dst_h;
968
969 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
970 sc->main_hratio, sc->main_vratio);
971
972 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
973 &sc->pre_shfactor);
974
975 DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor);
976
977 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
978 GSC_PRESC_H_RATIO(sc->pre_hratio) |
979 GSC_PRESC_V_RATIO(sc->pre_vratio));
980 gsc_write(cfg, GSC_PRE_SCALE_RATIO);
981
982 return ret;
983 }
984
985 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
986 {
987 int i, j, k, sc_ratio;
988
989 if (main_hratio <= GSC_SC_UP_MAX_RATIO)
990 sc_ratio = 0;
991 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
992 sc_ratio = 1;
993 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
994 sc_ratio = 2;
995 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
996 sc_ratio = 3;
997 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
998 sc_ratio = 4;
999 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
1000 sc_ratio = 5;
1001 else
1002 sc_ratio = 6;
1003
1004 for (i = 0; i < GSC_COEF_PHASE; i++)
1005 for (j = 0; j < GSC_COEF_H_8T; j++)
1006 for (k = 0; k < GSC_COEF_DEPTH; k++)
1007 gsc_write(h_coef_8t[sc_ratio][i][j],
1008 GSC_HCOEF(i, j, k));
1009 }
1010
1011 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
1012 {
1013 int i, j, k, sc_ratio;
1014
1015 if (main_vratio <= GSC_SC_UP_MAX_RATIO)
1016 sc_ratio = 0;
1017 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
1018 sc_ratio = 1;
1019 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
1020 sc_ratio = 2;
1021 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
1022 sc_ratio = 3;
1023 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
1024 sc_ratio = 4;
1025 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
1026 sc_ratio = 5;
1027 else
1028 sc_ratio = 6;
1029
1030 for (i = 0; i < GSC_COEF_PHASE; i++)
1031 for (j = 0; j < GSC_COEF_V_4T; j++)
1032 for (k = 0; k < GSC_COEF_DEPTH; k++)
1033 gsc_write(v_coef_4t[sc_ratio][i][j],
1034 GSC_VCOEF(i, j, k));
1035 }
1036
1037 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
1038 {
1039 u32 cfg;
1040
1041 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
1042 sc->main_hratio, sc->main_vratio);
1043
1044 gsc_set_h_coef(ctx, sc->main_hratio);
1045 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
1046 gsc_write(cfg, GSC_MAIN_H_RATIO);
1047
1048 gsc_set_v_coef(ctx, sc->main_vratio);
1049 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
1050 gsc_write(cfg, GSC_MAIN_V_RATIO);
1051 }
1052
1053 static int gsc_dst_set_size(struct device *dev, int swap,
1054 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1055 {
1056 struct gsc_context *ctx = get_gsc_context(dev);
1057 struct drm_exynos_pos img_pos = *pos;
1058 struct gsc_scaler *sc = &ctx->sc;
1059 u32 cfg;
1060
1061 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
1062 swap, pos->x, pos->y, pos->w, pos->h);
1063
1064 if (swap) {
1065 img_pos.w = pos->h;
1066 img_pos.h = pos->w;
1067 }
1068
1069 /* pixel offset */
1070 cfg = (GSC_DSTIMG_OFFSET_X(pos->x) |
1071 GSC_DSTIMG_OFFSET_Y(pos->y));
1072 gsc_write(cfg, GSC_DSTIMG_OFFSET);
1073
1074 /* scaled size */
1075 cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h));
1076 gsc_write(cfg, GSC_SCALED_SIZE);
1077
1078 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
1079
1080 /* original size */
1081 cfg = gsc_read(GSC_DSTIMG_SIZE);
1082 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK |
1083 GSC_DSTIMG_WIDTH_MASK);
1084 cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) |
1085 GSC_DSTIMG_HEIGHT(sz->vsize));
1086 gsc_write(cfg, GSC_DSTIMG_SIZE);
1087
1088 cfg = gsc_read(GSC_OUT_CON);
1089 cfg &= ~GSC_OUT_RGB_TYPE_MASK;
1090
1091 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
1092
1093 if (pos->w >= GSC_WIDTH_ITU_709)
1094 if (sc->range)
1095 cfg |= GSC_OUT_RGB_HD_WIDE;
1096 else
1097 cfg |= GSC_OUT_RGB_HD_NARROW;
1098 else
1099 if (sc->range)
1100 cfg |= GSC_OUT_RGB_SD_WIDE;
1101 else
1102 cfg |= GSC_OUT_RGB_SD_NARROW;
1103
1104 gsc_write(cfg, GSC_OUT_CON);
1105
1106 return 0;
1107 }
1108
1109 static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
1110 {
1111 u32 cfg, i, buf_num = GSC_REG_SZ;
1112 u32 mask = 0x00000001;
1113
1114 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1115
1116 for (i = 0; i < GSC_REG_SZ; i++)
1117 if (cfg & (mask << i))
1118 buf_num--;
1119
1120 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1121
1122 return buf_num;
1123 }
1124
1125 static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
1126 enum drm_exynos_ipp_buf_type buf_type)
1127 {
1128 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1129 bool masked;
1130 u32 cfg;
1131 u32 mask = 0x00000001 << buf_id;
1132 int ret = 0;
1133
1134 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1135
1136 mutex_lock(&ctx->lock);
1137
1138 /* mask register set */
1139 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1140
1141 switch (buf_type) {
1142 case IPP_BUF_ENQUEUE:
1143 masked = false;
1144 break;
1145 case IPP_BUF_DEQUEUE:
1146 masked = true;
1147 break;
1148 default:
1149 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1150 ret = -EINVAL;
1151 goto err_unlock;
1152 }
1153
1154 /* sequence id */
1155 cfg &= ~mask;
1156 cfg |= masked << buf_id;
1157 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
1158 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
1159 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
1160
1161 /* interrupt enable */
1162 if (buf_type == IPP_BUF_ENQUEUE &&
1163 gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
1164 gsc_handle_irq(ctx, true, false, true);
1165
1166 /* interrupt disable */
1167 if (buf_type == IPP_BUF_DEQUEUE &&
1168 gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
1169 gsc_handle_irq(ctx, false, false, true);
1170
1171 err_unlock:
1172 mutex_unlock(&ctx->lock);
1173 return ret;
1174 }
1175
1176 static int gsc_dst_set_addr(struct device *dev,
1177 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1178 enum drm_exynos_ipp_buf_type buf_type)
1179 {
1180 struct gsc_context *ctx = get_gsc_context(dev);
1181 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1182 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1183 struct drm_exynos_ipp_property *property;
1184
1185 if (!c_node) {
1186 DRM_ERROR("failed to get c_node.\n");
1187 return -EFAULT;
1188 }
1189
1190 property = &c_node->property;
1191
1192 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1193 property->prop_id, buf_id, buf_type);
1194
1195 if (buf_id > GSC_MAX_DST) {
1196 dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id);
1197 return -EINVAL;
1198 }
1199
1200 /* address register set */
1201 switch (buf_type) {
1202 case IPP_BUF_ENQUEUE:
1203 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1204 GSC_OUT_BASE_ADDR_Y(buf_id));
1205 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1206 GSC_OUT_BASE_ADDR_CB(buf_id));
1207 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1208 GSC_OUT_BASE_ADDR_CR(buf_id));
1209 break;
1210 case IPP_BUF_DEQUEUE:
1211 gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
1212 gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
1213 gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
1214 break;
1215 default:
1216 /* bypass */
1217 break;
1218 }
1219
1220 return gsc_dst_set_buf_seq(ctx, buf_id, buf_type);
1221 }
1222
1223 static struct exynos_drm_ipp_ops gsc_dst_ops = {
1224 .set_fmt = gsc_dst_set_fmt,
1225 .set_transf = gsc_dst_set_transf,
1226 .set_size = gsc_dst_set_size,
1227 .set_addr = gsc_dst_set_addr,
1228 };
1229
1230 static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable)
1231 {
1232 DRM_DEBUG_KMS("enable[%d]\n", enable);
1233
1234 if (enable) {
1235 clk_prepare_enable(ctx->gsc_clk);
1236 ctx->suspended = false;
1237 } else {
1238 clk_disable_unprepare(ctx->gsc_clk);
1239 ctx->suspended = true;
1240 }
1241
1242 return 0;
1243 }
1244
1245 static int gsc_get_src_buf_index(struct gsc_context *ctx)
1246 {
1247 u32 cfg, curr_index, i;
1248 u32 buf_id = GSC_MAX_SRC;
1249 int ret;
1250
1251 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1252
1253 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
1254 curr_index = GSC_IN_CURR_GET_INDEX(cfg);
1255
1256 for (i = curr_index; i < GSC_MAX_SRC; i++) {
1257 if (!((cfg >> i) & 0x1)) {
1258 buf_id = i;
1259 break;
1260 }
1261 }
1262
1263 if (buf_id == GSC_MAX_SRC) {
1264 DRM_ERROR("failed to get in buffer index.\n");
1265 return -EINVAL;
1266 }
1267
1268 ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1269 if (ret < 0) {
1270 DRM_ERROR("failed to dequeue.\n");
1271 return ret;
1272 }
1273
1274 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1275 curr_index, buf_id);
1276
1277 return buf_id;
1278 }
1279
1280 static int gsc_get_dst_buf_index(struct gsc_context *ctx)
1281 {
1282 u32 cfg, curr_index, i;
1283 u32 buf_id = GSC_MAX_DST;
1284 int ret;
1285
1286 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1287
1288 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1289 curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
1290
1291 for (i = curr_index; i < GSC_MAX_DST; i++) {
1292 if (!((cfg >> i) & 0x1)) {
1293 buf_id = i;
1294 break;
1295 }
1296 }
1297
1298 if (buf_id == GSC_MAX_DST) {
1299 DRM_ERROR("failed to get out buffer index.\n");
1300 return -EINVAL;
1301 }
1302
1303 ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1304 if (ret < 0) {
1305 DRM_ERROR("failed to dequeue.\n");
1306 return ret;
1307 }
1308
1309 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1310 curr_index, buf_id);
1311
1312 return buf_id;
1313 }
1314
1315 static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1316 {
1317 struct gsc_context *ctx = dev_id;
1318 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1319 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1320 struct drm_exynos_ipp_event_work *event_work =
1321 c_node->event_work;
1322 u32 status;
1323 int buf_id[EXYNOS_DRM_OPS_MAX];
1324
1325 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1326
1327 status = gsc_read(GSC_IRQ);
1328 if (status & GSC_IRQ_STATUS_OR_IRQ) {
1329 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
1330 ctx->id, status);
1331 return IRQ_NONE;
1332 }
1333
1334 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1335 dev_dbg(ippdrv->dev, "occurred frame done at %d, status 0x%x.\n",
1336 ctx->id, status);
1337
1338 buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx);
1339 if (buf_id[EXYNOS_DRM_OPS_SRC] < 0)
1340 return IRQ_HANDLED;
1341
1342 buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx);
1343 if (buf_id[EXYNOS_DRM_OPS_DST] < 0)
1344 return IRQ_HANDLED;
1345
1346 DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n",
1347 buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]);
1348
1349 event_work->ippdrv = ippdrv;
1350 event_work->buf_id[EXYNOS_DRM_OPS_SRC] =
1351 buf_id[EXYNOS_DRM_OPS_SRC];
1352 event_work->buf_id[EXYNOS_DRM_OPS_DST] =
1353 buf_id[EXYNOS_DRM_OPS_DST];
1354 queue_work(ippdrv->event_workq, &event_work->work);
1355 }
1356
1357 return IRQ_HANDLED;
1358 }
1359
1360 static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1361 {
1362 struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1363
1364 prop_list->version = 1;
1365 prop_list->writeback = 1;
1366 prop_list->refresh_min = GSC_REFRESH_MIN;
1367 prop_list->refresh_max = GSC_REFRESH_MAX;
1368 prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1369 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1370 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1371 (1 << EXYNOS_DRM_DEGREE_90) |
1372 (1 << EXYNOS_DRM_DEGREE_180) |
1373 (1 << EXYNOS_DRM_DEGREE_270);
1374 prop_list->csc = 1;
1375 prop_list->crop = 1;
1376 prop_list->crop_max.hsize = GSC_CROP_MAX;
1377 prop_list->crop_max.vsize = GSC_CROP_MAX;
1378 prop_list->crop_min.hsize = GSC_CROP_MIN;
1379 prop_list->crop_min.vsize = GSC_CROP_MIN;
1380 prop_list->scale = 1;
1381 prop_list->scale_max.hsize = GSC_SCALE_MAX;
1382 prop_list->scale_max.vsize = GSC_SCALE_MAX;
1383 prop_list->scale_min.hsize = GSC_SCALE_MIN;
1384 prop_list->scale_min.vsize = GSC_SCALE_MIN;
1385
1386 return 0;
1387 }
1388
1389 static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip)
1390 {
1391 switch (flip) {
1392 case EXYNOS_DRM_FLIP_NONE:
1393 case EXYNOS_DRM_FLIP_VERTICAL:
1394 case EXYNOS_DRM_FLIP_HORIZONTAL:
1395 case EXYNOS_DRM_FLIP_BOTH:
1396 return true;
1397 default:
1398 DRM_DEBUG_KMS("invalid flip\n");
1399 return false;
1400 }
1401 }
1402
1403 static int gsc_ippdrv_check_property(struct device *dev,
1404 struct drm_exynos_ipp_property *property)
1405 {
1406 struct gsc_context *ctx = get_gsc_context(dev);
1407 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1408 struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1409 struct drm_exynos_ipp_config *config;
1410 struct drm_exynos_pos *pos;
1411 struct drm_exynos_sz *sz;
1412 bool swap;
1413 int i;
1414
1415 for_each_ipp_ops(i) {
1416 if ((i == EXYNOS_DRM_OPS_SRC) &&
1417 (property->cmd == IPP_CMD_WB))
1418 continue;
1419
1420 config = &property->config[i];
1421 pos = &config->pos;
1422 sz = &config->sz;
1423
1424 /* check for flip */
1425 if (!gsc_check_drm_flip(config->flip)) {
1426 DRM_ERROR("invalid flip.\n");
1427 goto err_property;
1428 }
1429
1430 /* check for degree */
1431 switch (config->degree) {
1432 case EXYNOS_DRM_DEGREE_90:
1433 case EXYNOS_DRM_DEGREE_270:
1434 swap = true;
1435 break;
1436 case EXYNOS_DRM_DEGREE_0:
1437 case EXYNOS_DRM_DEGREE_180:
1438 swap = false;
1439 break;
1440 default:
1441 DRM_ERROR("invalid degree.\n");
1442 goto err_property;
1443 }
1444
1445 /* check for buffer bound */
1446 if ((pos->x + pos->w > sz->hsize) ||
1447 (pos->y + pos->h > sz->vsize)) {
1448 DRM_ERROR("out of buf bound.\n");
1449 goto err_property;
1450 }
1451
1452 /* check for crop */
1453 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1454 if (swap) {
1455 if ((pos->h < pp->crop_min.hsize) ||
1456 (sz->vsize > pp->crop_max.hsize) ||
1457 (pos->w < pp->crop_min.vsize) ||
1458 (sz->hsize > pp->crop_max.vsize)) {
1459 DRM_ERROR("out of crop size.\n");
1460 goto err_property;
1461 }
1462 } else {
1463 if ((pos->w < pp->crop_min.hsize) ||
1464 (sz->hsize > pp->crop_max.hsize) ||
1465 (pos->h < pp->crop_min.vsize) ||
1466 (sz->vsize > pp->crop_max.vsize)) {
1467 DRM_ERROR("out of crop size.\n");
1468 goto err_property;
1469 }
1470 }
1471 }
1472
1473 /* check for scale */
1474 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1475 if (swap) {
1476 if ((pos->h < pp->scale_min.hsize) ||
1477 (sz->vsize > pp->scale_max.hsize) ||
1478 (pos->w < pp->scale_min.vsize) ||
1479 (sz->hsize > pp->scale_max.vsize)) {
1480 DRM_ERROR("out of scale size.\n");
1481 goto err_property;
1482 }
1483 } else {
1484 if ((pos->w < pp->scale_min.hsize) ||
1485 (sz->hsize > pp->scale_max.hsize) ||
1486 (pos->h < pp->scale_min.vsize) ||
1487 (sz->vsize > pp->scale_max.vsize)) {
1488 DRM_ERROR("out of scale size.\n");
1489 goto err_property;
1490 }
1491 }
1492 }
1493 }
1494
1495 return 0;
1496
1497 err_property:
1498 for_each_ipp_ops(i) {
1499 if ((i == EXYNOS_DRM_OPS_SRC) &&
1500 (property->cmd == IPP_CMD_WB))
1501 continue;
1502
1503 config = &property->config[i];
1504 pos = &config->pos;
1505 sz = &config->sz;
1506
1507 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1508 i ? "dst" : "src", config->flip, config->degree,
1509 pos->x, pos->y, pos->w, pos->h,
1510 sz->hsize, sz->vsize);
1511 }
1512
1513 return -EINVAL;
1514 }
1515
1516
1517 static int gsc_ippdrv_reset(struct device *dev)
1518 {
1519 struct gsc_context *ctx = get_gsc_context(dev);
1520 struct gsc_scaler *sc = &ctx->sc;
1521 int ret;
1522
1523 /* reset h/w block */
1524 ret = gsc_sw_reset(ctx);
1525 if (ret < 0) {
1526 dev_err(dev, "failed to reset hardware.\n");
1527 return ret;
1528 }
1529
1530 /* scaler setting */
1531 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1532 sc->range = true;
1533
1534 return 0;
1535 }
1536
1537 static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1538 {
1539 struct gsc_context *ctx = get_gsc_context(dev);
1540 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1541 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1542 struct drm_exynos_ipp_property *property;
1543 struct drm_exynos_ipp_config *config;
1544 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1545 struct drm_exynos_ipp_set_wb set_wb;
1546 u32 cfg;
1547 int ret, i;
1548
1549 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1550
1551 if (!c_node) {
1552 DRM_ERROR("failed to get c_node.\n");
1553 return -EINVAL;
1554 }
1555
1556 property = &c_node->property;
1557
1558 gsc_handle_irq(ctx, true, false, true);
1559
1560 for_each_ipp_ops(i) {
1561 config = &property->config[i];
1562 img_pos[i] = config->pos;
1563 }
1564
1565 switch (cmd) {
1566 case IPP_CMD_M2M:
1567 /* enable one shot */
1568 cfg = gsc_read(GSC_ENABLE);
1569 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1570 GSC_ENABLE_CLK_GATE_MODE_MASK);
1571 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1572 gsc_write(cfg, GSC_ENABLE);
1573
1574 /* src dma memory */
1575 cfg = gsc_read(GSC_IN_CON);
1576 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1577 cfg |= GSC_IN_PATH_MEMORY;
1578 gsc_write(cfg, GSC_IN_CON);
1579
1580 /* dst dma memory */
1581 cfg = gsc_read(GSC_OUT_CON);
1582 cfg |= GSC_OUT_PATH_MEMORY;
1583 gsc_write(cfg, GSC_OUT_CON);
1584 break;
1585 case IPP_CMD_WB:
1586 set_wb.enable = 1;
1587 set_wb.refresh = property->refresh_rate;
1588 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1589 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1590
1591 /* src local path */
1592 cfg = gsc_read(GSC_IN_CON);
1593 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1594 cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB);
1595 gsc_write(cfg, GSC_IN_CON);
1596
1597 /* dst dma memory */
1598 cfg = gsc_read(GSC_OUT_CON);
1599 cfg |= GSC_OUT_PATH_MEMORY;
1600 gsc_write(cfg, GSC_OUT_CON);
1601 break;
1602 case IPP_CMD_OUTPUT:
1603 /* src dma memory */
1604 cfg = gsc_read(GSC_IN_CON);
1605 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1606 cfg |= GSC_IN_PATH_MEMORY;
1607 gsc_write(cfg, GSC_IN_CON);
1608
1609 /* dst local path */
1610 cfg = gsc_read(GSC_OUT_CON);
1611 cfg |= GSC_OUT_PATH_MEMORY;
1612 gsc_write(cfg, GSC_OUT_CON);
1613 break;
1614 default:
1615 ret = -EINVAL;
1616 dev_err(dev, "invalid operations.\n");
1617 return ret;
1618 }
1619
1620 ret = gsc_set_prescaler(ctx, &ctx->sc,
1621 &img_pos[EXYNOS_DRM_OPS_SRC],
1622 &img_pos[EXYNOS_DRM_OPS_DST]);
1623 if (ret) {
1624 dev_err(dev, "failed to set precalser.\n");
1625 return ret;
1626 }
1627
1628 gsc_set_scaler(ctx, &ctx->sc);
1629
1630 cfg = gsc_read(GSC_ENABLE);
1631 cfg |= GSC_ENABLE_ON;
1632 gsc_write(cfg, GSC_ENABLE);
1633
1634 return 0;
1635 }
1636
1637 static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1638 {
1639 struct gsc_context *ctx = get_gsc_context(dev);
1640 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1641 u32 cfg;
1642
1643 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1644
1645 switch (cmd) {
1646 case IPP_CMD_M2M:
1647 /* bypass */
1648 break;
1649 case IPP_CMD_WB:
1650 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1651 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1652 break;
1653 case IPP_CMD_OUTPUT:
1654 default:
1655 dev_err(dev, "invalid operations.\n");
1656 break;
1657 }
1658
1659 gsc_handle_irq(ctx, false, false, true);
1660
1661 /* reset sequence */
1662 gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK);
1663 gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK);
1664 gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK);
1665
1666 cfg = gsc_read(GSC_ENABLE);
1667 cfg &= ~GSC_ENABLE_ON;
1668 gsc_write(cfg, GSC_ENABLE);
1669 }
1670
1671 static int gsc_probe(struct platform_device *pdev)
1672 {
1673 struct device *dev = &pdev->dev;
1674 struct gsc_context *ctx;
1675 struct resource *res;
1676 struct exynos_drm_ippdrv *ippdrv;
1677 int ret;
1678
1679 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1680 if (!ctx)
1681 return -ENOMEM;
1682
1683 if (dev->of_node) {
1684 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1685 "samsung,sysreg");
1686 if (IS_ERR(ctx->sysreg)) {
1687 dev_warn(dev, "failed to get system register.\n");
1688 ctx->sysreg = NULL;
1689 }
1690 }
1691
1692 /* clock control */
1693 ctx->gsc_clk = devm_clk_get(dev, "gscl");
1694 if (IS_ERR(ctx->gsc_clk)) {
1695 dev_err(dev, "failed to get gsc clock.\n");
1696 return PTR_ERR(ctx->gsc_clk);
1697 }
1698
1699 /* resource memory */
1700 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1701 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1702 if (IS_ERR(ctx->regs))
1703 return PTR_ERR(ctx->regs);
1704
1705 /* resource irq */
1706 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1707 if (!res) {
1708 dev_err(dev, "failed to request irq resource.\n");
1709 return -ENOENT;
1710 }
1711
1712 ctx->irq = res->start;
1713 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler,
1714 IRQF_ONESHOT, "drm_gsc", ctx);
1715 if (ret < 0) {
1716 dev_err(dev, "failed to request irq.\n");
1717 return ret;
1718 }
1719
1720 /* context initailization */
1721 ctx->id = pdev->id;
1722
1723 ippdrv = &ctx->ippdrv;
1724 ippdrv->dev = dev;
1725 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops;
1726 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops;
1727 ippdrv->check_property = gsc_ippdrv_check_property;
1728 ippdrv->reset = gsc_ippdrv_reset;
1729 ippdrv->start = gsc_ippdrv_start;
1730 ippdrv->stop = gsc_ippdrv_stop;
1731 ret = gsc_init_prop_list(ippdrv);
1732 if (ret < 0) {
1733 dev_err(dev, "failed to init property list.\n");
1734 return ret;
1735 }
1736
1737 DRM_DEBUG_KMS("id[%d]ippdrv[%p]\n", ctx->id, ippdrv);
1738
1739 mutex_init(&ctx->lock);
1740 platform_set_drvdata(pdev, ctx);
1741
1742 pm_runtime_enable(dev);
1743
1744 ret = exynos_drm_ippdrv_register(ippdrv);
1745 if (ret < 0) {
1746 dev_err(dev, "failed to register drm gsc device.\n");
1747 goto err_ippdrv_register;
1748 }
1749
1750 dev_info(dev, "drm gsc registered successfully.\n");
1751
1752 return 0;
1753
1754 err_ippdrv_register:
1755 pm_runtime_disable(dev);
1756 return ret;
1757 }
1758
1759 static int gsc_remove(struct platform_device *pdev)
1760 {
1761 struct device *dev = &pdev->dev;
1762 struct gsc_context *ctx = get_gsc_context(dev);
1763 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1764
1765 exynos_drm_ippdrv_unregister(ippdrv);
1766 mutex_destroy(&ctx->lock);
1767
1768 pm_runtime_set_suspended(dev);
1769 pm_runtime_disable(dev);
1770
1771 return 0;
1772 }
1773
1774 static int __maybe_unused gsc_runtime_suspend(struct device *dev)
1775 {
1776 struct gsc_context *ctx = get_gsc_context(dev);
1777
1778 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1779
1780 return gsc_clk_ctrl(ctx, false);
1781 }
1782
1783 static int __maybe_unused gsc_runtime_resume(struct device *dev)
1784 {
1785 struct gsc_context *ctx = get_gsc_context(dev);
1786
1787 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1788
1789 return gsc_clk_ctrl(ctx, true);
1790 }
1791
1792 static const struct dev_pm_ops gsc_pm_ops = {
1793 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1794 pm_runtime_force_resume)
1795 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1796 };
1797
1798 static const struct of_device_id exynos_drm_gsc_of_match[] = {
1799 { .compatible = "samsung,exynos5-gsc" },
1800 { },
1801 };
1802 MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match);
1803
1804 struct platform_driver gsc_driver = {
1805 .probe = gsc_probe,
1806 .remove = gsc_remove,
1807 .driver = {
1808 .name = "exynos-drm-gsc",
1809 .owner = THIS_MODULE,
1810 .pm = &gsc_pm_ops,
1811 .of_match_table = of_match_ptr(exynos_drm_gsc_of_match),
1812 },
1813 };
1814
Linux with added FPC-III support