| blob | d7cbe53c4c01f440cf9c0aecec153dc3d4f3f912 |
1 /* drivers/gpu/drm/exynos/regs-fimc.h
2 *
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Register definition file for Samsung Camera Interface (FIMC) driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
13 #ifndef EXYNOS_REGS_FIMC_H
14 #define EXYNOS_REGS_FIMC_H
16 /*
17 * Register part
18 */
19 /* Input source format */
20 #define EXYNOS_CISRCFMT (0x00)
21 /* Window offset */
22 #define EXYNOS_CIWDOFST (0x04)
23 /* Global control */
24 #define EXYNOS_CIGCTRL (0x08)
25 /* Window offset 2 */
26 #define EXYNOS_CIWDOFST2 (0x14)
27 /* Y 1st frame start address for output DMA */
28 #define EXYNOS_CIOYSA1 (0x18)
29 /* Y 2nd frame start address for output DMA */
30 #define EXYNOS_CIOYSA2 (0x1c)
31 /* Y 3rd frame start address for output DMA */
32 #define EXYNOS_CIOYSA3 (0x20)
33 /* Y 4th frame start address for output DMA */
34 #define EXYNOS_CIOYSA4 (0x24)
35 /* Cb 1st frame start address for output DMA */
36 #define EXYNOS_CIOCBSA1 (0x28)
37 /* Cb 2nd frame start address for output DMA */
38 #define EXYNOS_CIOCBSA2 (0x2c)
39 /* Cb 3rd frame start address for output DMA */
40 #define EXYNOS_CIOCBSA3 (0x30)
41 /* Cb 4th frame start address for output DMA */
42 #define EXYNOS_CIOCBSA4 (0x34)
43 /* Cr 1st frame start address for output DMA */
44 #define EXYNOS_CIOCRSA1 (0x38)
45 /* Cr 2nd frame start address for output DMA */
46 #define EXYNOS_CIOCRSA2 (0x3c)
47 /* Cr 3rd frame start address for output DMA */
48 #define EXYNOS_CIOCRSA3 (0x40)
49 /* Cr 4th frame start address for output DMA */
50 #define EXYNOS_CIOCRSA4 (0x44)
51 /* Target image format */
52 #define EXYNOS_CITRGFMT (0x48)
53 /* Output DMA control */
54 #define EXYNOS_CIOCTRL (0x4c)
55 /* Pre-scaler control 1 */
56 #define EXYNOS_CISCPRERATIO (0x50)
57 /* Pre-scaler control 2 */
58 #define EXYNOS_CISCPREDST (0x54)
59 /* Main scaler control */
60 #define EXYNOS_CISCCTRL (0x58)
61 /* Target area */
62 #define EXYNOS_CITAREA (0x5c)
63 /* Status */
64 #define EXYNOS_CISTATUS (0x64)
65 /* Status2 */
66 #define EXYNOS_CISTATUS2 (0x68)
67 /* Image capture enable command */
68 #define EXYNOS_CIIMGCPT (0xc0)
69 /* Capture sequence */
70 #define EXYNOS_CICPTSEQ (0xc4)
71 /* Image effects */
72 #define EXYNOS_CIIMGEFF (0xd0)
73 /* Y frame start address for input DMA */
74 #define EXYNOS_CIIYSA0 (0xd4)
75 /* Cb frame start address for input DMA */
76 #define EXYNOS_CIICBSA0 (0xd8)
77 /* Cr frame start address for input DMA */
78 #define EXYNOS_CIICRSA0 (0xdc)
79 /* Input DMA Y Line Skip */
80 #define EXYNOS_CIILINESKIP_Y (0xec)
81 /* Input DMA Cb Line Skip */
82 #define EXYNOS_CIILINESKIP_CB (0xf0)
83 /* Input DMA Cr Line Skip */
84 #define EXYNOS_CIILINESKIP_CR (0xf4)
85 /* Real input DMA image size */
86 #define EXYNOS_CIREAL_ISIZE (0xf8)
87 /* Input DMA control */
88 #define EXYNOS_MSCTRL (0xfc)
89 /* Y frame start address for input DMA */
90 #define EXYNOS_CIIYSA1 (0x144)
91 /* Cb frame start address for input DMA */
92 #define EXYNOS_CIICBSA1 (0x148)
93 /* Cr frame start address for input DMA */
94 #define EXYNOS_CIICRSA1 (0x14c)
95 /* Output DMA Y offset */
96 #define EXYNOS_CIOYOFF (0x168)
97 /* Output DMA CB offset */
98 #define EXYNOS_CIOCBOFF (0x16c)
99 /* Output DMA CR offset */
100 #define EXYNOS_CIOCROFF (0x170)
101 /* Input DMA Y offset */
102 #define EXYNOS_CIIYOFF (0x174)
103 /* Input DMA CB offset */
104 #define EXYNOS_CIICBOFF (0x178)
105 /* Input DMA CR offset */
106 #define EXYNOS_CIICROFF (0x17c)
107 /* Input DMA original image size */
108 #define EXYNOS_ORGISIZE (0x180)
109 /* Output DMA original image size */
110 #define EXYNOS_ORGOSIZE (0x184)
111 /* Real output DMA image size */
112 #define EXYNOS_CIEXTEN (0x188)
113 /* DMA parameter */
114 #define EXYNOS_CIDMAPARAM (0x18c)
115 /* MIPI CSI image format */
116 #define EXYNOS_CSIIMGFMT (0x194)
117 /* FIMC Clock Source Select */
118 #define EXYNOS_MISC_FIMC (0x198)
120 /* Add for FIMC v5.1 */
121 /* Output Frame Buffer Sequence */
122 #define EXYNOS_CIFCNTSEQ (0x1fc)
123 /* Y 5th frame start address for output DMA */
124 #define EXYNOS_CIOYSA5 (0x200)
125 /* Y 6th frame start address for output DMA */
126 #define EXYNOS_CIOYSA6 (0x204)
127 /* Y 7th frame start address for output DMA */
128 #define EXYNOS_CIOYSA7 (0x208)
129 /* Y 8th frame start address for output DMA */
130 #define EXYNOS_CIOYSA8 (0x20c)
131 /* Y 9th frame start address for output DMA */
132 #define EXYNOS_CIOYSA9 (0x210)
133 /* Y 10th frame start address for output DMA */
134 #define EXYNOS_CIOYSA10 (0x214)
135 /* Y 11th frame start address for output DMA */
136 #define EXYNOS_CIOYSA11 (0x218)
137 /* Y 12th frame start address for output DMA */
138 #define EXYNOS_CIOYSA12 (0x21c)
139 /* Y 13th frame start address for output DMA */
140 #define EXYNOS_CIOYSA13 (0x220)
141 /* Y 14th frame start address for output DMA */
142 #define EXYNOS_CIOYSA14 (0x224)
143 /* Y 15th frame start address for output DMA */
144 #define EXYNOS_CIOYSA15 (0x228)
145 /* Y 16th frame start address for output DMA */
146 #define EXYNOS_CIOYSA16 (0x22c)
147 /* Y 17th frame start address for output DMA */
148 #define EXYNOS_CIOYSA17 (0x230)
149 /* Y 18th frame start address for output DMA */
150 #define EXYNOS_CIOYSA18 (0x234)
151 /* Y 19th frame start address for output DMA */
152 #define EXYNOS_CIOYSA19 (0x238)
153 /* Y 20th frame start address for output DMA */
154 #define EXYNOS_CIOYSA20 (0x23c)
155 /* Y 21th frame start address for output DMA */
156 #define EXYNOS_CIOYSA21 (0x240)
157 /* Y 22th frame start address for output DMA */
158 #define EXYNOS_CIOYSA22 (0x244)
159 /* Y 23th frame start address for output DMA */
160 #define EXYNOS_CIOYSA23 (0x248)
161 /* Y 24th frame start address for output DMA */
162 #define EXYNOS_CIOYSA24 (0x24c)
163 /* Y 25th frame start address for output DMA */
164 #define EXYNOS_CIOYSA25 (0x250)
165 /* Y 26th frame start address for output DMA */
166 #define EXYNOS_CIOYSA26 (0x254)
167 /* Y 27th frame start address for output DMA */
168 #define EXYNOS_CIOYSA27 (0x258)
169 /* Y 28th frame start address for output DMA */
170 #define EXYNOS_CIOYSA28 (0x25c)
171 /* Y 29th frame start address for output DMA */
172 #define EXYNOS_CIOYSA29 (0x260)
173 /* Y 30th frame start address for output DMA */
174 #define EXYNOS_CIOYSA30 (0x264)
175 /* Y 31th frame start address for output DMA */
176 #define EXYNOS_CIOYSA31 (0x268)
177 /* Y 32th frame start address for output DMA */
178 #define EXYNOS_CIOYSA32 (0x26c)
180 /* CB 5th frame start address for output DMA */
181 #define EXYNOS_CIOCBSA5 (0x270)
182 /* CB 6th frame start address for output DMA */
183 #define EXYNOS_CIOCBSA6 (0x274)
184 /* CB 7th frame start address for output DMA */
185 #define EXYNOS_CIOCBSA7 (0x278)
186 /* CB 8th frame start address for output DMA */
187 #define EXYNOS_CIOCBSA8 (0x27c)
188 /* CB 9th frame start address for output DMA */
189 #define EXYNOS_CIOCBSA9 (0x280)
190 /* CB 10th frame start address for output DMA */
191 #define EXYNOS_CIOCBSA10 (0x284)
192 /* CB 11th frame start address for output DMA */
193 #define EXYNOS_CIOCBSA11 (0x288)
194 /* CB 12th frame start address for output DMA */
195 #define EXYNOS_CIOCBSA12 (0x28c)
196 /* CB 13th frame start address for output DMA */
197 #define EXYNOS_CIOCBSA13 (0x290)
198 /* CB 14th frame start address for output DMA */
199 #define EXYNOS_CIOCBSA14 (0x294)
200 /* CB 15th frame start address for output DMA */
201 #define EXYNOS_CIOCBSA15 (0x298)
202 /* CB 16th frame start address for output DMA */
203 #define EXYNOS_CIOCBSA16 (0x29c)
204 /* CB 17th frame start address for output DMA */
205 #define EXYNOS_CIOCBSA17 (0x2a0)
206 /* CB 18th frame start address for output DMA */
207 #define EXYNOS_CIOCBSA18 (0x2a4)
208 /* CB 19th frame start address for output DMA */
209 #define EXYNOS_CIOCBSA19 (0x2a8)
210 /* CB 20th frame start address for output DMA */
211 #define EXYNOS_CIOCBSA20 (0x2ac)
212 /* CB 21th frame start address for output DMA */
213 #define EXYNOS_CIOCBSA21 (0x2b0)
214 /* CB 22th frame start address for output DMA */
215 #define EXYNOS_CIOCBSA22 (0x2b4)
216 /* CB 23th frame start address for output DMA */
217 #define EXYNOS_CIOCBSA23 (0x2b8)
218 /* CB 24th frame start address for output DMA */
219 #define EXYNOS_CIOCBSA24 (0x2bc)
220 /* CB 25th frame start address for output DMA */
221 #define EXYNOS_CIOCBSA25 (0x2c0)
222 /* CB 26th frame start address for output DMA */
223 #define EXYNOS_CIOCBSA26 (0x2c4)
224 /* CB 27th frame start address for output DMA */
225 #define EXYNOS_CIOCBSA27 (0x2c8)
226 /* CB 28th frame start address for output DMA */
227 #define EXYNOS_CIOCBSA28 (0x2cc)
228 /* CB 29th frame start address for output DMA */
229 #define EXYNOS_CIOCBSA29 (0x2d0)
230 /* CB 30th frame start address for output DMA */
231 #define EXYNOS_CIOCBSA30 (0x2d4)
232 /* CB 31th frame start address for output DMA */
233 #define EXYNOS_CIOCBSA31 (0x2d8)
234 /* CB 32th frame start address for output DMA */
235 #define EXYNOS_CIOCBSA32 (0x2dc)
237 /* CR 5th frame start address for output DMA */
238 #define EXYNOS_CIOCRSA5 (0x2e0)
239 /* CR 6th frame start address for output DMA */
240 #define EXYNOS_CIOCRSA6 (0x2e4)
241 /* CR 7th frame start address for output DMA */
242 #define EXYNOS_CIOCRSA7 (0x2e8)
243 /* CR 8th frame start address for output DMA */
244 #define EXYNOS_CIOCRSA8 (0x2ec)
245 /* CR 9th frame start address for output DMA */
246 #define EXYNOS_CIOCRSA9 (0x2f0)
247 /* CR 10th frame start address for output DMA */
248 #define EXYNOS_CIOCRSA10 (0x2f4)
249 /* CR 11th frame start address for output DMA */
250 #define EXYNOS_CIOCRSA11 (0x2f8)
251 /* CR 12th frame start address for output DMA */
252 #define EXYNOS_CIOCRSA12 (0x2fc)
253 /* CR 13th frame start address for output DMA */
254 #define EXYNOS_CIOCRSA13 (0x300)
255 /* CR 14th frame start address for output DMA */
256 #define EXYNOS_CIOCRSA14 (0x304)
257 /* CR 15th frame start address for output DMA */
258 #define EXYNOS_CIOCRSA15 (0x308)
259 /* CR 16th frame start address for output DMA */
260 #define EXYNOS_CIOCRSA16 (0x30c)
261 /* CR 17th frame start address for output DMA */
262 #define EXYNOS_CIOCRSA17 (0x310)
263 /* CR 18th frame start address for output DMA */
264 #define EXYNOS_CIOCRSA18 (0x314)
265 /* CR 19th frame start address for output DMA */
266 #define EXYNOS_CIOCRSA19 (0x318)
267 /* CR 20th frame start address for output DMA */
268 #define EXYNOS_CIOCRSA20 (0x31c)
269 /* CR 21th frame start address for output DMA */
270 #define EXYNOS_CIOCRSA21 (0x320)
271 /* CR 22th frame start address for output DMA */
272 #define EXYNOS_CIOCRSA22 (0x324)
273 /* CR 23th frame start address for output DMA */
274 #define EXYNOS_CIOCRSA23 (0x328)
275 /* CR 24th frame start address for output DMA */
276 #define EXYNOS_CIOCRSA24 (0x32c)
277 /* CR 25th frame start address for output DMA */
278 #define EXYNOS_CIOCRSA25 (0x330)
279 /* CR 26th frame start address for output DMA */
280 #define EXYNOS_CIOCRSA26 (0x334)
281 /* CR 27th frame start address for output DMA */
282 #define EXYNOS_CIOCRSA27 (0x338)
283 /* CR 28th frame start address for output DMA */
284 #define EXYNOS_CIOCRSA28 (0x33c)
285 /* CR 29th frame start address for output DMA */
286 #define EXYNOS_CIOCRSA29 (0x340)
287 /* CR 30th frame start address for output DMA */
288 #define EXYNOS_CIOCRSA30 (0x344)
289 /* CR 31th frame start address for output DMA */
290 #define EXYNOS_CIOCRSA31 (0x348)
291 /* CR 32th frame start address for output DMA */
292 #define EXYNOS_CIOCRSA32 (0x34c)
294 /*
295 * Macro part
296 */
297 /* frame start address 1 ~ 4, 5 ~ 32 */
298 /* Number of Default PingPong Memory */
299 #define DEF_PP 4
300 #define EXYNOS_CIOYSA(__x) \
301 (((__x) < DEF_PP) ? \
302 (EXYNOS_CIOYSA1 + (__x) * 4) : \
303 (EXYNOS_CIOYSA5 + ((__x) - DEF_PP) * 4))
304 #define EXYNOS_CIOCBSA(__x) \
305 (((__x) < DEF_PP) ? \
306 (EXYNOS_CIOCBSA1 + (__x) * 4) : \
307 (EXYNOS_CIOCBSA5 + ((__x) - DEF_PP) * 4))
308 #define EXYNOS_CIOCRSA(__x) \
309 (((__x) < DEF_PP) ? \
310 (EXYNOS_CIOCRSA1 + (__x) * 4) : \
311 (EXYNOS_CIOCRSA5 + ((__x) - DEF_PP) * 4))
312 /* Number of Default PingPong Memory */
313 #define DEF_IPP 1
314 #define EXYNOS_CIIYSA(__x) \
315 (((__x) < DEF_IPP) ? \
316 (EXYNOS_CIIYSA0) : (EXYNOS_CIIYSA1))
317 #define EXYNOS_CIICBSA(__x) \
318 (((__x) < DEF_IPP) ? \
319 (EXYNOS_CIICBSA0) : (EXYNOS_CIICBSA1))
320 #define EXYNOS_CIICRSA(__x) \
321 (((__x) < DEF_IPP) ? \
322 (EXYNOS_CIICRSA0) : (EXYNOS_CIICRSA1))
324 #define EXYNOS_CISRCFMT_SOURCEHSIZE(x) ((x) << 16)
325 #define EXYNOS_CISRCFMT_SOURCEVSIZE(x) ((x) << 0)
327 #define EXYNOS_CIWDOFST_WINHOROFST(x) ((x) << 16)
328 #define EXYNOS_CIWDOFST_WINVEROFST(x) ((x) << 0)
330 #define EXYNOS_CIWDOFST2_WINHOROFST2(x) ((x) << 16)
331 #define EXYNOS_CIWDOFST2_WINVEROFST2(x) ((x) << 0)
333 #define EXYNOS_CITRGFMT_TARGETHSIZE(x) (((x) & 0x1fff) << 16)
334 #define EXYNOS_CITRGFMT_TARGETVSIZE(x) (((x) & 0x1fff) << 0)
336 #define EXYNOS_CISCPRERATIO_SHFACTOR(x) ((x) << 28)
337 #define EXYNOS_CISCPRERATIO_PREHORRATIO(x) ((x) << 16)
338 #define EXYNOS_CISCPRERATIO_PREVERRATIO(x) ((x) << 0)
340 #define EXYNOS_CISCPREDST_PREDSTWIDTH(x) ((x) << 16)
341 #define EXYNOS_CISCPREDST_PREDSTHEIGHT(x) ((x) << 0)
343 #define EXYNOS_CISCCTRL_MAINHORRATIO(x) ((x) << 16)
344 #define EXYNOS_CISCCTRL_MAINVERRATIO(x) ((x) << 0)
346 #define EXYNOS_CITAREA_TARGET_AREA(x) ((x) << 0)
348 #define EXYNOS_CISTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3)
349 #define EXYNOS_CISTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1)
350 #define EXYNOS_CISTATUS_GET_LAST_CAPTURE_END(x) (((x) >> 16) & 0x1)
351 #define EXYNOS_CISTATUS_GET_LCD_STATUS(x) (((x) >> 9) & 0x1)
352 #define EXYNOS_CISTATUS_GET_ENVID_STATUS(x) (((x) >> 8) & 0x1)
354 #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(x) (((x) >> 7) & 0x3f)
355 #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(x) ((x) & 0x3f)
357 #define EXYNOS_CIIMGEFF_FIN(x) ((x & 0x7) << 26)
358 #define EXYNOS_CIIMGEFF_PAT_CB(x) ((x) << 13)
359 #define EXYNOS_CIIMGEFF_PAT_CR(x) ((x) << 0)
361 #define EXYNOS_CIILINESKIP(x) (((x) & 0xf) << 24)
363 #define EXYNOS_CIREAL_ISIZE_HEIGHT(x) ((x) << 16)
364 #define EXYNOS_CIREAL_ISIZE_WIDTH(x) ((x) << 0)
366 #define EXYNOS_MSCTRL_SUCCESSIVE_COUNT(x) ((x) << 24)
367 #define EXYNOS_MSCTRL_GET_INDMA_STATUS(x) ((x) & 0x1)
369 #define EXYNOS_CIOYOFF_VERTICAL(x) ((x) << 16)
370 #define EXYNOS_CIOYOFF_HORIZONTAL(x) ((x) << 0)
372 #define EXYNOS_CIOCBOFF_VERTICAL(x) ((x) << 16)
373 #define EXYNOS_CIOCBOFF_HORIZONTAL(x) ((x) << 0)
375 #define EXYNOS_CIOCROFF_VERTICAL(x) ((x) << 16)
376 #define EXYNOS_CIOCROFF_HORIZONTAL(x) ((x) << 0)
378 #define EXYNOS_CIIYOFF_VERTICAL(x) ((x) << 16)
379 #define EXYNOS_CIIYOFF_HORIZONTAL(x) ((x) << 0)
381 #define EXYNOS_CIICBOFF_VERTICAL(x) ((x) << 16)
382 #define EXYNOS_CIICBOFF_HORIZONTAL(x) ((x) << 0)
384 #define EXYNOS_CIICROFF_VERTICAL(x) ((x) << 16)
385 #define EXYNOS_CIICROFF_HORIZONTAL(x) ((x) << 0)
387 #define EXYNOS_ORGISIZE_VERTICAL(x) ((x) << 16)
388 #define EXYNOS_ORGISIZE_HORIZONTAL(x) ((x) << 0)
390 #define EXYNOS_ORGOSIZE_VERTICAL(x) ((x) << 16)
391 #define EXYNOS_ORGOSIZE_HORIZONTAL(x) ((x) << 0)
393 #define EXYNOS_CIEXTEN_TARGETH_EXT(x) ((((x) & 0x2000) >> 13) << 26)
394 #define EXYNOS_CIEXTEN_TARGETV_EXT(x) ((((x) & 0x2000) >> 13) << 24)
395 #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT(x) (((x) & 0x3F) << 10)
396 #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT(x) ((x) & 0x3F)
398 /*
399 * Bit definition part
400 */
401 /* Source format register */
402 #define EXYNOS_CISRCFMT_ITU601_8BIT (1 << 31)
403 #define EXYNOS_CISRCFMT_ITU656_8BIT (0 << 31)
404 #define EXYNOS_CISRCFMT_ITU601_16BIT (1 << 29)
405 #define EXYNOS_CISRCFMT_ORDER422_YCBYCR (0 << 14)
406 #define EXYNOS_CISRCFMT_ORDER422_YCRYCB (1 << 14)
407 #define EXYNOS_CISRCFMT_ORDER422_CBYCRY (2 << 14)
408 #define EXYNOS_CISRCFMT_ORDER422_CRYCBY (3 << 14)
409 /* ITU601 16bit only */
410 #define EXYNOS_CISRCFMT_ORDER422_Y4CBCRCBCR (0 << 14)
411 /* ITU601 16bit only */
412 #define EXYNOS_CISRCFMT_ORDER422_Y4CRCBCRCB (1 << 14)
414 /* Window offset register */
415 #define EXYNOS_CIWDOFST_WINOFSEN (1 << 31)
416 #define EXYNOS_CIWDOFST_CLROVFIY (1 << 30)
417 #define EXYNOS_CIWDOFST_CLROVRLB (1 << 29)
418 #define EXYNOS_CIWDOFST_WINHOROFST_MASK (0x7ff << 16)
419 #define EXYNOS_CIWDOFST_CLROVFICB (1 << 15)
420 #define EXYNOS_CIWDOFST_CLROVFICR (1 << 14)
421 #define EXYNOS_CIWDOFST_WINVEROFST_MASK (0xfff << 0)
423 /* Global control register */
424 #define EXYNOS_CIGCTRL_SWRST (1 << 31)
425 #define EXYNOS_CIGCTRL_CAMRST_A (1 << 30)
426 #define EXYNOS_CIGCTRL_SELCAM_ITU_B (0 << 29)
427 #define EXYNOS_CIGCTRL_SELCAM_ITU_A (1 << 29)
428 #define EXYNOS_CIGCTRL_SELCAM_ITU_MASK (1 << 29)
429 #define EXYNOS_CIGCTRL_TESTPATTERN_NORMAL (0 << 27)
430 #define EXYNOS_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27)
431 #define EXYNOS_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27)
432 #define EXYNOS_CIGCTRL_TESTPATTERN_VER_INC (3 << 27)
433 #define EXYNOS_CIGCTRL_TESTPATTERN_MASK (3 << 27)
434 #define EXYNOS_CIGCTRL_TESTPATTERN_SHIFT (27)
435 #define EXYNOS_CIGCTRL_INVPOLPCLK (1 << 26)
436 #define EXYNOS_CIGCTRL_INVPOLVSYNC (1 << 25)
437 #define EXYNOS_CIGCTRL_INVPOLHREF (1 << 24)
438 #define EXYNOS_CIGCTRL_IRQ_OVFEN (1 << 22)
439 #define EXYNOS_CIGCTRL_HREF_MASK (1 << 21)
440 #define EXYNOS_CIGCTRL_IRQ_EDGE (0 << 20)
441 #define EXYNOS_CIGCTRL_IRQ_LEVEL (1 << 20)
442 #define EXYNOS_CIGCTRL_IRQ_CLR (1 << 19)
443 #define EXYNOS_CIGCTRL_IRQ_END_DISABLE (1 << 18)
444 #define EXYNOS_CIGCTRL_IRQ_DISABLE (0 << 16)
445 #define EXYNOS_CIGCTRL_IRQ_ENABLE (1 << 16)
446 #define EXYNOS_CIGCTRL_SHADOW_DISABLE (1 << 12)
447 #define EXYNOS_CIGCTRL_CAM_JPEG (1 << 8)
448 #define EXYNOS_CIGCTRL_SELCAM_MIPI_B (0 << 7)
449 #define EXYNOS_CIGCTRL_SELCAM_MIPI_A (1 << 7)
450 #define EXYNOS_CIGCTRL_SELCAM_MIPI_MASK (1 << 7)
451 #define EXYNOS_CIGCTRL_SELWB_CAMIF_CAMERA (0 << 6)
452 #define EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK (1 << 6)
453 #define EXYNOS_CIGCTRL_SELWRITEBACK_MASK (1 << 10)
454 #define EXYNOS_CIGCTRL_SELWRITEBACK_A (1 << 10)
455 #define EXYNOS_CIGCTRL_SELWRITEBACK_B (0 << 10)
456 #define EXYNOS_CIGCTRL_SELWB_CAMIF_MASK (1 << 6)
457 #define EXYNOS_CIGCTRL_CSC_ITU601 (0 << 5)
458 #define EXYNOS_CIGCTRL_CSC_ITU709 (1 << 5)
459 #define EXYNOS_CIGCTRL_CSC_MASK (1 << 5)
460 #define EXYNOS_CIGCTRL_INVPOLHSYNC (1 << 4)
461 #define EXYNOS_CIGCTRL_SELCAM_FIMC_ITU (0 << 3)
462 #define EXYNOS_CIGCTRL_SELCAM_FIMC_MIPI (1 << 3)
463 #define EXYNOS_CIGCTRL_SELCAM_FIMC_MASK (1 << 3)
464 #define EXYNOS_CIGCTRL_PROGRESSIVE (0 << 0)
465 #define EXYNOS_CIGCTRL_INTERLACE (1 << 0)
467 /* Window offset2 register */
468 #define EXYNOS_CIWDOFST_WINHOROFST2_MASK (0xfff << 16)
469 #define EXYNOS_CIWDOFST_WINVEROFST2_MASK (0xfff << 16)
471 /* Target format register */
472 #define EXYNOS_CITRGFMT_INROT90_CLOCKWISE (1 << 31)
473 #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29)
474 #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29)
475 #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE (2 << 29)
476 #define EXYNOS_CITRGFMT_OUTFORMAT_RGB (3 << 29)
477 #define EXYNOS_CITRGFMT_OUTFORMAT_MASK (3 << 29)
478 #define EXYNOS_CITRGFMT_FLIP_SHIFT (14)
479 #define EXYNOS_CITRGFMT_FLIP_NORMAL (0 << 14)
480 #define EXYNOS_CITRGFMT_FLIP_X_MIRROR (1 << 14)
481 #define EXYNOS_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
482 #define EXYNOS_CITRGFMT_FLIP_180 (3 << 14)
483 #define EXYNOS_CITRGFMT_FLIP_MASK (3 << 14)
484 #define EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE (1 << 13)
485 #define EXYNOS_CITRGFMT_TARGETV_MASK (0x1fff << 0)
486 #define EXYNOS_CITRGFMT_TARGETH_MASK (0x1fff << 16)
488 /* Output DMA control register */
489 #define EXYNOS_CIOCTRL_WEAVE_OUT (1 << 31)
490 #define EXYNOS_CIOCTRL_WEAVE_MASK (1 << 31)
491 #define EXYNOS_CIOCTRL_LASTENDEN (1 << 30)
492 #define EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR (0 << 24)
493 #define EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB (1 << 24)
494 #define EXYNOS_CIOCTRL_ORDER2P_MSB_CRCB (2 << 24)
495 #define EXYNOS_CIOCTRL_ORDER2P_MSB_CBCR (3 << 24)
496 #define EXYNOS_CIOCTRL_ORDER2P_SHIFT (24)
497 #define EXYNOS_CIOCTRL_ORDER2P_MASK (3 << 24)
498 #define EXYNOS_CIOCTRL_YCBCR_3PLANE (0 << 3)
499 #define EXYNOS_CIOCTRL_YCBCR_2PLANE (1 << 3)
500 #define EXYNOS_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
501 #define EXYNOS_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
502 #define EXYNOS_CIOCTRL_ALPHA_OUT (0xff << 4)
503 #define EXYNOS_CIOCTRL_ORDER422_YCBYCR (0 << 0)
504 #define EXYNOS_CIOCTRL_ORDER422_YCRYCB (1 << 0)
505 #define EXYNOS_CIOCTRL_ORDER422_CBYCRY (2 << 0)
506 #define EXYNOS_CIOCTRL_ORDER422_CRYCBY (3 << 0)
507 #define EXYNOS_CIOCTRL_ORDER422_MASK (3 << 0)
509 /* Main scaler control register */
510 #define EXYNOS_CISCCTRL_SCALERBYPASS (1 << 31)
511 #define EXYNOS_CISCCTRL_SCALEUP_H (1 << 30)
512 #define EXYNOS_CISCCTRL_SCALEUP_V (1 << 29)
513 #define EXYNOS_CISCCTRL_CSCR2Y_NARROW (0 << 28)
514 #define EXYNOS_CISCCTRL_CSCR2Y_WIDE (1 << 28)
515 #define EXYNOS_CISCCTRL_CSCY2R_NARROW (0 << 27)
516 #define EXYNOS_CISCCTRL_CSCY2R_WIDE (1 << 27)
517 #define EXYNOS_CISCCTRL_LCDPATHEN_FIFO (1 << 26)
518 #define EXYNOS_CISCCTRL_PROGRESSIVE (0 << 25)
519 #define EXYNOS_CISCCTRL_INTERLACE (1 << 25)
520 #define EXYNOS_CISCCTRL_SCAN_MASK (1 << 25)
521 #define EXYNOS_CISCCTRL_SCALERSTART (1 << 15)
522 #define EXYNOS_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
523 #define EXYNOS_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
524 #define EXYNOS_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
525 #define EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK (3 << 13)
526 #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
527 #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
528 #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
529 #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK (3 << 11)
530 #define EXYNOS_CISCCTRL_EXTRGB_NORMAL (0 << 10)
531 #define EXYNOS_CISCCTRL_EXTRGB_EXTENSION (1 << 10)
532 #define EXYNOS_CISCCTRL_ONE2ONE (1 << 9)
533 #define EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK (0x1ff << 0)
534 #define EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK (0x1ff << 16)
536 /* Status register */
537 #define EXYNOS_CISTATUS_OVFIY (1 << 31)
538 #define EXYNOS_CISTATUS_OVFICB (1 << 30)
539 #define EXYNOS_CISTATUS_OVFICR (1 << 29)
540 #define EXYNOS_CISTATUS_VSYNC (1 << 28)
541 #define EXYNOS_CISTATUS_SCALERSTART (1 << 26)
542 #define EXYNOS_CISTATUS_WINOFSTEN (1 << 25)
543 #define EXYNOS_CISTATUS_IMGCPTEN (1 << 22)
544 #define EXYNOS_CISTATUS_IMGCPTENSC (1 << 21)
545 #define EXYNOS_CISTATUS_VSYNC_A (1 << 20)
546 #define EXYNOS_CISTATUS_VSYNC_B (1 << 19)
547 #define EXYNOS_CISTATUS_OVRLB (1 << 18)
548 #define EXYNOS_CISTATUS_FRAMEEND (1 << 17)
549 #define EXYNOS_CISTATUS_LASTCAPTUREEND (1 << 16)
550 #define EXYNOS_CISTATUS_VVALID_A (1 << 15)
551 #define EXYNOS_CISTATUS_VVALID_B (1 << 14)
553 /* Image capture enable register */
554 #define EXYNOS_CIIMGCPT_IMGCPTEN (1 << 31)
555 #define EXYNOS_CIIMGCPT_IMGCPTEN_SC (1 << 30)
556 #define EXYNOS_CIIMGCPT_CPT_FREN_ENABLE (1 << 25)
557 #define EXYNOS_CIIMGCPT_CPT_FRMOD_EN (0 << 18)
558 #define EXYNOS_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
560 /* Image effects register */
561 #define EXYNOS_CIIMGEFF_IE_DISABLE (0 << 30)
562 #define EXYNOS_CIIMGEFF_IE_ENABLE (1 << 30)
563 #define EXYNOS_CIIMGEFF_IE_SC_BEFORE (0 << 29)
564 #define EXYNOS_CIIMGEFF_IE_SC_AFTER (1 << 29)
565 #define EXYNOS_CIIMGEFF_FIN_BYPASS (0 << 26)
566 #define EXYNOS_CIIMGEFF_FIN_ARBITRARY (1 << 26)
567 #define EXYNOS_CIIMGEFF_FIN_NEGATIVE (2 << 26)
568 #define EXYNOS_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
569 #define EXYNOS_CIIMGEFF_FIN_EMBOSSING (4 << 26)
570 #define EXYNOS_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
571 #define EXYNOS_CIIMGEFF_FIN_MASK (7 << 26)
572 #define EXYNOS_CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | (0xff << 0))
574 /* Real input DMA size register */
575 #define EXYNOS_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31)
576 #define EXYNOS_CIREAL_ISIZE_ADDR_CH_DISABLE (1 << 30)
577 #define EXYNOS_CIREAL_ISIZE_HEIGHT_MASK (0x3FFF << 16)
578 #define EXYNOS_CIREAL_ISIZE_WIDTH_MASK (0x3FFF << 0)
580 /* Input DMA control register */
581 #define EXYNOS_MSCTRL_FIELD_MASK (1 << 31)
582 #define EXYNOS_MSCTRL_FIELD_WEAVE (1 << 31)
583 #define EXYNOS_MSCTRL_FIELD_NORMAL (0 << 31)
584 #define EXYNOS_MSCTRL_BURST_CNT (24)
585 #define EXYNOS_MSCTRL_BURST_CNT_MASK (0xf << 24)
586 #define EXYNOS_MSCTRL_ORDER2P_LSB_CBCR (0 << 16)
587 #define EXYNOS_MSCTRL_ORDER2P_LSB_CRCB (1 << 16)
588 #define EXYNOS_MSCTRL_ORDER2P_MSB_CRCB (2 << 16)
589 #define EXYNOS_MSCTRL_ORDER2P_MSB_CBCR (3 << 16)
590 #define EXYNOS_MSCTRL_ORDER2P_SHIFT (16)
591 #define EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK (0x3 << 16)
592 #define EXYNOS_MSCTRL_C_INT_IN_3PLANE (0 << 15)
593 #define EXYNOS_MSCTRL_C_INT_IN_2PLANE (1 << 15)
594 #define EXYNOS_MSCTRL_FLIP_SHIFT (13)
595 #define EXYNOS_MSCTRL_FLIP_NORMAL (0 << 13)
596 #define EXYNOS_MSCTRL_FLIP_X_MIRROR (1 << 13)
597 #define EXYNOS_MSCTRL_FLIP_Y_MIRROR (2 << 13)
598 #define EXYNOS_MSCTRL_FLIP_180 (3 << 13)
599 #define EXYNOS_MSCTRL_FLIP_MASK (3 << 13)
600 #define EXYNOS_MSCTRL_ORDER422_CRYCBY (0 << 4)
601 #define EXYNOS_MSCTRL_ORDER422_YCRYCB (1 << 4)
602 #define EXYNOS_MSCTRL_ORDER422_CBYCRY (2 << 4)
603 #define EXYNOS_MSCTRL_ORDER422_YCBYCR (3 << 4)
604 #define EXYNOS_MSCTRL_INPUT_EXTCAM (0 << 3)
605 #define EXYNOS_MSCTRL_INPUT_MEMORY (1 << 3)
606 #define EXYNOS_MSCTRL_INPUT_MASK (1 << 3)
607 #define EXYNOS_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
608 #define EXYNOS_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
609 #define EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE (2 << 1)
610 #define EXYNOS_MSCTRL_INFORMAT_RGB (3 << 1)
611 #define EXYNOS_MSCTRL_ENVID (1 << 0)
613 /* DMA parameter register */
614 #define EXYNOS_CIDMAPARAM_R_MODE_LINEAR (0 << 29)
615 #define EXYNOS_CIDMAPARAM_R_MODE_CONFTILE (1 << 29)
616 #define EXYNOS_CIDMAPARAM_R_MODE_16X16 (2 << 29)
617 #define EXYNOS_CIDMAPARAM_R_MODE_64X32 (3 << 29)
618 #define EXYNOS_CIDMAPARAM_R_MODE_MASK (3 << 29)
619 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_64 (0 << 24)
620 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_128 (1 << 24)
621 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_256 (2 << 24)
622 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_512 (3 << 24)
623 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24)
624 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_2048 (5 << 24)
625 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_4096 (6 << 24)
626 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_1 (0 << 20)
627 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_2 (1 << 20)
628 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_4 (2 << 20)
629 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_8 (3 << 20)
630 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_16 (4 << 20)
631 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_32 (5 << 20)
632 #define EXYNOS_CIDMAPARAM_W_MODE_LINEAR (0 << 13)
633 #define EXYNOS_CIDMAPARAM_W_MODE_CONFTILE (1 << 13)
634 #define EXYNOS_CIDMAPARAM_W_MODE_16X16 (2 << 13)
635 #define EXYNOS_CIDMAPARAM_W_MODE_64X32 (3 << 13)
636 #define EXYNOS_CIDMAPARAM_W_MODE_MASK (3 << 13)
637 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_64 (0 << 8)
638 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_128 (1 << 8)
639 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_256 (2 << 8)
640 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_512 (3 << 8)
641 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8)
642 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_2048 (5 << 8)
643 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_4096 (6 << 8)
644 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_1 (0 << 4)
645 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_2 (1 << 4)
646 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_4 (2 << 4)
647 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_8 (3 << 4)
648 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_16 (4 << 4)
649 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_32 (5 << 4)
651 /* Gathering Extension register */
652 #define EXYNOS_CIEXTEN_TARGETH_EXT_MASK (1 << 26)
653 #define EXYNOS_CIEXTEN_TARGETV_EXT_MASK (1 << 24)
654 #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK (0x3F << 10)
655 #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK (0x3F)
656 #define EXYNOS_CIEXTEN_YUV444_OUT (1 << 22)
658 /* FIMC Clock Source Select register */
659 #define EXYNOS_CLKSRC_HCLK (0 << 1)
660 #define EXYNOS_CLKSRC_HCLK_MASK (1 << 1)
661 #define EXYNOS_CLKSRC_SCLK (1 << 1)
663 /* SYSREG for FIMC writeback */
664 #define SYSREG_CAMERA_BLK (0x0218)
665 #define SYSREG_FIMD0WB_DEST_MASK (0x3 << 23)
666 #define SYSREG_FIMD0WB_DEST_SHIFT 23