drivers/ide/serverworks.c

   1 /*
   2  * Copyright (C) 1998-2000 Michel Aubry
   3  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   4  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
   6  * Portions copyright (c) 2001 Sun Microsystems
   7  *
   8  *
   9  * RCC/ServerWorks IDE driver for Linux
  10  *
  11  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  12  *         supports UDMA mode 2 (33 MB/s)
  13  *
  14  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  15  *         all revisions support UDMA mode 4 (66 MB/s)
  16  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  17  *
  18  *         *** The CSB5 does not provide ANY register ***
  19  *         *** to detect 80-conductor cable presence. ***
  20  *
  21  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  22  *
  23  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  24  *   controller same as the CSB6. Single channel ATA100 only.
  25  *
  26  * Documentation:
  27  *      Available under NDA only. Errata info very hard to get.
  28  *
  29  */
  30
  31 #include <linux/types.h>
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/pci.h>
  35 #include <linux/ide.h>
  36 #include <linux/init.h>
  37
  38 #include <asm/io.h>
  39
  40 #define DRV_NAME "serverworks"
  41
  42 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  43 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  44
  45 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  46  * can overrun their FIFOs when used with the CSB5 */
  47 static const char *svwks_bad_ata100[] = {
  48         "ST320011A",
  49         "ST340016A",
  50         "ST360021A",
  51         "ST380021A",
  52         NULL
  53 };
  54
  55 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  56 {
  57         char *m = (char *)&drive->id[ATA_ID_PROD];
  58
  59         while (*list)
  60                 if (!strcmp(*list++, m))
  61                         return 1;
  62         return 0;
  63 }
  64
  65 static u8 svwks_udma_filter(ide_drive_t *drive)
  66 {
  67         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  68
  69         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
  70                 return 0x1f;
  71         } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
  72                 return 0x07;
  73         } else {
  74                 u8 btr = 0, mode, mask;
  75
  76                 pci_read_config_byte(dev, 0x5A, &btr);
  77                 mode = btr & 0x3;
  78
  79                 /* If someone decides to do UDMA133 on CSB5 the same
  80                    issue will bite so be inclusive */
  81                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
  82                         mode = 2;
  83
  84                 switch(mode) {
  85                 case 3:  mask = 0x3f; break;
  86                 case 2:  mask = 0x1f; break;
  87                 case 1:  mask = 0x07; break;
  88                 default: mask = 0x00; break;
  89                 }
  90
  91                 return mask;
  92         }
  93 }
  94
  95 static u8 svwks_csb_check (struct pci_dev *dev)
  96 {
  97         switch (dev->device) {
  98                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
  99                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 100                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 101                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 102                         return 1;
 103                 default:
 104                         break;
 105         }
 106         return 0;
 107 }
 108
 109 static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 110 {
 111         static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 112         static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
 113
 114         struct pci_dev *dev = to_pci_dev(hwif->dev);
 115         const u8 pio = drive->pio_mode - XFER_PIO_0;
 116
 117         if (drive->dn >= ARRAY_SIZE(drive_pci))
 118                 return;
 119
 120         pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
 121
 122         if (svwks_csb_check(dev)) {
 123                 u16 csb_pio = 0;
 124
 125                 pci_read_config_word(dev, 0x4a, &csb_pio);
 126
 127                 csb_pio &= ~(0x0f << (4 * drive->dn));
 128                 csb_pio |= (pio << (4 * drive->dn));
 129
 130                 pci_write_config_word(dev, 0x4a, csb_pio);
 131         }
 132 }
 133
 134 static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 135 {
 136         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 137         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 138         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 139
 140         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 141         const u8 speed          = drive->dma_mode;
 142         u8 unit                 = drive->dn & 1;
 143
 144         u8 ultra_enable  = 0, ultra_timing = 0, dma_timing = 0;
 145
 146         if (drive->dn >= ARRAY_SIZE(drive_pci2))
 147                 return;
 148
 149         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 150         pci_read_config_byte(dev, 0x54, &ultra_enable);
 151
 152         ultra_timing    &= ~(0x0F << (4*unit));
 153         ultra_enable    &= ~(0x01 << drive->dn);
 154
 155         if (speed >= XFER_UDMA_0) {
 156                 dma_timing   |= dma_modes[2];
 157                 ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
 158                 ultra_enable |= (0x01 << drive->dn);
 159         } else if (speed >= XFER_MW_DMA_0)
 160                 dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];
 161
 162         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 163         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 164         pci_write_config_byte(dev, 0x54, ultra_enable);
 165 }
 166
 167 static int init_chipset_svwks(struct pci_dev *dev)
 168 {
 169         unsigned int reg;
 170         u8 btr;
 171
 172         /* force Master Latency Timer value to 64 PCICLKs */
 173         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 174
 175         /* OSB4 : South Bridge and IDE */
 176         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 177                 struct pci_dev *isa_dev =
 178                         pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 179                                         PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 180                 if (isa_dev) {
 181                         pci_read_config_dword(isa_dev, 0x64, &reg);
 182                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 183                         if(!(reg & 0x00004000))
 184                                 printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
 185                                         "enabled.\n", pci_name(dev));
 186                         reg |=  0x00004000; /* enable UDMA/33 support */
 187                         pci_write_config_dword(isa_dev, 0x64, reg);
 188                         pci_dev_put(isa_dev);
 189                 }
 190         }
 191
 192         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 193         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 194                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 195                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 196
 197                 /* Third Channel Test */
 198                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 199                         struct pci_dev * findev = NULL;
 200                         u32 reg4c = 0;
 201                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 202                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 203                         if (findev) {
 204                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 205                                 reg4c &= ~0x000007FF;
 206                                 reg4c |=  0x00000040;
 207                                 reg4c |=  0x00000020;
 208                                 pci_write_config_dword(findev, 0x4C, reg4c);
 209                                 pci_dev_put(findev);
 210                         }
 211                         outb_p(0x06, 0x0c00);
 212                         dev->irq = inb_p(0x0c01);
 213                 } else {
 214                         struct pci_dev * findev = NULL;
 215                         u8 reg41 = 0;
 216
 217                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 218                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 219                         if (findev) {
 220                                 pci_read_config_byte(findev, 0x41, &reg41);
 221                                 reg41 &= ~0x40;
 222                                 pci_write_config_byte(findev, 0x41, reg41);
 223                                 pci_dev_put(findev);
 224                         }
 225                         /*
 226                          * This is a device pin issue on CSB6.
 227                          * Since there will be a future raid mode,
 228                          * early versions of the chipset require the
 229                          * interrupt pin to be set, and it is a compatibility
 230                          * mode issue.
 231                          */
 232                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 233                                 dev->irq = 0;
 234                 }
 235 //              pci_read_config_dword(dev, 0x40, &pioreg)
 236 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 237 //              pci_read_config_dword(dev, 0x44, &dmareg);
 238 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 239                 /* setup the UDMA Control register
 240                  *
 241                  * 1. clear bit 6 to enable DMA
 242                  * 2. enable DMA modes with bits 0-1
 243                  *      00 : legacy
 244                  *      01 : udma2
 245                  *      10 : udma2/udma4
 246                  *      11 : udma2/udma4/udma5
 247                  */
 248                 pci_read_config_byte(dev, 0x5A, &btr);
 249                 btr &= ~0x40;
 250                 if (!(PCI_FUNC(dev->devfn) & 1))
 251                         btr |= 0x2;
 252                 else
 253                         btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 254                 pci_write_config_byte(dev, 0x5A, btr);
 255         }
 256         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 257         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 258                 pci_read_config_byte(dev, 0x5A, &btr);
 259                 btr &= ~0x40;
 260                 btr |= 0x3;
 261                 pci_write_config_byte(dev, 0x5A, btr);
 262         }
 263
 264         return 0;
 265 }
 266
 267 static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
 268 {
 269         return ATA_CBL_PATA80;
 270 }
 271
 272 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 273  * of the subsystem device ID indicate presence of an 80-pin cable.
 274  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 275  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 276  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 277  * Bit 14 set   = primary IDE channel has 80-pin cable.
 278  */
 279 static u8 ata66_svwks_dell(ide_hwif_t *hwif)
 280 {
 281         struct pci_dev *dev = to_pci_dev(hwif->dev);
 282
 283         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 284             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 285             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 286              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 287                 return ((1 << (hwif->channel + 14)) &
 288                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 289         return ATA_CBL_PATA40;
 290 }
 291
 292 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 293  * detect issue by attaching the drives directly to the board.
 294  * This check follows the Dell precedent (how scary is that?!)
 295  *
 296  * WARNING: this only works on Alpine hardware!
 297  */
 298 static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
 299 {
 300         struct pci_dev *dev = to_pci_dev(hwif->dev);
 301
 302         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 303             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 304             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 305                 return ((1 << (hwif->channel + 14)) &
 306                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 307         return ATA_CBL_PATA40;
 308 }
 309
 310 static u8 svwks_cable_detect(ide_hwif_t *hwif)
 311 {
 312         struct pci_dev *dev = to_pci_dev(hwif->dev);
 313
 314         /* Server Works */
 315         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 316                 return ata66_svwks_svwks (hwif);
 317
 318         /* Dell PowerEdge */
 319         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 320                 return ata66_svwks_dell (hwif);
 321
 322         /* Cobalt Alpine */
 323         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 324                 return ata66_svwks_cobalt (hwif);
 325
 326         /* Per Specified Design by OEM, and ASIC Architect */
 327         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 328             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 329                 return ATA_CBL_PATA80;
 330
 331         return ATA_CBL_PATA40;
 332 }
 333
 334 static const struct ide_port_ops osb4_port_ops = {
 335         .set_pio_mode           = svwks_set_pio_mode,
 336         .set_dma_mode           = svwks_set_dma_mode,
 337 };
 338
 339 static const struct ide_port_ops svwks_port_ops = {
 340         .set_pio_mode           = svwks_set_pio_mode,
 341         .set_dma_mode           = svwks_set_dma_mode,
 342         .udma_filter            = svwks_udma_filter,
 343         .cable_detect           = svwks_cable_detect,
 344 };
 345
 346 static const struct ide_port_info serverworks_chipsets[] = {
 347         {       /* 0: OSB4 */
 348                 .name           = DRV_NAME,
 349                 .init_chipset   = init_chipset_svwks,
 350                 .port_ops       = &osb4_port_ops,
 351                 .pio_mask       = ATA_PIO4,
 352                 .mwdma_mask     = ATA_MWDMA2,
 353                 .udma_mask      = 0x00, /* UDMA is problematic on OSB4 */
 354         },
 355         {       /* 1: CSB5 */
 356                 .name           = DRV_NAME,
 357                 .init_chipset   = init_chipset_svwks,
 358                 .port_ops       = &svwks_port_ops,
 359                 .pio_mask       = ATA_PIO4,
 360                 .mwdma_mask     = ATA_MWDMA2,
 361                 .udma_mask      = ATA_UDMA5,
 362         },
 363         {       /* 2: CSB6 */
 364                 .name           = DRV_NAME,
 365                 .init_chipset   = init_chipset_svwks,
 366                 .port_ops       = &svwks_port_ops,
 367                 .pio_mask       = ATA_PIO4,
 368                 .mwdma_mask     = ATA_MWDMA2,
 369                 .udma_mask      = ATA_UDMA5,
 370         },
 371         {       /* 3: CSB6-2 */
 372                 .name           = DRV_NAME,
 373                 .init_chipset   = init_chipset_svwks,
 374                 .port_ops       = &svwks_port_ops,
 375                 .host_flags     = IDE_HFLAG_SINGLE,
 376                 .pio_mask       = ATA_PIO4,
 377                 .mwdma_mask     = ATA_MWDMA2,
 378                 .udma_mask      = ATA_UDMA5,
 379         },
 380         {       /* 4: HT1000 */
 381                 .name           = DRV_NAME,
 382                 .init_chipset   = init_chipset_svwks,
 383                 .port_ops       = &svwks_port_ops,
 384                 .host_flags     = IDE_HFLAG_SINGLE,
 385                 .pio_mask       = ATA_PIO4,
 386                 .mwdma_mask     = ATA_MWDMA2,
 387                 .udma_mask      = ATA_UDMA5,
 388         }
 389 };
 390
 391 /**
 392  *      svwks_init_one  -       called when a OSB/CSB is found
 393  *      @dev: the svwks device
 394  *      @id: the matching pci id
 395  *
 396  *      Called when the PCI registration layer (or the IDE initialization)
 397  *      finds a device matching our IDE device tables.
 398  */
 399
 400 static int svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 401 {
 402         struct ide_port_info d;
 403         u8 idx = id->driver_data;
 404
 405         d = serverworks_chipsets[idx];
 406
 407         if (idx == 1)
 408                 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
 409         else if (idx == 2 || idx == 3) {
 410                 if ((PCI_FUNC(dev->devfn) & 1) == 0) {
 411                         if (pci_resource_start(dev, 0) != 0x01f1)
 412                                 d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
 413                         d.host_flags |= IDE_HFLAG_SINGLE;
 414                 } else
 415                         d.host_flags &= ~IDE_HFLAG_SINGLE;
 416         }
 417
 418         return ide_pci_init_one(dev, &d, NULL);
 419 }
 420
 421 static const struct pci_device_id svwks_pci_tbl[] = {
 422         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
 423         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
 424         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
 425         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
 426         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
 427         { 0, },
 428 };
 429 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 430
 431 static struct pci_driver svwks_pci_driver = {
 432         .name           = "Serverworks_IDE",
 433         .id_table       = svwks_pci_tbl,
 434         .probe          = svwks_init_one,
 435         .remove         = ide_pci_remove,
 436         .suspend        = ide_pci_suspend,
 437         .resume         = ide_pci_resume,
 438 };
 439
 440 static int __init svwks_ide_init(void)
 441 {
 442         return ide_pci_register_driver(&svwks_pci_driver);
 443 }
 444
 445 static void __exit svwks_ide_exit(void)
 446 {
 447         pci_unregister_driver(&svwks_pci_driver);
 448 }
 449
 450 module_init(svwks_ide_init);
 451 module_exit(svwks_ide_exit);
 452
 453 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
 454 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 455 MODULE_LICENSE("GPL");