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Linux 4.9.243
[linux/fpc-iii.git] / drivers / mtd / nand / fsl_ifc_nand.c
blobcf0fccb5908e7362e74028b8289498542ee65960
1 /*
2 * Freescale Integrated Flash Controller NAND driver
3 *
4 * Copyright 2011-2012 Freescale Semiconductor, Inc
5 *
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mtd/nand_ecc.h>
32 #include <linux/fsl_ifc.h>
33
34 #define ERR_BYTE 0xFF /* Value returned for read
35 bytes when read failed */
36 #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
37 for IFC NAND Machine */
38
39 struct fsl_ifc_ctrl;
40
41 /* mtd information per set */
42 struct fsl_ifc_mtd {
43 struct nand_chip chip;
44 struct fsl_ifc_ctrl *ctrl;
45
46 struct device *dev;
47 int bank; /* Chip select bank number */
48 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
49 u8 __iomem *vbase; /* Chip select base virtual address */
50 };
51
52 /* overview of the fsl ifc controller */
53 struct fsl_ifc_nand_ctrl {
54 struct nand_hw_control controller;
55 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
56
57 void __iomem *addr; /* Address of assigned IFC buffer */
58 unsigned int page; /* Last page written to / read from */
59 unsigned int read_bytes;/* Number of bytes read during command */
60 unsigned int column; /* Saved column from SEQIN */
61 unsigned int index; /* Pointer to next byte to 'read' */
62 unsigned int oob; /* Non zero if operating on OOB data */
63 unsigned int eccread; /* Non zero for a full-page ECC read */
64 unsigned int counter; /* counter for the initializations */
65 unsigned int max_bitflips; /* Saved during READ0 cmd */
66 };
67
68 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
69
70 /*
71 * Generic flash bbt descriptors
72 */
73 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
74 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
75
76 static struct nand_bbt_descr bbt_main_descr = {
77 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
78 NAND_BBT_2BIT | NAND_BBT_VERSION,
79 .offs = 2, /* 0 on 8-bit small page */
80 .len = 4,
81 .veroffs = 6,
82 .maxblocks = 4,
83 .pattern = bbt_pattern,
84 };
85
86 static struct nand_bbt_descr bbt_mirror_descr = {
87 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
88 NAND_BBT_2BIT | NAND_BBT_VERSION,
89 .offs = 2, /* 0 on 8-bit small page */
90 .len = 4,
91 .veroffs = 6,
92 .maxblocks = 4,
93 .pattern = mirror_pattern,
94 };
95
96 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
97 struct mtd_oob_region *oobregion)
98 {
99 struct nand_chip *chip = mtd_to_nand(mtd);
100
101 if (section)
102 return -ERANGE;
103
104 oobregion->offset = 8;
105 oobregion->length = chip->ecc.total;
106
107 return 0;
108 }
109
110 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
111 struct mtd_oob_region *oobregion)
112 {
113 struct nand_chip *chip = mtd_to_nand(mtd);
114
115 if (section > 1)
116 return -ERANGE;
117
118 if (mtd->writesize == 512 &&
119 !(chip->options & NAND_BUSWIDTH_16)) {
120 if (!section) {
121 oobregion->offset = 0;
122 oobregion->length = 5;
123 } else {
124 oobregion->offset = 6;
125 oobregion->length = 2;
126 }
127
128 return 0;
129 }
130
131 if (!section) {
132 oobregion->offset = 2;
133 oobregion->length = 6;
134 } else {
135 oobregion->offset = chip->ecc.total + 8;
136 oobregion->length = mtd->oobsize - oobregion->offset;
137 }
138
139 return 0;
140 }
141
142 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
143 .ecc = fsl_ifc_ooblayout_ecc,
144 .free = fsl_ifc_ooblayout_free,
145 };
146
147 /*
148 * Set up the IFC hardware block and page address fields, and the ifc nand
149 * structure addr field to point to the correct IFC buffer in memory
150 */
151 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
152 {
153 struct nand_chip *chip = mtd_to_nand(mtd);
154 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
155 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
156 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
157 int buf_num;
158
159 ifc_nand_ctrl->page = page_addr;
160 /* Program ROW0/COL0 */
161 ifc_out32(page_addr, &ifc->ifc_nand.row0);
162 ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
163
164 buf_num = page_addr & priv->bufnum_mask;
165
166 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
167 ifc_nand_ctrl->index = column;
168
169 /* for OOB data point to the second half of the buffer */
170 if (oob)
171 ifc_nand_ctrl->index += mtd->writesize;
172 }
173
174 static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
175 {
176 struct nand_chip *chip = mtd_to_nand(mtd);
177 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
178 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
179 u32 __iomem *mainarea = (u32 __iomem *)addr;
180 u8 __iomem *oob = addr + mtd->writesize;
181 struct mtd_oob_region oobregion = { };
182 int i, section = 0;
183
184 for (i = 0; i < mtd->writesize / 4; i++) {
185 if (__raw_readl(&mainarea[i]) != 0xffffffff)
186 return 0;
187 }
188
189 mtd_ooblayout_ecc(mtd, section++, &oobregion);
190 while (oobregion.length) {
191 for (i = 0; i < oobregion.length; i++) {
192 if (__raw_readb(&oob[oobregion.offset + i]) != 0xff)
193 return 0;
194 }
195
196 mtd_ooblayout_ecc(mtd, section++, &oobregion);
197 }
198
199 return 1;
200 }
201
202 /* returns nonzero if entire page is blank */
203 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
204 u32 eccstat, unsigned int bufnum)
205 {
206 return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
207 }
208
209 /*
210 * execute IFC NAND command and wait for it to complete
211 */
212 static void fsl_ifc_run_command(struct mtd_info *mtd)
213 {
214 struct nand_chip *chip = mtd_to_nand(mtd);
215 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
216 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
217 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
218 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
219 u32 eccstat;
220 int i;
221
222 /* set the chip select for NAND Transaction */
223 ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
224 &ifc->ifc_nand.nand_csel);
225
226 dev_vdbg(priv->dev,
227 "%s: fir0=%08x fcr0=%08x\n",
228 __func__,
229 ifc_in32(&ifc->ifc_nand.nand_fir0),
230 ifc_in32(&ifc->ifc_nand.nand_fcr0));
231
232 ctrl->nand_stat = 0;
233
234 /* start read/write seq */
235 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
236
237 /* wait for command complete flag or timeout */
238 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
239 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
240
241 /* ctrl->nand_stat will be updated from IRQ context */
242 if (!ctrl->nand_stat)
243 dev_err(priv->dev, "Controller is not responding\n");
244 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
245 dev_err(priv->dev, "NAND Flash Timeout Error\n");
246 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
247 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
248
249 nctrl->max_bitflips = 0;
250
251 if (nctrl->eccread) {
252 int errors;
253 int bufnum = nctrl->page & priv->bufnum_mask;
254 int sector_start = bufnum * chip->ecc.steps;
255 int sector_end = sector_start + chip->ecc.steps - 1;
256 __be32 *eccstat_regs;
257
258 eccstat_regs = ifc->ifc_nand.nand_eccstat;
259 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
260
261 for (i = sector_start; i <= sector_end; i++) {
262 if (i != sector_start && !(i % 4))
263 eccstat = ifc_in32(&eccstat_regs[i / 4]);
264
265 errors = check_read_ecc(mtd, ctrl, eccstat, i);
266
267 if (errors == 15) {
268 /*
269 * Uncorrectable error.
270 * OK only if the whole page is blank.
271 *
272 * We disable ECCER reporting due to...
273 * erratum IFC-A002770 -- so report it now if we
274 * see an uncorrectable error in ECCSTAT.
275 */
276 if (!is_blank(mtd, bufnum))
277 ctrl->nand_stat |=
278 IFC_NAND_EVTER_STAT_ECCER;
279 break;
280 }
281
282 mtd->ecc_stats.corrected += errors;
283 nctrl->max_bitflips = max_t(unsigned int,
284 nctrl->max_bitflips,
285 errors);
286 }
287
288 nctrl->eccread = 0;
289 }
290 }
291
292 static void fsl_ifc_do_read(struct nand_chip *chip,
293 int oob,
294 struct mtd_info *mtd)
295 {
296 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
297 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
298 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
299
300 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
301 if (mtd->writesize > 512) {
302 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
303 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
304 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
305 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
306 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
307 &ifc->ifc_nand.nand_fir0);
308 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
309
310 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
311 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
312 &ifc->ifc_nand.nand_fcr0);
313 } else {
314 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
315 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
316 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
317 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
318 &ifc->ifc_nand.nand_fir0);
319 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
320
321 if (oob)
322 ifc_out32(NAND_CMD_READOOB <<
323 IFC_NAND_FCR0_CMD0_SHIFT,
324 &ifc->ifc_nand.nand_fcr0);
325 else
326 ifc_out32(NAND_CMD_READ0 <<
327 IFC_NAND_FCR0_CMD0_SHIFT,
328 &ifc->ifc_nand.nand_fcr0);
329 }
330 }
331
332 /* cmdfunc send commands to the IFC NAND Machine */
333 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
334 int column, int page_addr) {
335 struct nand_chip *chip = mtd_to_nand(mtd);
336 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
337 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
338 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
339
340 /* clear the read buffer */
341 ifc_nand_ctrl->read_bytes = 0;
342 if (command != NAND_CMD_PAGEPROG)
343 ifc_nand_ctrl->index = 0;
344
345 switch (command) {
346 /* READ0 read the entire buffer to use hardware ECC. */
347 case NAND_CMD_READ0:
348 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
349 set_addr(mtd, 0, page_addr, 0);
350
351 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
352 ifc_nand_ctrl->index += column;
353
354 if (chip->ecc.mode == NAND_ECC_HW)
355 ifc_nand_ctrl->eccread = 1;
356
357 fsl_ifc_do_read(chip, 0, mtd);
358 fsl_ifc_run_command(mtd);
359 return;
360
361 /* READOOB reads only the OOB because no ECC is performed. */
362 case NAND_CMD_READOOB:
363 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
364 set_addr(mtd, column, page_addr, 1);
365
366 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
367
368 fsl_ifc_do_read(chip, 1, mtd);
369 fsl_ifc_run_command(mtd);
370
371 return;
372
373 case NAND_CMD_READID:
374 case NAND_CMD_PARAM: {
375 /*
376 * For READID, read 8 bytes that are currently used.
377 * For PARAM, read all 3 copies of 256-bytes pages.
378 */
379 int len = 8;
380 int timing = IFC_FIR_OP_RB;
381 if (command == NAND_CMD_PARAM) {
382 timing = IFC_FIR_OP_RBCD;
383 len = 256 * 3;
384 }
385
386 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
387 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
388 (timing << IFC_NAND_FIR0_OP2_SHIFT),
389 &ifc->ifc_nand.nand_fir0);
390 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
391 &ifc->ifc_nand.nand_fcr0);
392 ifc_out32(column, &ifc->ifc_nand.row3);
393
394 ifc_out32(len, &ifc->ifc_nand.nand_fbcr);
395 ifc_nand_ctrl->read_bytes = len;
396
397 set_addr(mtd, 0, 0, 0);
398 fsl_ifc_run_command(mtd);
399 return;
400 }
401
402 /* ERASE1 stores the block and page address */
403 case NAND_CMD_ERASE1:
404 set_addr(mtd, 0, page_addr, 0);
405 return;
406
407 /* ERASE2 uses the block and page address from ERASE1 */
408 case NAND_CMD_ERASE2:
409 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
410 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
411 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
412 &ifc->ifc_nand.nand_fir0);
413
414 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
415 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
416 &ifc->ifc_nand.nand_fcr0);
417
418 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
419 ifc_nand_ctrl->read_bytes = 0;
420 fsl_ifc_run_command(mtd);
421 return;
422
423 /* SEQIN sets up the addr buffer and all registers except the length */
424 case NAND_CMD_SEQIN: {
425 u32 nand_fcr0;
426 ifc_nand_ctrl->column = column;
427 ifc_nand_ctrl->oob = 0;
428
429 if (mtd->writesize > 512) {
430 nand_fcr0 =
431 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
432 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
433 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
434
435 ifc_out32(
436 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
437 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
438 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
439 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
440 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
441 &ifc->ifc_nand.nand_fir0);
442 ifc_out32(
443 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
444 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
445 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
446 &ifc->ifc_nand.nand_fir1);
447 } else {
448 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
449 IFC_NAND_FCR0_CMD1_SHIFT) |
450 (NAND_CMD_SEQIN <<
451 IFC_NAND_FCR0_CMD2_SHIFT) |
452 (NAND_CMD_STATUS <<
453 IFC_NAND_FCR0_CMD3_SHIFT));
454
455 ifc_out32(
456 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
457 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
458 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
459 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
460 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
461 &ifc->ifc_nand.nand_fir0);
462 ifc_out32(
463 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
464 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
465 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
466 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
467 &ifc->ifc_nand.nand_fir1);
468
469 if (column >= mtd->writesize)
470 nand_fcr0 |=
471 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
472 else
473 nand_fcr0 |=
474 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
475 }
476
477 if (column >= mtd->writesize) {
478 /* OOB area --> READOOB */
479 column -= mtd->writesize;
480 ifc_nand_ctrl->oob = 1;
481 }
482 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
483 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
484 return;
485 }
486
487 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
488 case NAND_CMD_PAGEPROG: {
489 if (ifc_nand_ctrl->oob) {
490 ifc_out32(ifc_nand_ctrl->index -
491 ifc_nand_ctrl->column,
492 &ifc->ifc_nand.nand_fbcr);
493 } else {
494 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
495 }
496
497 fsl_ifc_run_command(mtd);
498 return;
499 }
500
501 case NAND_CMD_STATUS: {
502 void __iomem *addr;
503
504 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
505 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
506 &ifc->ifc_nand.nand_fir0);
507 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
508 &ifc->ifc_nand.nand_fcr0);
509 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
510 set_addr(mtd, 0, 0, 0);
511 ifc_nand_ctrl->read_bytes = 1;
512
513 fsl_ifc_run_command(mtd);
514
515 /*
516 * The chip always seems to report that it is
517 * write-protected, even when it is not.
518 */
519 addr = ifc_nand_ctrl->addr;
520 if (chip->options & NAND_BUSWIDTH_16)
521 ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
522 else
523 ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
524 return;
525 }
526
527 case NAND_CMD_RESET:
528 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
529 &ifc->ifc_nand.nand_fir0);
530 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
531 &ifc->ifc_nand.nand_fcr0);
532 fsl_ifc_run_command(mtd);
533 return;
534
535 default:
536 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
537 __func__, command);
538 }
539 }
540
541 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
542 {
543 /* The hardware does not seem to support multiple
544 * chips per bank.
545 */
546 }
547
548 /*
549 * Write buf to the IFC NAND Controller Data Buffer
550 */
551 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
552 {
553 struct nand_chip *chip = mtd_to_nand(mtd);
554 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
555 unsigned int bufsize = mtd->writesize + mtd->oobsize;
556
557 if (len <= 0) {
558 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
559 return;
560 }
561
562 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
563 dev_err(priv->dev,
564 "%s: beyond end of buffer (%d requested, %u available)\n",
565 __func__, len, bufsize - ifc_nand_ctrl->index);
566 len = bufsize - ifc_nand_ctrl->index;
567 }
568
569 memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
570 ifc_nand_ctrl->index += len;
571 }
572
573 /*
574 * Read a byte from either the IFC hardware buffer
575 * read function for 8-bit buswidth
576 */
577 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
578 {
579 struct nand_chip *chip = mtd_to_nand(mtd);
580 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
581 unsigned int offset;
582
583 /*
584 * If there are still bytes in the IFC buffer, then use the
585 * next byte.
586 */
587 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
588 offset = ifc_nand_ctrl->index++;
589 return ifc_in8(ifc_nand_ctrl->addr + offset);
590 }
591
592 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
593 return ERR_BYTE;
594 }
595
596 /*
597 * Read two bytes from the IFC hardware buffer
598 * read function for 16-bit buswith
599 */
600 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
601 {
602 struct nand_chip *chip = mtd_to_nand(mtd);
603 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
604 uint16_t data;
605
606 /*
607 * If there are still bytes in the IFC buffer, then use the
608 * next byte.
609 */
610 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
611 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
612 ifc_nand_ctrl->index += 2;
613 return (uint8_t) data;
614 }
615
616 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
617 return ERR_BYTE;
618 }
619
620 /*
621 * Read from the IFC Controller Data Buffer
622 */
623 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
624 {
625 struct nand_chip *chip = mtd_to_nand(mtd);
626 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
627 int avail;
628
629 if (len < 0) {
630 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
631 return;
632 }
633
634 avail = min((unsigned int)len,
635 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
636 memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
637 ifc_nand_ctrl->index += avail;
638
639 if (len > avail)
640 dev_err(priv->dev,
641 "%s: beyond end of buffer (%d requested, %d available)\n",
642 __func__, len, avail);
643 }
644
645 /*
646 * This function is called after Program and Erase Operations to
647 * check for success or failure.
648 */
649 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
650 {
651 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
652 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
653 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
654 u32 nand_fsr;
655 int status;
656
657 /* Use READ_STATUS command, but wait for the device to be ready */
658 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
659 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
660 &ifc->ifc_nand.nand_fir0);
661 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
662 &ifc->ifc_nand.nand_fcr0);
663 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
664 set_addr(mtd, 0, 0, 0);
665 ifc_nand_ctrl->read_bytes = 1;
666
667 fsl_ifc_run_command(mtd);
668
669 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
670 status = nand_fsr >> 24;
671 /*
672 * The chip always seems to report that it is
673 * write-protected, even when it is not.
674 */
675 return status | NAND_STATUS_WP;
676 }
677
678 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
679 uint8_t *buf, int oob_required, int page)
680 {
681 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
682 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
683 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
684
685 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
686 if (oob_required)
687 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
688
689 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
690 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
691
692 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
693 mtd->ecc_stats.failed++;
694
695 return nctrl->max_bitflips;
696 }
697
698 /* ECC will be calculated automatically, and errors will be detected in
699 * waitfunc.
700 */
701 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
702 const uint8_t *buf, int oob_required, int page)
703 {
704 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
705 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
706
707 return 0;
708 }
709
710 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
711 {
712 struct nand_chip *chip = mtd_to_nand(mtd);
713 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
714
715 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
716 chip->numchips);
717 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
718 chip->chipsize);
719 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
720 chip->pagemask);
721 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
722 chip->chip_delay);
723 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
724 chip->badblockpos);
725 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
726 chip->chip_shift);
727 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
728 chip->page_shift);
729 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
730 chip->phys_erase_shift);
731 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
732 chip->ecc.mode);
733 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
734 chip->ecc.steps);
735 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
736 chip->ecc.bytes);
737 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
738 chip->ecc.total);
739 dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
740 mtd->ooblayout);
741 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
742 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
743 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
744 mtd->erasesize);
745 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
746 mtd->writesize);
747 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
748 mtd->oobsize);
749
750 return 0;
751 }
752
753 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
754 {
755 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
756 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
757 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
758 uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
759 uint32_t cs = priv->bank;
760
761 /* Save CSOR and CSOR_ext */
762 csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
763 csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
764
765 /* chage PageSize 8K and SpareSize 1K*/
766 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
767 ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
768 ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
769
770 /* READID */
771 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
772 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
773 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
774 &ifc_runtime->ifc_nand.nand_fir0);
775 ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
776 &ifc_runtime->ifc_nand.nand_fcr0);
777 ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
778
779 ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
780
781 /* Program ROW0/COL0 */
782 ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
783 ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
784
785 /* set the chip select for NAND Transaction */
786 ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
787 &ifc_runtime->ifc_nand.nand_csel);
788
789 /* start read seq */
790 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
791 &ifc_runtime->ifc_nand.nandseq_strt);
792
793 /* wait for command complete flag or timeout */
794 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
795 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
796
797 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
798 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
799
800 /* Restore CSOR and CSOR_ext */
801 ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
802 ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
803 }
804
805 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
806 {
807 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
808 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
809 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
810 struct nand_chip *chip = &priv->chip;
811 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
812 u32 csor;
813
814 /* Fill in fsl_ifc_mtd structure */
815 mtd->dev.parent = priv->dev;
816 nand_set_flash_node(chip, priv->dev->of_node);
817
818 /* fill in nand_chip structure */
819 /* set up function call table */
820 if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
821 & CSPR_PORT_SIZE_16)
822 chip->read_byte = fsl_ifc_read_byte16;
823 else
824 chip->read_byte = fsl_ifc_read_byte;
825
826 chip->write_buf = fsl_ifc_write_buf;
827 chip->read_buf = fsl_ifc_read_buf;
828 chip->select_chip = fsl_ifc_select_chip;
829 chip->cmdfunc = fsl_ifc_cmdfunc;
830 chip->waitfunc = fsl_ifc_wait;
831
832 chip->bbt_td = &bbt_main_descr;
833 chip->bbt_md = &bbt_mirror_descr;
834
835 ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
836
837 /* set up nand options */
838 chip->bbt_options = NAND_BBT_USE_FLASH;
839 chip->options = NAND_NO_SUBPAGE_WRITE;
840
841 if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
842 & CSPR_PORT_SIZE_16) {
843 chip->read_byte = fsl_ifc_read_byte16;
844 chip->options |= NAND_BUSWIDTH_16;
845 } else {
846 chip->read_byte = fsl_ifc_read_byte;
847 }
848
849 chip->controller = &ifc_nand_ctrl->controller;
850 nand_set_controller_data(chip, priv);
851
852 chip->ecc.read_page = fsl_ifc_read_page;
853 chip->ecc.write_page = fsl_ifc_write_page;
854
855 csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
856
857 switch (csor & CSOR_NAND_PGS_MASK) {
858 case CSOR_NAND_PGS_512:
859 if (!(chip->options & NAND_BUSWIDTH_16)) {
860 /* Avoid conflict with bad block marker */
861 bbt_main_descr.offs = 0;
862 bbt_mirror_descr.offs = 0;
863 }
864
865 priv->bufnum_mask = 15;
866 break;
867
868 case CSOR_NAND_PGS_2K:
869 priv->bufnum_mask = 3;
870 break;
871
872 case CSOR_NAND_PGS_4K:
873 priv->bufnum_mask = 1;
874 break;
875
876 case CSOR_NAND_PGS_8K:
877 priv->bufnum_mask = 0;
878 break;
879
880 default:
881 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
882 return -ENODEV;
883 }
884
885 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
886 if (csor & CSOR_NAND_ECC_DEC_EN) {
887 chip->ecc.mode = NAND_ECC_HW;
888 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
889
890 /* Hardware generates ECC per 512 Bytes */
891 chip->ecc.size = 512;
892 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
893 chip->ecc.bytes = 8;
894 chip->ecc.strength = 4;
895 } else {
896 chip->ecc.bytes = 16;
897 chip->ecc.strength = 8;
898 }
899 } else {
900 chip->ecc.mode = NAND_ECC_SOFT;
901 chip->ecc.algo = NAND_ECC_HAMMING;
902 }
903
904 if (ctrl->version == FSL_IFC_VERSION_1_1_0)
905 fsl_ifc_sram_init(priv);
906
907 /*
908 * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
909 * versions which had 8KB. Hence bufnum mask needs to be updated.
910 */
911 if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
912 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
913
914 return 0;
915 }
916
917 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
918 {
919 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
920
921 nand_release(&priv->chip);
922
923 kfree(mtd->name);
924
925 if (priv->vbase)
926 iounmap(priv->vbase);
927
928 ifc_nand_ctrl->chips[priv->bank] = NULL;
929
930 return 0;
931 }
932
933 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
934 phys_addr_t addr)
935 {
936 u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
937
938 if (!(cspr & CSPR_V))
939 return 0;
940 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
941 return 0;
942
943 return (cspr & CSPR_BA) == convert_ifc_address(addr);
944 }
945
946 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
947
948 static int fsl_ifc_nand_probe(struct platform_device *dev)
949 {
950 struct fsl_ifc_runtime __iomem *ifc;
951 struct fsl_ifc_mtd *priv;
952 struct resource res;
953 static const char *part_probe_types[]
954 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
955 int ret;
956 int bank;
957 struct device_node *node = dev->dev.of_node;
958 struct mtd_info *mtd;
959
960 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
961 return -ENODEV;
962 ifc = fsl_ifc_ctrl_dev->rregs;
963
964 /* get, allocate and map the memory resource */
965 ret = of_address_to_resource(node, 0, &res);
966 if (ret) {
967 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
968 return ret;
969 }
970
971 /* find which chip select it is connected to */
972 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
973 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
974 break;
975 }
976
977 if (bank >= fsl_ifc_ctrl_dev->banks) {
978 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
979 __func__);
980 return -ENODEV;
981 }
982
983 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
984 if (!priv)
985 return -ENOMEM;
986
987 mutex_lock(&fsl_ifc_nand_mutex);
988 if (!fsl_ifc_ctrl_dev->nand) {
989 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
990 if (!ifc_nand_ctrl) {
991 mutex_unlock(&fsl_ifc_nand_mutex);
992 return -ENOMEM;
993 }
994
995 ifc_nand_ctrl->read_bytes = 0;
996 ifc_nand_ctrl->index = 0;
997 ifc_nand_ctrl->addr = NULL;
998 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
999
1000 nand_hw_control_init(&ifc_nand_ctrl->controller);
1001 } else {
1002 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1003 }
1004 mutex_unlock(&fsl_ifc_nand_mutex);
1005
1006 ifc_nand_ctrl->chips[bank] = priv;
1007 priv->bank = bank;
1008 priv->ctrl = fsl_ifc_ctrl_dev;
1009 priv->dev = &dev->dev;
1010
1011 priv->vbase = ioremap(res.start, resource_size(&res));
1012 if (!priv->vbase) {
1013 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1014 ret = -ENOMEM;
1015 goto err;
1016 }
1017
1018 dev_set_drvdata(priv->dev, priv);
1019
1020 ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1021 IFC_NAND_EVTER_EN_FTOER_EN |
1022 IFC_NAND_EVTER_EN_WPER_EN,
1023 &ifc->ifc_nand.nand_evter_en);
1024
1025 /* enable NAND Machine Interrupts */
1026 ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1027 IFC_NAND_EVTER_INTR_FTOERIR_EN |
1028 IFC_NAND_EVTER_INTR_WPERIR_EN,
1029 &ifc->ifc_nand.nand_evter_intr_en);
1030
1031 mtd = nand_to_mtd(&priv->chip);
1032 mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1033 if (!mtd->name) {
1034 ret = -ENOMEM;
1035 goto err;
1036 }
1037
1038 ret = fsl_ifc_chip_init(priv);
1039 if (ret)
1040 goto err;
1041
1042 ret = nand_scan_ident(mtd, 1, NULL);
1043 if (ret)
1044 goto err;
1045
1046 ret = fsl_ifc_chip_init_tail(mtd);
1047 if (ret)
1048 goto err;
1049
1050 ret = nand_scan_tail(mtd);
1051 if (ret)
1052 goto err;
1053
1054 /* First look for RedBoot table or partitions on the command
1055 * line, these take precedence over device tree information */
1056 mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1057
1058 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1059 (unsigned long long)res.start, priv->bank);
1060 return 0;
1061
1062 err:
1063 fsl_ifc_chip_remove(priv);
1064 return ret;
1065 }
1066
1067 static int fsl_ifc_nand_remove(struct platform_device *dev)
1068 {
1069 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1070
1071 fsl_ifc_chip_remove(priv);
1072
1073 mutex_lock(&fsl_ifc_nand_mutex);
1074 ifc_nand_ctrl->counter--;
1075 if (!ifc_nand_ctrl->counter) {
1076 fsl_ifc_ctrl_dev->nand = NULL;
1077 kfree(ifc_nand_ctrl);
1078 }
1079 mutex_unlock(&fsl_ifc_nand_mutex);
1080
1081 return 0;
1082 }
1083
1084 static const struct of_device_id fsl_ifc_nand_match[] = {
1085 {
1086 .compatible = "fsl,ifc-nand",
1087 },
1088 {}
1089 };
1090 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1091
1092 static struct platform_driver fsl_ifc_nand_driver = {
1093 .driver = {
1094 .name = "fsl,ifc-nand",
1095 .of_match_table = fsl_ifc_nand_match,
1096 },
1097 .probe = fsl_ifc_nand_probe,
1098 .remove = fsl_ifc_nand_remove,
1099 };
1100
1101 module_platform_driver(fsl_ifc_nand_driver);
1102
1103 MODULE_LICENSE("GPL");
1104 MODULE_AUTHOR("Freescale");
1105 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
Linux with added FPC-III support