arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/sched.h>
  21 #include <linux/tty.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/bitops.h>
  26 #include <linux/time.h>
  27 #include <linux/timex.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30 #include <linux/io.h>
  31
  32 #include <mach/udc.h>
  33 #include <mach/hardware.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <asm/irq.h>
  38
  39 #include <asm/mach/map.h>
  40 #include <asm/mach/irq.h>
  41 #include <asm/mach/time.h>
  42
  43 static void __init ixp4xx_clocksource_init(void);
  44 static void __init ixp4xx_clockevent_init(void);
  45 static struct clock_event_device clockevent_ixp4xx;
  46
  47 /*************************************************************************
  48  * IXP4xx chipset I/O mapping
  49  *************************************************************************/
  50 static struct map_desc ixp4xx_io_desc[] __initdata = {
  51         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  52                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  53                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  54                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  55                 .type           = MT_DEVICE
  56         }, {    /* Expansion Bus Config Registers */
  57                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  58                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  59                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  60                 .type           = MT_DEVICE
  61         }, {    /* PCI Registers */
  62                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  63                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  64                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  65                 .type           = MT_DEVICE
  66         },
  67 #ifdef CONFIG_DEBUG_LL
  68         {       /* Debug UART mapping */
  69                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  70                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
  71                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  72                 .type           = MT_DEVICE
  73         }
  74 #endif
  75 };
  76
  77 void __init ixp4xx_map_io(void)
  78 {
  79         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  80 }
  81
  82
  83 /*************************************************************************
  84  * IXP4xx chipset IRQ handling
  85  *
  86  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  87  *       (be it PCI or something else) configures that GPIO line
  88  *       as an IRQ.
  89  **************************************************************************/
  90 enum ixp4xx_irq_type {
  91         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  92 };
  93
  94 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
  95 static unsigned long long ixp4xx_irq_edge = 0;
  96
  97 /*
  98  * IRQ -> GPIO mapping table
  99  */
 100 static signed char irq2gpio[32] = {
 101         -1, -1, -1, -1, -1, -1,  0,  1,
 102         -1, -1, -1, -1, -1, -1, -1, -1,
 103         -1, -1, -1,  2,  3,  4,  5,  6,
 104          7,  8,  9, 10, 11, 12, -1, -1,
 105 };
 106
 107 int gpio_to_irq(int gpio)
 108 {
 109         int irq;
 110
 111         for (irq = 0; irq < 32; irq++) {
 112                 if (irq2gpio[irq] == gpio)
 113                         return irq;
 114         }
 115         return -EINVAL;
 116 }
 117 EXPORT_SYMBOL(gpio_to_irq);
 118
 119 int irq_to_gpio(unsigned int irq)
 120 {
 121         int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
 122
 123         if (gpio == -1)
 124                 return -EINVAL;
 125
 126         return gpio;
 127 }
 128 EXPORT_SYMBOL(irq_to_gpio);
 129
 130 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 131 {
 132         int line = irq2gpio[irq];
 133         u32 int_style;
 134         enum ixp4xx_irq_type irq_type;
 135         volatile u32 *int_reg;
 136
 137         /*
 138          * Only for GPIO IRQs
 139          */
 140         if (line < 0)
 141                 return -EINVAL;
 142
 143         switch (type){
 144         case IRQ_TYPE_EDGE_BOTH:
 145                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 146                 irq_type = IXP4XX_IRQ_EDGE;
 147                 break;
 148         case IRQ_TYPE_EDGE_RISING:
 149                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 150                 irq_type = IXP4XX_IRQ_EDGE;
 151                 break;
 152         case IRQ_TYPE_EDGE_FALLING:
 153                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 154                 irq_type = IXP4XX_IRQ_EDGE;
 155                 break;
 156         case IRQ_TYPE_LEVEL_HIGH:
 157                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 158                 irq_type = IXP4XX_IRQ_LEVEL;
 159                 break;
 160         case IRQ_TYPE_LEVEL_LOW:
 161                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 162                 irq_type = IXP4XX_IRQ_LEVEL;
 163                 break;
 164         default:
 165                 return -EINVAL;
 166         }
 167
 168         if (irq_type == IXP4XX_IRQ_EDGE)
 169                 ixp4xx_irq_edge |= (1 << irq);
 170         else
 171                 ixp4xx_irq_edge &= ~(1 << irq);
 172
 173         if (line >= 8) {        /* pins 8-15 */
 174                 line -= 8;
 175                 int_reg = IXP4XX_GPIO_GPIT2R;
 176         } else {                /* pins 0-7 */
 177                 int_reg = IXP4XX_GPIO_GPIT1R;
 178         }
 179
 180         /* Clear the style for the appropriate pin */
 181         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 182                         (line * IXP4XX_GPIO_STYLE_SIZE));
 183
 184         *IXP4XX_GPIO_GPISR = (1 << line);
 185
 186         /* Set the new style */
 187         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 188
 189         /* Configure the line as an input */
 190         gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN);
 191
 192         return 0;
 193 }
 194
 195 static void ixp4xx_irq_mask(unsigned int irq)
 196 {
 197         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
 198                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
 199         else
 200                 *IXP4XX_ICMR &= ~(1 << irq);
 201 }
 202
 203 static void ixp4xx_irq_ack(unsigned int irq)
 204 {
 205         int line = (irq < 32) ? irq2gpio[irq] : -1;
 206
 207         if (line >= 0)
 208                 *IXP4XX_GPIO_GPISR = (1 << line);
 209 }
 210
 211 /*
 212  * Level triggered interrupts on GPIO lines can only be cleared when the
 213  * interrupt condition disappears.
 214  */
 215 static void ixp4xx_irq_unmask(unsigned int irq)
 216 {
 217         if (!(ixp4xx_irq_edge & (1 << irq)))
 218                 ixp4xx_irq_ack(irq);
 219
 220         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
 221                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
 222         else
 223                 *IXP4XX_ICMR |= (1 << irq);
 224 }
 225
 226 static struct irq_chip ixp4xx_irq_chip = {
 227         .name           = "IXP4xx",
 228         .ack            = ixp4xx_irq_ack,
 229         .mask           = ixp4xx_irq_mask,
 230         .unmask         = ixp4xx_irq_unmask,
 231         .set_type       = ixp4xx_set_irq_type,
 232 };
 233
 234 void __init ixp4xx_init_irq(void)
 235 {
 236         int i = 0;
 237
 238         /* Route all sources to IRQ instead of FIQ */
 239         *IXP4XX_ICLR = 0x0;
 240
 241         /* Disable all interrupt */
 242         *IXP4XX_ICMR = 0x0;
 243
 244         if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
 245                 /* Route upper 32 sources to IRQ instead of FIQ */
 246                 *IXP4XX_ICLR2 = 0x00;
 247
 248                 /* Disable upper 32 interrupts */
 249                 *IXP4XX_ICMR2 = 0x00;
 250         }
 251
 252         /* Default to all level triggered */
 253         for(i = 0; i < NR_IRQS; i++) {
 254                 set_irq_chip(i, &ixp4xx_irq_chip);
 255                 set_irq_handler(i, handle_level_irq);
 256                 set_irq_flags(i, IRQF_VALID);
 257         }
 258 }
 259
 260
 261 /*************************************************************************
 262  * IXP4xx timer tick
 263  * We use OS timer1 on the CPU for the timer tick and the timestamp
 264  * counter as a source of real clock ticks to account for missed jiffies.
 265  *************************************************************************/
 266
 267 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 268 {
 269         struct clock_event_device *evt = dev_id;
 270
 271         /* Clear Pending Interrupt by writing '1' to it */
 272         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 273
 274         evt->event_handler(evt);
 275
 276         return IRQ_HANDLED;
 277 }
 278
 279 static struct irqaction ixp4xx_timer_irq = {
 280         .name           = "timer1",
 281         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 282         .handler        = ixp4xx_timer_interrupt,
 283         .dev_id         = &clockevent_ixp4xx,
 284 };
 285
 286 void __init ixp4xx_timer_init(void)
 287 {
 288         /* Reset/disable counter */
 289         *IXP4XX_OSRT1 = 0;
 290
 291         /* Clear Pending Interrupt by writing '1' to it */
 292         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 293
 294         /* Reset time-stamp counter */
 295         *IXP4XX_OSTS = 0;
 296
 297         /* Connect the interrupt handler and enable the interrupt */
 298         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 299
 300         ixp4xx_clocksource_init();
 301         ixp4xx_clockevent_init();
 302 }
 303
 304 struct sys_timer ixp4xx_timer = {
 305         .init           = ixp4xx_timer_init,
 306 };
 307
 308 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 309
 310 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
 311 {
 312         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 313 }
 314
 315 static struct resource ixp4xx_udc_resources[] = {
 316         [0] = {
 317                 .start  = 0xc800b000,
 318                 .end    = 0xc800bfff,
 319                 .flags  = IORESOURCE_MEM,
 320         },
 321         [1] = {
 322                 .start  = IRQ_IXP4XX_USB,
 323                 .end    = IRQ_IXP4XX_USB,
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 /*
 329  * USB device controller. The IXP4xx uses the same controller as PXA25X,
 330  * so we just use the same device.
 331  */
 332 static struct platform_device ixp4xx_udc_device = {
 333         .name           = "pxa25x-udc",
 334         .id             = -1,
 335         .num_resources  = 2,
 336         .resource       = ixp4xx_udc_resources,
 337         .dev            = {
 338                 .platform_data = &ixp4xx_udc_info,
 339         },
 340 };
 341
 342 static struct platform_device *ixp4xx_devices[] __initdata = {
 343         &ixp4xx_udc_device,
 344 };
 345
 346 static struct resource ixp46x_i2c_resources[] = {
 347         [0] = {
 348                 .start  = 0xc8011000,
 349                 .end    = 0xc801101c,
 350                 .flags  = IORESOURCE_MEM,
 351         },
 352         [1] = {
 353                 .start  = IRQ_IXP4XX_I2C,
 354                 .end    = IRQ_IXP4XX_I2C,
 355                 .flags  = IORESOURCE_IRQ
 356         }
 357 };
 358
 359 /*
 360  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 361  * we just use the same device name.
 362  */
 363 static struct platform_device ixp46x_i2c_controller = {
 364         .name           = "IOP3xx-I2C",
 365         .id             = 0,
 366         .num_resources  = 2,
 367         .resource       = ixp46x_i2c_resources
 368 };
 369
 370 static struct platform_device *ixp46x_devices[] __initdata = {
 371         &ixp46x_i2c_controller
 372 };
 373
 374 unsigned long ixp4xx_exp_bus_size;
 375 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 376
 377 void __init ixp4xx_sys_init(void)
 378 {
 379         ixp4xx_exp_bus_size = SZ_16M;
 380
 381         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 382
 383         if (cpu_is_ixp46x()) {
 384                 int region;
 385
 386                 platform_add_devices(ixp46x_devices,
 387                                 ARRAY_SIZE(ixp46x_devices));
 388
 389                 for (region = 0; region < 7; region++) {
 390                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 391                                 ixp4xx_exp_bus_size = SZ_32M;
 392                                 break;
 393                         }
 394                 }
 395         }
 396
 397         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 398                         ixp4xx_exp_bus_size >> 20);
 399 }
 400
 401 /*
 402  * clocksource
 403  */
 404 static cycle_t ixp4xx_get_cycles(struct clocksource *cs)
 405 {
 406         return *IXP4XX_OSTS;
 407 }
 408
 409 static struct clocksource clocksource_ixp4xx = {
 410         .name           = "OSTS",
 411         .rating         = 200,
 412         .read           = ixp4xx_get_cycles,
 413         .mask           = CLOCKSOURCE_MASK(32),
 414         .shift          = 20,
 415         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 416 };
 417
 418 unsigned long ixp4xx_timer_freq = FREQ;
 419 EXPORT_SYMBOL(ixp4xx_timer_freq);
 420 static void __init ixp4xx_clocksource_init(void)
 421 {
 422         clocksource_ixp4xx.mult =
 423                 clocksource_hz2mult(ixp4xx_timer_freq,
 424                                     clocksource_ixp4xx.shift);
 425         clocksource_register(&clocksource_ixp4xx);
 426 }
 427
 428 /*
 429  * sched_clock()
 430  */
 431 unsigned long long sched_clock(void)
 432 {
 433         cycle_t cyc = ixp4xx_get_cycles(NULL);
 434         struct clocksource *cs = &clocksource_ixp4xx;
 435
 436         return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
 437 }
 438
 439 /*
 440  * clockevents
 441  */
 442 static int ixp4xx_set_next_event(unsigned long evt,
 443                                  struct clock_event_device *unused)
 444 {
 445         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 446
 447         *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
 448
 449         return 0;
 450 }
 451
 452 static void ixp4xx_set_mode(enum clock_event_mode mode,
 453                             struct clock_event_device *evt)
 454 {
 455         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 456         unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
 457
 458         switch (mode) {
 459         case CLOCK_EVT_MODE_PERIODIC:
 460                 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
 461                 opts = IXP4XX_OST_ENABLE;
 462                 break;
 463         case CLOCK_EVT_MODE_ONESHOT:
 464                 /* period set by 'set next_event' */
 465                 osrt = 0;
 466                 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
 467                 break;
 468         case CLOCK_EVT_MODE_SHUTDOWN:
 469                 opts &= ~IXP4XX_OST_ENABLE;
 470                 break;
 471         case CLOCK_EVT_MODE_RESUME:
 472                 opts |= IXP4XX_OST_ENABLE;
 473                 break;
 474         case CLOCK_EVT_MODE_UNUSED:
 475         default:
 476                 osrt = opts = 0;
 477                 break;
 478         }
 479
 480         *IXP4XX_OSRT1 = osrt | opts;
 481 }
 482
 483 static struct clock_event_device clockevent_ixp4xx = {
 484         .name           = "ixp4xx timer1",
 485         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 486         .rating         = 200,
 487         .shift          = 24,
 488         .set_mode       = ixp4xx_set_mode,
 489         .set_next_event = ixp4xx_set_next_event,
 490 };
 491
 492 static void __init ixp4xx_clockevent_init(void)
 493 {
 494         clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC,
 495                                         clockevent_ixp4xx.shift);
 496         clockevent_ixp4xx.max_delta_ns =
 497                 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
 498         clockevent_ixp4xx.min_delta_ns =
 499                 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
 500         clockevent_ixp4xx.cpumask = cpumask_of(0);
 501
 502         clockevents_register_device(&clockevent_ixp4xx);
 503 }