arch/arm/mach-kirkwood/pcie.c

   1 /*
   2  * arch/arm/mach-kirkwood/pcie.c
   3  *
   4  * PCIe functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <linux/slab.h>
  14 #include <linux/mbus.h>
  15 #include <asm/irq.h>
  16 #include <asm/mach/pci.h>
  17 #include <plat/pcie.h>
  18 #include <mach/bridge-regs.h>
  19 #include "common.h"
  20
  21
  22 #define PCIE_BASE       ((void __iomem *)PCIE_VIRT_BASE)
  23
  24 void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
  25 {
  26         *dev = orion_pcie_dev_id(PCIE_BASE);
  27         *rev = orion_pcie_rev(PCIE_BASE);
  28 }
  29
  30 static int pcie_valid_config(int bus, int dev)
  31 {
  32         /*
  33          * Don't go out when trying to access --
  34          * 1. nonexisting device on local bus
  35          * 2. where there's no device connected (no link)
  36          */
  37         if (bus == 0 && dev == 0)
  38                 return 1;
  39
  40         if (!orion_pcie_link_up(PCIE_BASE))
  41                 return 0;
  42
  43         if (bus == 0 && dev != 1)
  44                 return 0;
  45
  46         return 1;
  47 }
  48
  49
  50 /*
  51  * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
  52  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  53  * transactions are atomic.
  54  */
  55 static DEFINE_SPINLOCK(kirkwood_pcie_lock);
  56
  57 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  58                         int size, u32 *val)
  59 {
  60         unsigned long flags;
  61         int ret;
  62
  63         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
  64                 *val = 0xffffffff;
  65                 return PCIBIOS_DEVICE_NOT_FOUND;
  66         }
  67
  68         spin_lock_irqsave(&kirkwood_pcie_lock, flags);
  69         ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
  70         spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
  71
  72         return ret;
  73 }
  74
  75 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
  76                         int where, int size, u32 val)
  77 {
  78         unsigned long flags;
  79         int ret;
  80
  81         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
  82                 return PCIBIOS_DEVICE_NOT_FOUND;
  83
  84         spin_lock_irqsave(&kirkwood_pcie_lock, flags);
  85         ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
  86         spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
  87
  88         return ret;
  89 }
  90
  91 static struct pci_ops pcie_ops = {
  92         .read = pcie_rd_conf,
  93         .write = pcie_wr_conf,
  94 };
  95
  96
  97 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
  98 {
  99         struct resource *res;
 100         extern unsigned int kirkwood_clk_ctrl;
 101
 102         /*
 103          * Generic PCIe unit setup.
 104          */
 105         orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
 106
 107         /*
 108          * Request resources.
 109          */
 110         res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
 111         if (!res)
 112                 panic("pcie_setup unable to alloc resources");
 113
 114         /*
 115          * IORESOURCE_IO
 116          */
 117         res[0].name = "PCIe I/O Space";
 118         res[0].flags = IORESOURCE_IO;
 119         res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
 120         res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
 121         if (request_resource(&ioport_resource, &res[0]))
 122                 panic("Request PCIe IO resource failed\n");
 123         sys->resource[0] = &res[0];
 124
 125         /*
 126          * IORESOURCE_MEM
 127          */
 128         res[1].name = "PCIe Memory Space";
 129         res[1].flags = IORESOURCE_MEM;
 130         res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
 131         res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
 132         if (request_resource(&iomem_resource, &res[1]))
 133                 panic("Request PCIe Memory resource failed\n");
 134         sys->resource[1] = &res[1];
 135
 136         sys->resource[2] = NULL;
 137         sys->io_offset = 0;
 138
 139         kirkwood_clk_ctrl |= CGC_PEX0;
 140
 141         return 1;
 142 }
 143
 144 static void __devinit rc_pci_fixup(struct pci_dev *dev)
 145 {
 146         /*
 147          * Prevent enumeration of root complex.
 148          */
 149         if (dev->bus->parent == NULL && dev->devfn == 0) {
 150                 int i;
 151
 152                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 153                         dev->resource[i].start = 0;
 154                         dev->resource[i].end   = 0;
 155                         dev->resource[i].flags = 0;
 156                 }
 157         }
 158 }
 159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
 160
 161 static struct pci_bus __init *
 162 kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 163 {
 164         struct pci_bus *bus;
 165
 166         if (nr == 0) {
 167                 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 168         } else {
 169                 bus = NULL;
 170                 BUG();
 171         }
 172
 173         return bus;
 174 }
 175
 176 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 177 {
 178         return IRQ_KIRKWOOD_PCIE;
 179 }
 180
 181 static struct hw_pci kirkwood_pci __initdata = {
 182         .nr_controllers = 1,
 183         .swizzle        = pci_std_swizzle,
 184         .setup          = kirkwood_pcie_setup,
 185         .scan           = kirkwood_pcie_scan_bus,
 186         .map_irq        = kirkwood_pcie_map_irq,
 187 };
 188
 189 void __init kirkwood_pcie_init(void)
 190 {
 191         pci_common_init(&kirkwood_pci);
 192 }