arch/arm/mach-s3c2416/clock.c

   1 /* linux/arch/arm/mach-s3c2416/clock.c
   2  *
   3  * Copyright (c) 2010 Simtec Electronics
   4  * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
   5  *
   6  * S3C2416 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16
  17 #include <plat/s3c2416.h>
  18 #include <plat/s3c2443.h>
  19 #include <plat/clock.h>
  20 #include <plat/clock-clksrc.h>
  21 #include <plat/cpu.h>
  22
  23 #include <plat/cpu-freq.h>
  24 #include <plat/pll6553x.h>
  25 #include <plat/pll.h>
  26
  27 #include <asm/mach/map.h>
  28
  29 #include <mach/regs-clock.h>
  30 #include <mach/regs-s3c2443-clock.h>
  31
  32 static unsigned int armdiv[8] = {
  33         [0] = 1,
  34         [1] = 2,
  35         [2] = 3,
  36         [3] = 4,
  37         [5] = 6,
  38         [7] = 8,
  39 };
  40
  41 /* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */
  42 static struct clksrc_clk hsmmc_div[] = {
  43         [0] = {
  44                 .clk = {
  45                         .name   = "hsmmc-div",
  46                         .id     = 1,
  47                         .parent = &clk_esysclk.clk,
  48                 },
  49                 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
  50         },
  51         [1] = {
  52                 .clk = {
  53                         .name   = "hsmmc-div",
  54                         .id     = 0,
  55                         .parent = &clk_esysclk.clk,
  56                 },
  57                 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
  58         },
  59 };
  60
  61 static struct clksrc_clk hsmmc_mux[] = {
  62         [0] = {
  63                 .clk    = {
  64                         .id     = 1,
  65                         .name   = "hsmmc-if",
  66                         .ctrlbit = (1 << 6),
  67                         .enable = s3c2443_clkcon_enable_s,
  68                 },
  69                 .sources = &(struct clksrc_sources) {
  70                         .nr_sources = 2,
  71                         .sources = (struct clk *[]) {
  72                                 [0] = &hsmmc_div[0].clk,
  73                                 [1] = NULL, /* to fix */
  74                         },
  75                 },
  76                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
  77         },
  78         [1] = {
  79                 .clk    = {
  80                         .id     = 0,
  81                         .name   = "hsmmc-if",
  82                         .ctrlbit = (1 << 12),
  83                         .enable = s3c2443_clkcon_enable_s,
  84                 },
  85                 .sources = &(struct clksrc_sources) {
  86                         .nr_sources = 2,
  87                         .sources = (struct clk *[]) {
  88                                 [0] = &hsmmc_div[1].clk,
  89                                 [1] = NULL, /* to fix */
  90                         },
  91                 },
  92                 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
  93         },
  94 };
  95
  96
  97 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
  98 {
  99         clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
 100
 101         return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
 102 }
 103
 104 void __init_or_cpufreq s3c2416_setup_clocks(void)
 105 {
 106         s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
 107 }
 108
 109
 110 static struct clksrc_clk *clksrcs[] __initdata = {
 111         &hsmmc_div[0],
 112         &hsmmc_div[1],
 113         &hsmmc_mux[0],
 114         &hsmmc_mux[1],
 115 };
 116
 117 void __init s3c2416_init_clocks(int xtal)
 118 {
 119         u32 epllcon = __raw_readl(S3C2443_EPLLCON);
 120         u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
 121         int ptr;
 122
 123         /* s3c2416 EPLL compatible with s3c64xx */
 124         clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
 125
 126         clk_epll.parent = &clk_epllref.clk;
 127
 128         s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
 129
 130         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 131                 s3c_register_clksrc(clksrcs[ptr], 1);
 132
 133         s3c_pwmclk_init();
 134
 135 }