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Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs
[linux/fpc-iii.git] / arch / arm / mach-s3c64xx / clock.c
blobfbd85a9b7bbfa1ee279a502f8b3a6393ae8228c3
1 /* linux/arch/arm/plat-s3c64xx/clock.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX Base clock support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22
23 #include <mach/hardware.h>
24 #include <mach/map.h>
25
26 #include <mach/regs-sys.h>
27 #include <mach/regs-clock.h>
28 #include <mach/pll.h>
29
30 #include <plat/cpu.h>
31 #include <plat/devs.h>
32 #include <plat/cpu-freq.h>
33 #include <plat/clock.h>
34 #include <plat/clock-clksrc.h>
35
36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37 * ext_xtal_mux for want of an actual name from the manual.
38 */
39
40 static struct clk clk_ext_xtal_mux = {
41 .name = "ext_xtal",
42 .id = -1,
43 };
44
45 #define clk_fin_apll clk_ext_xtal_mux
46 #define clk_fin_mpll clk_ext_xtal_mux
47 #define clk_fin_epll clk_ext_xtal_mux
48
49 #define clk_fout_mpll clk_mpll
50 #define clk_fout_epll clk_epll
51
52 struct clk clk_h2 = {
53 .name = "hclk2",
54 .id = -1,
55 .rate = 0,
56 };
57
58 struct clk clk_27m = {
59 .name = "clk_27m",
60 .id = -1,
61 .rate = 27000000,
62 };
63
64 static int clk_48m_ctrl(struct clk *clk, int enable)
65 {
66 unsigned long flags;
67 u32 val;
68
69 /* can't rely on clock lock, this register has other usages */
70 local_irq_save(flags);
71
72 val = __raw_readl(S3C64XX_OTHERS);
73 if (enable)
74 val |= S3C64XX_OTHERS_USBMASK;
75 else
76 val &= ~S3C64XX_OTHERS_USBMASK;
77
78 __raw_writel(val, S3C64XX_OTHERS);
79 local_irq_restore(flags);
80
81 return 0;
82 }
83
84 struct clk clk_48m = {
85 .name = "clk_48m",
86 .id = -1,
87 .rate = 48000000,
88 .enable = clk_48m_ctrl,
89 };
90
91 struct clk clk_xusbxti = {
92 .name = "xusbxti",
93 .id = -1,
94 .rate = 48000000,
95 };
96
97 static int inline s3c64xx_gate(void __iomem *reg,
98 struct clk *clk,
99 int enable)
100 {
101 unsigned int ctrlbit = clk->ctrlbit;
102 u32 con;
103
104 con = __raw_readl(reg);
105
106 if (enable)
107 con |= ctrlbit;
108 else
109 con &= ~ctrlbit;
110
111 __raw_writel(con, reg);
112 return 0;
113 }
114
115 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
116 {
117 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
118 }
119
120 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
121 {
122 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
123 }
124
125 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
126 {
127 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
128 }
129
130 static struct clk init_clocks_disable[] = {
131 {
132 .name = "nand",
133 .id = -1,
134 .parent = &clk_h,
135 }, {
136 .name = "adc",
137 .id = -1,
138 .parent = &clk_p,
139 .enable = s3c64xx_pclk_ctrl,
140 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
141 }, {
142 .name = "i2c",
143 .id = -1,
144 .parent = &clk_p,
145 .enable = s3c64xx_pclk_ctrl,
146 .ctrlbit = S3C_CLKCON_PCLK_IIC,
147 }, {
148 .name = "iis",
149 .id = 0,
150 .parent = &clk_p,
151 .enable = s3c64xx_pclk_ctrl,
152 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
153 }, {
154 .name = "iis",
155 .id = 1,
156 .parent = &clk_p,
157 .enable = s3c64xx_pclk_ctrl,
158 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
159 }, {
160 #ifdef CONFIG_CPU_S3C6410
161 .name = "iis",
162 .id = -1, /* There's only one IISv4 port */
163 .parent = &clk_p,
164 .enable = s3c64xx_pclk_ctrl,
165 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
166 }, {
167 #endif
168 .name = "spi",
169 .id = 0,
170 .parent = &clk_p,
171 .enable = s3c64xx_pclk_ctrl,
172 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
173 }, {
174 .name = "spi",
175 .id = 1,
176 .parent = &clk_p,
177 .enable = s3c64xx_pclk_ctrl,
178 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
179 }, {
180 .name = "spi_48m",
181 .id = 0,
182 .parent = &clk_48m,
183 .enable = s3c64xx_sclk_ctrl,
184 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
185 }, {
186 .name = "spi_48m",
187 .id = 1,
188 .parent = &clk_48m,
189 .enable = s3c64xx_sclk_ctrl,
190 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
191 }, {
192 .name = "48m",
193 .id = 0,
194 .parent = &clk_48m,
195 .enable = s3c64xx_sclk_ctrl,
196 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
197 }, {
198 .name = "48m",
199 .id = 1,
200 .parent = &clk_48m,
201 .enable = s3c64xx_sclk_ctrl,
202 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
203 }, {
204 .name = "48m",
205 .id = 2,
206 .parent = &clk_48m,
207 .enable = s3c64xx_sclk_ctrl,
208 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
209 }, {
210 .name = "dma0",
211 .id = -1,
212 .parent = &clk_h,
213 .enable = s3c64xx_hclk_ctrl,
214 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
215 }, {
216 .name = "dma1",
217 .id = -1,
218 .parent = &clk_h,
219 .enable = s3c64xx_hclk_ctrl,
220 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
221 },
222 };
223
224 static struct clk init_clocks[] = {
225 {
226 .name = "lcd",
227 .id = -1,
228 .parent = &clk_h,
229 .enable = s3c64xx_hclk_ctrl,
230 .ctrlbit = S3C_CLKCON_HCLK_LCD,
231 }, {
232 .name = "gpio",
233 .id = -1,
234 .parent = &clk_p,
235 .enable = s3c64xx_pclk_ctrl,
236 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
237 }, {
238 .name = "usb-host",
239 .id = -1,
240 .parent = &clk_h,
241 .enable = s3c64xx_hclk_ctrl,
242 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
243 }, {
244 .name = "hsmmc",
245 .id = 0,
246 .parent = &clk_h,
247 .enable = s3c64xx_hclk_ctrl,
248 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
249 }, {
250 .name = "hsmmc",
251 .id = 1,
252 .parent = &clk_h,
253 .enable = s3c64xx_hclk_ctrl,
254 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
255 }, {
256 .name = "hsmmc",
257 .id = 2,
258 .parent = &clk_h,
259 .enable = s3c64xx_hclk_ctrl,
260 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
261 }, {
262 .name = "otg",
263 .id = -1,
264 .parent = &clk_h,
265 .enable = s3c64xx_hclk_ctrl,
266 .ctrlbit = S3C_CLKCON_HCLK_USB,
267 }, {
268 .name = "timers",
269 .id = -1,
270 .parent = &clk_p,
271 .enable = s3c64xx_pclk_ctrl,
272 .ctrlbit = S3C_CLKCON_PCLK_PWM,
273 }, {
274 .name = "uart",
275 .id = 0,
276 .parent = &clk_p,
277 .enable = s3c64xx_pclk_ctrl,
278 .ctrlbit = S3C_CLKCON_PCLK_UART0,
279 }, {
280 .name = "uart",
281 .id = 1,
282 .parent = &clk_p,
283 .enable = s3c64xx_pclk_ctrl,
284 .ctrlbit = S3C_CLKCON_PCLK_UART1,
285 }, {
286 .name = "uart",
287 .id = 2,
288 .parent = &clk_p,
289 .enable = s3c64xx_pclk_ctrl,
290 .ctrlbit = S3C_CLKCON_PCLK_UART2,
291 }, {
292 .name = "uart",
293 .id = 3,
294 .parent = &clk_p,
295 .enable = s3c64xx_pclk_ctrl,
296 .ctrlbit = S3C_CLKCON_PCLK_UART3,
297 }, {
298 .name = "rtc",
299 .id = -1,
300 .parent = &clk_p,
301 .enable = s3c64xx_pclk_ctrl,
302 .ctrlbit = S3C_CLKCON_PCLK_RTC,
303 }, {
304 .name = "watchdog",
305 .id = -1,
306 .parent = &clk_p,
307 .ctrlbit = S3C_CLKCON_PCLK_WDT,
308 }, {
309 .name = "ac97",
310 .id = -1,
311 .parent = &clk_p,
312 .ctrlbit = S3C_CLKCON_PCLK_AC97,
313 }
314 };
315
316
317 static struct clk clk_fout_apll = {
318 .name = "fout_apll",
319 .id = -1,
320 };
321
322 static struct clk *clk_src_apll_list[] = {
323 [0] = &clk_fin_apll,
324 [1] = &clk_fout_apll,
325 };
326
327 static struct clksrc_sources clk_src_apll = {
328 .sources = clk_src_apll_list,
329 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
330 };
331
332 static struct clksrc_clk clk_mout_apll = {
333 .clk = {
334 .name = "mout_apll",
335 .id = -1,
336 },
337 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
338 .sources = &clk_src_apll,
339 };
340
341 static struct clk *clk_src_epll_list[] = {
342 [0] = &clk_fin_epll,
343 [1] = &clk_fout_epll,
344 };
345
346 static struct clksrc_sources clk_src_epll = {
347 .sources = clk_src_epll_list,
348 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
349 };
350
351 static struct clksrc_clk clk_mout_epll = {
352 .clk = {
353 .name = "mout_epll",
354 .id = -1,
355 },
356 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
357 .sources = &clk_src_epll,
358 };
359
360 static struct clk *clk_src_mpll_list[] = {
361 [0] = &clk_fin_mpll,
362 [1] = &clk_fout_mpll,
363 };
364
365 static struct clksrc_sources clk_src_mpll = {
366 .sources = clk_src_mpll_list,
367 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
368 };
369
370 static struct clksrc_clk clk_mout_mpll = {
371 .clk = {
372 .name = "mout_mpll",
373 .id = -1,
374 },
375 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
376 .sources = &clk_src_mpll,
377 };
378
379 static unsigned int armclk_mask;
380
381 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
382 {
383 unsigned long rate = clk_get_rate(clk->parent);
384 u32 clkdiv;
385
386 /* divisor mask starts at bit0, so no need to shift */
387 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
388
389 return rate / (clkdiv + 1);
390 }
391
392 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
393 unsigned long rate)
394 {
395 unsigned long parent = clk_get_rate(clk->parent);
396 u32 div;
397
398 if (parent < rate)
399 return parent;
400
401 div = (parent / rate) - 1;
402 if (div > armclk_mask)
403 div = armclk_mask;
404
405 return parent / (div + 1);
406 }
407
408 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
409 {
410 unsigned long parent = clk_get_rate(clk->parent);
411 u32 div;
412 u32 val;
413
414 if (rate < parent / (armclk_mask + 1))
415 return -EINVAL;
416
417 rate = clk_round_rate(clk, rate);
418 div = clk_get_rate(clk->parent) / rate;
419
420 val = __raw_readl(S3C_CLK_DIV0);
421 val &= ~armclk_mask;
422 val |= (div - 1);
423 __raw_writel(val, S3C_CLK_DIV0);
424
425 return 0;
426
427 }
428
429 static struct clk clk_arm = {
430 .name = "armclk",
431 .id = -1,
432 .parent = &clk_mout_apll.clk,
433 .ops = &(struct clk_ops) {
434 .get_rate = s3c64xx_clk_arm_get_rate,
435 .set_rate = s3c64xx_clk_arm_set_rate,
436 .round_rate = s3c64xx_clk_arm_round_rate,
437 },
438 };
439
440 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
441 {
442 unsigned long rate = clk_get_rate(clk->parent);
443
444 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
445
446 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
447 rate /= 2;
448
449 return rate;
450 }
451
452 static struct clk_ops clk_dout_ops = {
453 .get_rate = s3c64xx_clk_doutmpll_get_rate,
454 };
455
456 static struct clk clk_dout_mpll = {
457 .name = "dout_mpll",
458 .id = -1,
459 .parent = &clk_mout_mpll.clk,
460 .ops = &clk_dout_ops,
461 };
462
463 static struct clk *clkset_spi_mmc_list[] = {
464 &clk_mout_epll.clk,
465 &clk_dout_mpll,
466 &clk_fin_epll,
467 &clk_27m,
468 };
469
470 static struct clksrc_sources clkset_spi_mmc = {
471 .sources = clkset_spi_mmc_list,
472 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
473 };
474
475 static struct clk *clkset_irda_list[] = {
476 &clk_mout_epll.clk,
477 &clk_dout_mpll,
478 NULL,
479 &clk_27m,
480 };
481
482 static struct clksrc_sources clkset_irda = {
483 .sources = clkset_irda_list,
484 .nr_sources = ARRAY_SIZE(clkset_irda_list),
485 };
486
487 static struct clk *clkset_uart_list[] = {
488 &clk_mout_epll.clk,
489 &clk_dout_mpll,
490 NULL,
491 NULL
492 };
493
494 static struct clksrc_sources clkset_uart = {
495 .sources = clkset_uart_list,
496 .nr_sources = ARRAY_SIZE(clkset_uart_list),
497 };
498
499 static struct clk *clkset_uhost_list[] = {
500 &clk_48m,
501 &clk_mout_epll.clk,
502 &clk_dout_mpll,
503 &clk_fin_epll,
504 };
505
506 static struct clksrc_sources clkset_uhost = {
507 .sources = clkset_uhost_list,
508 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
509 };
510
511 /* The peripheral clocks are all controlled via clocksource followed
512 * by an optional divider and gate stage. We currently roll this into
513 * one clock which hides the intermediate clock from the mux.
514 *
515 * Note, the JPEG clock can only be an even divider...
516 *
517 * The scaler and LCD clocks depend on the S3C64XX version, and also
518 * have a common parent divisor so are not included here.
519 */
520
521 /* clocks that feed other parts of the clock source tree */
522
523 static struct clk clk_iis_cd0 = {
524 .name = "iis_cdclk0",
525 .id = -1,
526 };
527
528 static struct clk clk_iis_cd1 = {
529 .name = "iis_cdclk1",
530 .id = -1,
531 };
532
533 static struct clk clk_iisv4_cd = {
534 .name = "iis_cdclk_v4",
535 .id = -1,
536 };
537
538 static struct clk clk_pcm_cd = {
539 .name = "pcm_cdclk",
540 .id = -1,
541 };
542
543 static struct clk *clkset_audio0_list[] = {
544 [0] = &clk_mout_epll.clk,
545 [1] = &clk_dout_mpll,
546 [2] = &clk_fin_epll,
547 [3] = &clk_iis_cd0,
548 [4] = &clk_pcm_cd,
549 };
550
551 static struct clksrc_sources clkset_audio0 = {
552 .sources = clkset_audio0_list,
553 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
554 };
555
556 static struct clk *clkset_audio1_list[] = {
557 [0] = &clk_mout_epll.clk,
558 [1] = &clk_dout_mpll,
559 [2] = &clk_fin_epll,
560 [3] = &clk_iis_cd1,
561 [4] = &clk_pcm_cd,
562 };
563
564 static struct clksrc_sources clkset_audio1 = {
565 .sources = clkset_audio1_list,
566 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
567 };
568
569 static struct clk *clkset_audio2_list[] = {
570 [0] = &clk_mout_epll.clk,
571 [1] = &clk_dout_mpll,
572 [2] = &clk_fin_epll,
573 [3] = &clk_iisv4_cd,
574 [4] = &clk_pcm_cd,
575 };
576
577 static struct clksrc_sources clkset_audio2 = {
578 .sources = clkset_audio2_list,
579 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
580 };
581
582 static struct clk *clkset_camif_list[] = {
583 &clk_h2,
584 };
585
586 static struct clksrc_sources clkset_camif = {
587 .sources = clkset_camif_list,
588 .nr_sources = ARRAY_SIZE(clkset_camif_list),
589 };
590
591 static struct clksrc_clk clksrcs[] = {
592 {
593 .clk = {
594 .name = "mmc_bus",
595 .id = 0,
596 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
597 .enable = s3c64xx_sclk_ctrl,
598 },
599 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
600 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
601 .sources = &clkset_spi_mmc,
602 }, {
603 .clk = {
604 .name = "mmc_bus",
605 .id = 1,
606 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
607 .enable = s3c64xx_sclk_ctrl,
608 },
609 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
610 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
611 .sources = &clkset_spi_mmc,
612 }, {
613 .clk = {
614 .name = "mmc_bus",
615 .id = 2,
616 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
617 .enable = s3c64xx_sclk_ctrl,
618 },
619 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
620 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
621 .sources = &clkset_spi_mmc,
622 }, {
623 .clk = {
624 .name = "usb-bus-host",
625 .id = -1,
626 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
627 .enable = s3c64xx_sclk_ctrl,
628 },
629 .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
630 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
631 .sources = &clkset_uhost,
632 }, {
633 .clk = {
634 .name = "uclk1",
635 .id = -1,
636 .ctrlbit = S3C_CLKCON_SCLK_UART,
637 .enable = s3c64xx_sclk_ctrl,
638 },
639 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
640 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
641 .sources = &clkset_uart,
642 }, {
643 /* Where does UCLK0 come from? */
644 .clk = {
645 .name = "spi-bus",
646 .id = 0,
647 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
648 .enable = s3c64xx_sclk_ctrl,
649 },
650 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
651 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
652 .sources = &clkset_spi_mmc,
653 }, {
654 .clk = {
655 .name = "spi-bus",
656 .id = 1,
657 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
658 .enable = s3c64xx_sclk_ctrl,
659 },
660 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
661 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
662 .sources = &clkset_spi_mmc,
663 }, {
664 .clk = {
665 .name = "audio-bus",
666 .id = 0,
667 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
668 .enable = s3c64xx_sclk_ctrl,
669 },
670 .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
671 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
672 .sources = &clkset_audio0,
673 }, {
674 .clk = {
675 .name = "audio-bus",
676 .id = 1,
677 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
678 .enable = s3c64xx_sclk_ctrl,
679 },
680 .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
681 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
682 .sources = &clkset_audio1,
683 }, {
684 .clk = {
685 .name = "audio-bus",
686 .id = -1, /* There's only one IISv4 port */
687 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
688 .enable = s3c64xx_sclk_ctrl,
689 },
690 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
691 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
692 .sources = &clkset_audio2,
693 }, {
694 .clk = {
695 .name = "irda-bus",
696 .id = 0,
697 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
698 .enable = s3c64xx_sclk_ctrl,
699 },
700 .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
701 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
702 .sources = &clkset_irda,
703 }, {
704 .clk = {
705 .name = "camera",
706 .id = -1,
707 .ctrlbit = S3C_CLKCON_SCLK_CAM,
708 .enable = s3c64xx_sclk_ctrl,
709 },
710 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
711 .reg_src = { .reg = NULL, .shift = 0, .size = 0 },
712 .sources = &clkset_camif,
713 },
714 };
715
716 /* Clock initialisation code */
717
718 static struct clksrc_clk *init_parents[] = {
719 &clk_mout_apll,
720 &clk_mout_epll,
721 &clk_mout_mpll,
722 };
723
724 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
725
726 void __init_or_cpufreq s3c6400_setup_clocks(void)
727 {
728 struct clk *xtal_clk;
729 unsigned long xtal;
730 unsigned long fclk;
731 unsigned long hclk;
732 unsigned long hclk2;
733 unsigned long pclk;
734 unsigned long epll;
735 unsigned long apll;
736 unsigned long mpll;
737 unsigned int ptr;
738 u32 clkdiv0;
739
740 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
741
742 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
743 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
744
745 xtal_clk = clk_get(NULL, "xtal");
746 BUG_ON(IS_ERR(xtal_clk));
747
748 xtal = clk_get_rate(xtal_clk);
749 clk_put(xtal_clk);
750
751 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
752
753 /* For now assume the mux always selects the crystal */
754 clk_ext_xtal_mux.parent = xtal_clk;
755
756 epll = s3c6400_get_epll(xtal);
757 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
758 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
759
760 fclk = mpll;
761
762 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
763 apll, mpll, epll);
764
765 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
766 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
767 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
768
769 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
770 hclk2, hclk, pclk);
771
772 clk_fout_mpll.rate = mpll;
773 clk_fout_epll.rate = epll;
774 clk_fout_apll.rate = apll;
775
776 clk_h2.rate = hclk2;
777 clk_h.rate = hclk;
778 clk_p.rate = pclk;
779 clk_f.rate = fclk;
780
781 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
782 s3c_set_clksrc(init_parents[ptr], true);
783
784 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
785 s3c_set_clksrc(&clksrcs[ptr], true);
786 }
787
788 static struct clk *clks1[] __initdata = {
789 &clk_ext_xtal_mux,
790 &clk_iis_cd0,
791 &clk_iis_cd1,
792 &clk_iisv4_cd,
793 &clk_pcm_cd,
794 &clk_mout_epll.clk,
795 &clk_mout_mpll.clk,
796 &clk_dout_mpll,
797 &clk_arm,
798 };
799
800 static struct clk *clks[] __initdata = {
801 &clk_ext,
802 &clk_epll,
803 &clk_27m,
804 &clk_48m,
805 &clk_h2,
806 &clk_xusbxti,
807 };
808
809 /**
810 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
811 * @xtal: The rate for the clock crystal feeding the PLLs.
812 * @armclk_divlimit: Divisor mask for ARMCLK.
813 *
814 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
815 * as ARMCLK as well as the necessary parent clocks.
816 *
817 * This call does not setup the clocks, which is left to the
818 * s3c6400_setup_clocks() call which may be needed by the cpufreq
819 * or resume code to re-set the clocks if the bootloader has changed
820 * them.
821 */
822 void __init s3c64xx_register_clocks(unsigned long xtal,
823 unsigned armclk_divlimit)
824 {
825 struct clk *clkp;
826 int ret;
827 int ptr;
828
829 armclk_mask = armclk_divlimit;
830
831 s3c24xx_register_baseclocks(xtal);
832 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
833
834 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
835
836 clkp = init_clocks_disable;
837 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
838
839 ret = s3c24xx_register_clock(clkp);
840 if (ret < 0) {
841 printk(KERN_ERR "Failed to register clock %s (%d)\n",
842 clkp->name, ret);
843 }
844
845 (clkp->enable)(clkp, 0);
846 }
847
848 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
849 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
850 s3c_pwmclk_init();
851 }
Linux with added FPC-III support