arch/arm/mach-shmobile/intc-sh7372.c

   1 /*
   2  * sh7372 processor support - INTC hardware block
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/sh_intc.h>
  25 #include <asm/mach-types.h>
  26 #include <asm/mach/arch.h>
  27
  28 enum {
  29         UNUSED_INTCA = 0,
  30         ENABLED,
  31         DISABLED,
  32
  33         /* interrupt sources INTCA */
  34         IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
  35         IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
  36         IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
  37         IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
  38         DIRC,
  39         CRYPT_STD,
  40         IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
  41         AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
  42         MFI_MFIM, MFI_MFIS,
  43         BBIF1, BBIF2,
  44         USBHSDMAC0_USHDMI,
  45         _3DG_SGX540,
  46         CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
  47         KEYSC_KEY,
  48         SCIFA0, SCIFA1, SCIFA2, SCIFA3,
  49         MSIOF2, MSIOF1,
  50         SCIFA4, SCIFA5, SCIFB,
  51         FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
  52         SDHI0,
  53         SDHI1,
  54         IRREM,
  55         IRDA,
  56         TPU0,
  57         TTI20,
  58         DDM,
  59         SDHI2,
  60         RWDT0,
  61         DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
  62         DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
  63         DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
  64         DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
  65         DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
  66         DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
  67         SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
  68         HDMI,
  69         SPU2_SPU0, SPU2_SPU1,
  70         FSI, FMSI,
  71         MIPI_HSI,
  72         IPMMU_IPMMUD,
  73         CEC_1, CEC_2,
  74         AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
  75         MFIS2,
  76         CPORTR2S,
  77         CMT14, CMT15,
  78         MMC_MMC_ERR, MMC_MMC_NOR,
  79         IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
  80         IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
  81         USB0_USB0I1, USB0_USB0I0,
  82         USB1_USB1I1, USB1_USB1I0,
  83         USBHSDMAC1_USHDMI,
  84
  85         /* interrupt groups INTCA */
  86         DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
  87         AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1
  88 };
  89
  90 static struct intc_vect intca_vectors[] __initdata = {
  91         INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
  92         INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
  93         INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
  94         INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
  95         INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
  96         INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
  97         INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
  98         INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
  99         INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
 100         INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
 101         INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
 102         INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
 103         INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
 104         INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
 105         INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
 106         INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
 107         INTC_VECT(DIRC, 0x0560),
 108         INTC_VECT(CRYPT_STD, 0x0700),
 109         INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
 110         INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
 111         INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
 112         INTC_VECT(AP_ARM_COMMRX, 0x0860),
 113         INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
 114         INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
 115         INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
 116         INTC_VECT(_3DG_SGX540, 0x0a60),
 117         INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
 118         INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
 119         INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
 120         INTC_VECT(KEYSC_KEY, 0x0be0),
 121         INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
 122         INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
 123         INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
 124         INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
 125         INTC_VECT(SCIFB, 0x0d60),
 126         INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
 127         INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
 128         INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
 129         INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
 130         INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
 131         INTC_VECT(SDHI1, 0x0ec0),
 132         INTC_VECT(IRREM, 0x0f60),
 133         INTC_VECT(IRDA, 0x0480),
 134         INTC_VECT(TPU0, 0x04a0),
 135         INTC_VECT(TTI20, 0x1100),
 136         INTC_VECT(DDM, 0x1140),
 137         INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
 138         INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
 139         INTC_VECT(RWDT0, 0x1280),
 140         INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
 141         INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
 142         INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
 143         INTC_VECT(DMAC1_2_DADERR, 0x20c0),
 144         INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
 145         INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
 146         INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
 147         INTC_VECT(DMAC2_2_DADERR, 0x21c0),
 148         INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
 149         INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
 150         INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
 151         INTC_VECT(DMAC3_2_DADERR, 0x22c0),
 152         INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
 153         INTC_VECT(SHWYSTAT_COM, 0x1340),
 154         INTC_VECT(HDMI, 0x17e0),
 155         INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
 156         INTC_VECT(FSI, 0x1840),
 157         INTC_VECT(FMSI, 0x1860),
 158         INTC_VECT(MIPI_HSI, 0x18e0),
 159         INTC_VECT(IPMMU_IPMMUD, 0x1920),
 160         INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
 161         INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
 162         INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
 163         INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
 164         INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
 165         INTC_VECT(MFIS2, 0x1a00),
 166         INTC_VECT(CPORTR2S, 0x1a20),
 167         INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
 168         INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
 169         INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
 170         INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
 171         INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
 172         INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
 173         INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
 174         INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
 175         INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
 176 };
 177
 178 static struct intc_group intca_groups[] __initdata = {
 179         INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
 180                    DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
 181         INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
 182                    DMAC1_2_DEI5, DMAC1_2_DADERR),
 183         INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
 184                    DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
 185         INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
 186                    DMAC2_2_DEI5, DMAC2_2_DADERR),
 187         INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
 188                    DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
 189         INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
 190                    DMAC3_2_DEI5, DMAC3_2_DADERR),
 191         INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
 192         INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
 193                    AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
 194         INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
 195         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
 196                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 197         INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
 198         INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
 199 };
 200
 201 static struct intc_mask_reg intca_mask_registers[] __initdata = {
 202         { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
 203           { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
 204         { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
 205           { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
 206         { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
 207           { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
 208         { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
 209           { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
 210
 211         { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
 212           { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
 213             AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
 214         { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
 215           { 0, CRYPT_STD, DIRC, 0,
 216             DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
 217         { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
 218           { 0, 0, 0, 0,
 219             BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
 220         { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
 221           { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
 222             DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
 223         { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
 224           { DDM, 0, 0, 0,
 225             0, 0, 0, 0 } },
 226         { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
 227           { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
 228             SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
 229         { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
 230           { SCIFB, SCIFA5, SCIFA4, MSIOF1,
 231             0, 0, MSIOF2, 0 } },
 232         { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
 233           { DISABLED, DISABLED, ENABLED, ENABLED,
 234             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
 235         { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
 236           { 0, DISABLED, ENABLED, ENABLED,
 237             TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
 238         { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
 239           { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
 240             CMT2, 0, 0, _3DG_SGX540 } },
 241         { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
 242           { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
 243             0, 0, 0, 0 } },
 244         { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
 245           { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
 246             0, 0, IRREM, 0 } },
 247         { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
 248           { 0, 0, TPU0, 0,
 249             0, 0, 0, 0 } },
 250         { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
 251           { DISABLED, DISABLED, ENABLED, ENABLED,
 252             0, CMT3, 0, RWDT0 } },
 253         { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
 254           { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
 255             0, 0, 0, 0 } },
 256         { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
 257           { 0, 0, 0, 0,
 258             0, 0, 0, HDMI } },
 259         { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
 260           { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
 261             0, 0, 0, MIPI_HSI } },
 262         { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
 263           { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
 264             AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
 265             AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
 266         { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
 267           { MFIS2, CPORTR2S, CMT14, CMT15,
 268             0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
 269         { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
 270           { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
 271             IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
 272         { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
 273           { 0, 0, 0, 0,
 274             USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
 275         { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
 276           { USBHSDMAC1_USHDMI, 0, 0, 0,
 277             0, 0, 0, 0 } },
 278 };
 279
 280 static struct intc_prio_reg intca_prio_registers[] __initdata = {
 281         { 0xe6900010, 0, 32, 4, /* INTPRI00A */
 282           { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
 283         { 0xe6900014, 0, 32, 4, /* INTPRI10A */
 284           { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
 285         { 0xe6900018, 0, 32, 4, /* INTPRI20A */
 286           { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
 287         { 0xe690001c, 0, 32, 4, /* INTPRI30A */
 288           { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
 289
 290         { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
 291         { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
 292         { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
 293                                               CMT1_CMT11, AP_ARM1 } },
 294         { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
 295                                               CMT1_CMT12, 0 } },
 296         { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
 297                                               MFI_MFIM, 0 } },
 298         { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
 299                                               _3DG_SGX540, CMT1_CMT10 } },
 300         { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
 301                                               SCIFA2, SCIFA3 } },
 302         { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
 303                                               FLCTL, SDHI0 } },
 304         { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
 305                                               0/* MSU */, IIC1 } },
 306         { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
 307                                               0/* MSUG */, TTI20 } },
 308         { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
 309         { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
 310         { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
 311         { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
 312         { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
 313         { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
 314         { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
 315         { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
 316         { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
 317         { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
 318                                                CEC_1, CEC_2 } },
 319         { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
 320         { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
 321                                                CMT14, CMT15 } },
 322         { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
 323                                                MMC_MMC_ERR, MMC_MMC_NOR } },
 324         { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
 325                                                IIC4_WAITI4, IIC4_DTEI4 } },
 326         { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
 327                                                IIC3_WAITI3, IIC3_DTEI3 } },
 328         { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
 329                                                0/*TXI*/, 0/*TEI*/} },
 330         { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
 331                                                USB1_USB1I1, USB1_USB1I0 } },
 332         { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
 333 };
 334
 335 static struct intc_sense_reg intca_sense_registers[] __initdata = {
 336         { 0xe6900000, 32, 4, /* ICR1A */
 337           { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
 338         { 0xe6900004, 32, 4, /* ICR2A */
 339           { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
 340         { 0xe6900008, 32, 4, /* ICR3A */
 341           { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
 342         { 0xe690000c, 32, 4, /* ICR4A */
 343           { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
 344 };
 345
 346 static struct intc_mask_reg intca_ack_registers[] __initdata = {
 347         { 0xe6900020, 0, 8, /* INTREQ00A */
 348           { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
 349         { 0xe6900024, 0, 8, /* INTREQ10A */
 350           { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
 351         { 0xe6900028, 0, 8, /* INTREQ20A */
 352           { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
 353         { 0xe690002c, 0, 8, /* INTREQ30A */
 354           { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
 355 };
 356
 357 static struct intc_desc intca_desc __initdata = {
 358         .name = "sh7372-intca",
 359         .force_enable = ENABLED,
 360         .force_disable = DISABLED,
 361         .hw = INTC_HW_DESC(intca_vectors, intca_groups,
 362                            intca_mask_registers, intca_prio_registers,
 363                            intca_sense_registers, intca_ack_registers),
 364 };
 365
 366 void __init sh7372_init_irq(void)
 367 {
 368         register_intc_controller(&intca_desc);
 369 }