arch/blackfin/kernel/cplb-mpu/cplbinit.c

   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  * Copyright 2008-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10
  11 #include <asm/blackfin.h>
  12 #include <asm/cplb.h>
  13 #include <asm/cplbinit.h>
  14 #include <asm/mem_map.h>
  15
  16 #if ANOMALY_05000263
  17 # error the MPU will not function safely while Anomaly 05000263 applies
  18 #endif
  19
  20 struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
  21 struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
  22
  23 int first_switched_icplb, first_switched_dcplb;
  24 int first_mask_dcplb;
  25
  26 void __init generate_cplb_tables_cpu(unsigned int cpu)
  27 {
  28         int i_d, i_i;
  29         unsigned long addr;
  30         unsigned long d_data, i_data;
  31         unsigned long d_cache = 0, i_cache = 0;
  32
  33         printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
  34
  35 #ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
  36         i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
  37 #endif
  38
  39 #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
  40         d_cache = CPLB_L1_CHBL;
  41 #ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
  42         d_cache |= CPLB_L1_AOW | CPLB_WT;
  43 #endif
  44 #endif
  45
  46         i_d = i_i = 0;
  47
  48         /* Set up the zero page.  */
  49         dcplb_tbl[cpu][i_d].addr = 0;
  50         dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
  51
  52         icplb_tbl[cpu][i_i].addr = 0;
  53         icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
  54
  55         /* Cover kernel memory with 4M pages.  */
  56         addr = 0;
  57         d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
  58         i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
  59
  60         for (; addr < memory_start; addr += 4 * 1024 * 1024) {
  61                 dcplb_tbl[cpu][i_d].addr = addr;
  62                 dcplb_tbl[cpu][i_d++].data = d_data;
  63                 icplb_tbl[cpu][i_i].addr = addr;
  64                 icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
  65         }
  66
  67 #ifdef CONFIG_ROMKERNEL
  68         /* Cover kernel XIP flash area */
  69         addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
  70         dcplb_tbl[cpu][i_d].addr = addr;
  71         dcplb_tbl[cpu][i_d++].data = d_data | CPLB_USER_RD;
  72         icplb_tbl[cpu][i_i].addr = addr;
  73         icplb_tbl[cpu][i_i++].data = i_data | CPLB_USER_RD;
  74 #endif
  75
  76         /* Cover L1 memory.  One 4M area for code and data each is enough.  */
  77 #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
  78         dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
  79         dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
  80 #endif
  81 #if L1_CODE_LENGTH > 0
  82         icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
  83         icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
  84 #endif
  85
  86         /* Cover L2 memory */
  87 #if L2_LENGTH > 0
  88         dcplb_tbl[cpu][i_d].addr = L2_START;
  89         dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
  90         icplb_tbl[cpu][i_i].addr = L2_START;
  91         icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
  92 #endif
  93
  94         first_mask_dcplb = i_d;
  95         first_switched_dcplb = i_d + (1 << page_mask_order);
  96         first_switched_icplb = i_i;
  97
  98         while (i_d < MAX_CPLBS)
  99                 dcplb_tbl[cpu][i_d++].data = 0;
 100         while (i_i < MAX_CPLBS)
 101                 icplb_tbl[cpu][i_i++].data = 0;
 102 }
 103
 104 void __init generate_cplb_tables_all(void)
 105 {
 106 }