arch/blackfin/mach-common/pm.c

   1 /*
   2  * Blackfin power management
   3  *
   4  * Copyright 2006-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2
   7  * based on arm/mach-omap/pm.c
   8  *    Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
   9  */
  10
  11 #include <linux/suspend.h>
  12 #include <linux/sched.h>
  13 #include <linux/proc_fs.h>
  14 #include <linux/slab.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17
  18 #include <asm/cplb.h>
  19 #include <asm/gpio.h>
  20 #include <asm/dma.h>
  21 #include <asm/dpmc.h>
  22
  23
  24 void bfin_pm_suspend_standby_enter(void)
  25 {
  26         unsigned long flags;
  27
  28         local_irq_save_hw(flags);
  29         bfin_pm_standby_setup();
  30
  31 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
  32         sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
  33 #else
  34         sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
  35 #endif
  36
  37         bfin_pm_standby_restore();
  38
  39 #ifdef SIC_IWR0
  40         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
  41 # ifdef SIC_IWR1
  42         /* BF52x system reset does not properly reset SIC_IWR1 which
  43          * will screw up the bootrom as it relies on MDMA0/1 waking it
  44          * up from IDLE instructions.  See this report for more info:
  45          * http://blackfin.uclinux.org/gf/tracker/4323
  46          */
  47         if (ANOMALY_05000435)
  48                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
  49         else
  50                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
  51 # endif
  52 # ifdef SIC_IWR2
  53         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
  54 # endif
  55 #else
  56         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
  57 #endif
  58
  59         local_irq_restore_hw(flags);
  60 }
  61
  62 int bf53x_suspend_l1_mem(unsigned char *memptr)
  63 {
  64         dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
  65         dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
  66                         L1_DATA_A_LENGTH);
  67         dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
  68                         (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
  69         memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
  70                         L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
  71                         L1_SCRATCH_LENGTH);
  72
  73         return 0;
  74 }
  75
  76 int bf53x_resume_l1_mem(unsigned char *memptr)
  77 {
  78         dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
  79         dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
  80                         L1_DATA_A_LENGTH);
  81         dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
  82                         L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
  83         memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
  84                         L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
  85
  86         return 0;
  87 }
  88
  89 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
  90 static void flushinv_all_dcache(void)
  91 {
  92         u32 way, bank, subbank, set;
  93         u32 status, addr;
  94         u32 dmem_ctl = bfin_read_DMEM_CONTROL();
  95
  96         for (bank = 0; bank < 2; ++bank) {
  97                 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
  98                         continue;
  99
 100                 for (way = 0; way < 2; ++way)
 101                         for (subbank = 0; subbank < 4; ++subbank)
 102                                 for (set = 0; set < 64; ++set) {
 103
 104                                         bfin_write_DTEST_COMMAND(
 105                                                 way << 26 |
 106                                                 bank << 23 |
 107                                                 subbank << 16 |
 108                                                 set << 5
 109                                         );
 110                                         CSYNC();
 111                                         status = bfin_read_DTEST_DATA0();
 112
 113                                         /* only worry about valid/dirty entries */
 114                                         if ((status & 0x3) != 0x3)
 115                                                 continue;
 116
 117                                         /* construct the address using the tag */
 118                                         addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
 119
 120                                         /* flush it */
 121                                         __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
 122                                 }
 123         }
 124 }
 125 #endif
 126
 127 int bfin_pm_suspend_mem_enter(void)
 128 {
 129         unsigned long flags;
 130         int wakeup, ret;
 131
 132         unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
 133                                          + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
 134                                           GFP_KERNEL);
 135
 136         if (memptr == NULL) {
 137                 panic("bf53x_suspend_l1_mem malloc failed");
 138                 return -ENOMEM;
 139         }
 140
 141         wakeup = bfin_read_VR_CTL() & ~FREQ;
 142         wakeup |= SCKELOW;
 143
 144 #ifdef CONFIG_PM_BFIN_WAKE_PH6
 145         wakeup |= PHYWE;
 146 #endif
 147 #ifdef CONFIG_PM_BFIN_WAKE_GP
 148         wakeup |= GPWE;
 149 #endif
 150
 151         local_irq_save_hw(flags);
 152
 153         ret = blackfin_dma_suspend();
 154
 155         if (ret) {
 156                 local_irq_restore_hw(flags);
 157                 kfree(memptr);
 158                 return ret;
 159         }
 160
 161         bfin_gpio_pm_hibernate_suspend();
 162
 163 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
 164         flushinv_all_dcache();
 165 #endif
 166         _disable_dcplb();
 167         _disable_icplb();
 168         bf53x_suspend_l1_mem(memptr);
 169
 170         do_hibernate(wakeup | vr_wakeup);       /* Goodbye */
 171
 172         bf53x_resume_l1_mem(memptr);
 173
 174         _enable_icplb();
 175         _enable_dcplb();
 176
 177         bfin_gpio_pm_hibernate_restore();
 178         blackfin_dma_resume();
 179
 180         local_irq_restore_hw(flags);
 181         kfree(memptr);
 182
 183         return 0;
 184 }
 185
 186 /*
 187  *      bfin_pm_valid - Tell the PM core that we only support the standby sleep
 188  *                      state
 189  *      @state:         suspend state we're checking.
 190  *
 191  */
 192 static int bfin_pm_valid(suspend_state_t state)
 193 {
 194         return (state == PM_SUSPEND_STANDBY
 195 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
 196         /*
 197          * On BF533/2/1:
 198          * If we enter Hibernate the SCKE Pin is driven Low,
 199          * so that the SDRAM enters Self Refresh Mode.
 200          * However when the reset sequence that follows hibernate
 201          * state is executed, SCKE is driven High, taking the
 202          * SDRAM out of Self Refresh.
 203          *
 204          * If you reconfigure and access the SDRAM "very quickly",
 205          * you are likely to avoid errors, otherwise the SDRAM
 206          * start losing its contents.
 207          * An external HW workaround is possible using logic gates.
 208          */
 209         || state == PM_SUSPEND_MEM
 210 #endif
 211         );
 212 }
 213
 214 /*
 215  *      bfin_pm_enter - Actually enter a sleep state.
 216  *      @state:         State we're entering.
 217  *
 218  */
 219 static int bfin_pm_enter(suspend_state_t state)
 220 {
 221         switch (state) {
 222         case PM_SUSPEND_STANDBY:
 223                 bfin_pm_suspend_standby_enter();
 224                 break;
 225         case PM_SUSPEND_MEM:
 226                 bfin_pm_suspend_mem_enter();
 227                 break;
 228         default:
 229                 return -EINVAL;
 230         }
 231
 232         return 0;
 233 }
 234
 235 struct platform_suspend_ops bfin_pm_ops = {
 236         .enter = bfin_pm_enter,
 237         .valid  = bfin_pm_valid,
 238 };
 239
 240 static int __init bfin_pm_init(void)
 241 {
 242         suspend_set_ops(&bfin_pm_ops);
 243         return 0;
 244 }
 245
 246 __initcall(bfin_pm_init);