2 * linux/arch/cris/arch-v10/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 * Copyright (C) 1999-2002 Axis Communications AB
9 #include <linux/timex.h>
10 #include <linux/time.h>
11 #include <linux/jiffies.h>
12 #include <linux/interrupt.h>
13 #include <linux/swap.h>
14 #include <linux/sched.h>
15 #include <linux/init.h>
17 #include <arch/svinto.h>
18 #include <asm/types.h>
19 #include <asm/signal.h>
21 #include <asm/delay.h>
23 #include <asm/irq_regs.h>
25 /* define this if you need to use print_timestamp */
26 /* it will make jiffies at 96 hz instead of 100 hz though */
27 #undef USE_CASCADE_TIMERS
29 extern int set_rtc_mmss(unsigned long nowtime
);
32 unsigned long get_ns_in_jiffie(void)
34 unsigned char timer_count
, t1
;
35 unsigned short presc_count
;
39 local_irq_save(flags
);
40 timer_count
= *R_TIMER0_DATA
;
41 presc_count
= *R_TIM_PRESC_STATUS
;
42 /* presc_count might be wrapped */
45 if (timer_count
!= t1
){
46 /* it wrapped, read prescaler again... */
47 presc_count
= *R_TIM_PRESC_STATUS
;
50 local_irq_restore(flags
);
51 if (presc_count
>= PRESCALE_VALUE
/2 ){
52 presc_count
= PRESCALE_VALUE
- presc_count
+ PRESCALE_VALUE
/2;
54 presc_count
= PRESCALE_VALUE
- presc_count
- PRESCALE_VALUE
/2;
57 ns
= ( (TIMER0_DIV
- timer_count
) * ((1000000000/HZ
)/TIMER0_DIV
)) +
58 ( (presc_count
) * (1000000000/PRESCALE_FREQ
));
62 unsigned long do_slow_gettimeoffset(void)
64 unsigned long count
, t1
;
65 unsigned long usec_count
= 0;
66 unsigned short presc_count
;
68 static unsigned long count_p
= TIMER0_DIV
;/* for the first call after boot */
69 static unsigned long jiffies_p
= 0;
72 * cache volatile jiffies temporarily; we have IRQs turned off.
74 unsigned long jiffies_t
;
76 /* The timer interrupt comes from Etrax timer 0. In order to get
77 * better precision, we check the current value. It might have
78 * underflowed already though.
81 #ifndef CONFIG_SVINTO_SIM
82 /* Not available in the xsim simulator. */
83 count
= *R_TIMER0_DATA
;
84 presc_count
= *R_TIM_PRESC_STATUS
;
85 /* presc_count might be wrapped */
88 /* it wrapped, read prescaler again... */
89 presc_count
= *R_TIM_PRESC_STATUS
;
100 * avoiding timer inconsistencies (they are rare, but they happen)...
101 * there are one problem that must be avoided here:
102 * 1. the timer counter underflows
104 if( jiffies_t
== jiffies_p
) {
105 if( count
> count_p
) {
106 /* Timer wrapped, use new count and prescale
107 * increase the time corresponding to one jiffie
109 usec_count
= 1000000/HZ
;
112 jiffies_p
= jiffies_t
;
114 if (presc_count
>= PRESCALE_VALUE
/2 ){
115 presc_count
= PRESCALE_VALUE
- presc_count
+ PRESCALE_VALUE
/2;
117 presc_count
= PRESCALE_VALUE
- presc_count
- PRESCALE_VALUE
/2;
119 /* Convert timer value to usec */
120 usec_count
+= ( (TIMER0_DIV
- count
) * (1000000/HZ
)/TIMER0_DIV
) +
121 (( (presc_count
) * (1000000000/PRESCALE_FREQ
))/1000);
126 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
128 * 3.10.4 Watchdog timer
130 * When the watchdog timer is started, it generates an NMI if the watchdog
131 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
132 * stopped after an additional 3.3 ms, the watchdog resets the chip.
133 * The watchdog timer is stopped after reset. The watchdog timer is controlled
134 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
135 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
136 * described in the table below:
138 * Watchdog Value written:
139 * state: To enable: To key: Operation:
140 * -------- ---------- ------- ----------
141 * stopped 0 X No effect.
142 * stopped 1 key_val Start watchdog with key = key_val.
143 * started 0 ~key Stop watchdog
144 * started 1 ~key Restart watchdog with key = ~key.
145 * started X new_key_val Change key to new_key_val.
147 * Note: '~' is the bitwise NOT operator.
151 /* right now, starting the watchdog is the same as resetting it */
152 #define start_watchdog reset_watchdog
154 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
155 static int watchdog_key
= 0; /* arbitrary number */
158 /* number of pages to consider "out of memory". it is normal that the memory
159 * is used though, so put this really low.
162 #define WATCHDOG_MIN_FREE_PAGES 8
167 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
168 /* only keep watchdog happy as long as we have memory left! */
169 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES
) {
170 /* reset the watchdog with the inverse of the old key */
171 watchdog_key
^= 0x7; /* invert key, which is 3 bits */
172 *R_WATCHDOG
= IO_FIELD(R_WATCHDOG
, key
, watchdog_key
) |
173 IO_STATE(R_WATCHDOG
, enable
, start
);
178 /* stop the watchdog - we still need the correct key */
183 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
184 watchdog_key
^= 0x7; /* invert key, which is 3 bits */
185 *R_WATCHDOG
= IO_FIELD(R_WATCHDOG
, key
, watchdog_key
) |
186 IO_STATE(R_WATCHDOG
, enable
, stop
);
192 * timer_interrupt() needs to keep up the real-time clock,
193 * as well as call the "do_timer()" routine every clocktick
196 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
198 extern void cris_do_profile(struct pt_regs
*regs
);
200 static inline irqreturn_t
201 timer_interrupt(int irq
, void *dev_id
)
203 struct pt_regs
*regs
= get_irq_regs();
204 /* acknowledge the timer irq */
206 #ifdef USE_CASCADE_TIMERS
208 IO_FIELD( R_TIMER_CTRL
, timerdiv1
, 0) |
209 IO_FIELD( R_TIMER_CTRL
, timerdiv0
, 0) |
210 IO_STATE( R_TIMER_CTRL
, i1
, clr
) |
211 IO_STATE( R_TIMER_CTRL
, tm1
, run
) |
212 IO_STATE( R_TIMER_CTRL
, clksel1
, cascade0
) |
213 IO_STATE( R_TIMER_CTRL
, i0
, clr
) |
214 IO_STATE( R_TIMER_CTRL
, tm0
, run
) |
215 IO_STATE( R_TIMER_CTRL
, clksel0
, c6250kHz
);
217 *R_TIMER_CTRL
= r_timer_ctrl_shadow
|
218 IO_STATE(R_TIMER_CTRL
, i0
, clr
);
221 /* reset watchdog otherwise it resets us! */
224 /* Update statistics. */
225 update_process_times(user_mode(regs
));
227 /* call the real timer interrupt handler */
231 cris_do_profile(regs
); /* Save profiling information */
235 /* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
236 * it needs to be IRQF_DISABLED to make the jiffies update work properly
239 static struct irqaction irq2
= {
240 .handler
= timer_interrupt
,
241 .flags
= IRQF_SHARED
| IRQF_DISABLED
,
248 /* probe for the RTC and read it if it exists
249 * Before the RTC can be probed the loops_per_usec variable needs
250 * to be initialized to make usleep work. A better value for
251 * loops_per_usec is calculated by the kernel later once the
261 /* Setup the etrax timers
262 * Base frequency is 25000 hz, divider 250 -> 100 HZ
263 * In normal mode, we use timer0, so timer1 is free. In cascade
264 * mode (which we sometimes use for debugging) both timers are used.
265 * Remember that linux/timex.h contains #defines that rely on the
266 * timer settings below (hz and divide factor) !!!
269 #ifdef USE_CASCADE_TIMERS
271 IO_FIELD( R_TIMER_CTRL
, timerdiv1
, 0) |
272 IO_FIELD( R_TIMER_CTRL
, timerdiv0
, 0) |
273 IO_STATE( R_TIMER_CTRL
, i1
, nop
) |
274 IO_STATE( R_TIMER_CTRL
, tm1
, stop_ld
) |
275 IO_STATE( R_TIMER_CTRL
, clksel1
, cascade0
) |
276 IO_STATE( R_TIMER_CTRL
, i0
, nop
) |
277 IO_STATE( R_TIMER_CTRL
, tm0
, stop_ld
) |
278 IO_STATE( R_TIMER_CTRL
, clksel0
, c6250kHz
);
280 *R_TIMER_CTRL
= r_timer_ctrl_shadow
=
281 IO_FIELD( R_TIMER_CTRL
, timerdiv1
, 0) |
282 IO_FIELD( R_TIMER_CTRL
, timerdiv0
, 0) |
283 IO_STATE( R_TIMER_CTRL
, i1
, nop
) |
284 IO_STATE( R_TIMER_CTRL
, tm1
, run
) |
285 IO_STATE( R_TIMER_CTRL
, clksel1
, cascade0
) |
286 IO_STATE( R_TIMER_CTRL
, i0
, nop
) |
287 IO_STATE( R_TIMER_CTRL
, tm0
, run
) |
288 IO_STATE( R_TIMER_CTRL
, clksel0
, c6250kHz
);
291 IO_FIELD(R_TIMER_CTRL
, timerdiv1
, 192) |
292 IO_FIELD(R_TIMER_CTRL
, timerdiv0
, TIMER0_DIV
) |
293 IO_STATE(R_TIMER_CTRL
, i1
, nop
) |
294 IO_STATE(R_TIMER_CTRL
, tm1
, stop_ld
) |
295 IO_STATE(R_TIMER_CTRL
, clksel1
, c19k2Hz
) |
296 IO_STATE(R_TIMER_CTRL
, i0
, nop
) |
297 IO_STATE(R_TIMER_CTRL
, tm0
, stop_ld
) |
298 IO_STATE(R_TIMER_CTRL
, clksel0
, flexible
);
300 *R_TIMER_CTRL
= r_timer_ctrl_shadow
=
301 IO_FIELD(R_TIMER_CTRL
, timerdiv1
, 192) |
302 IO_FIELD(R_TIMER_CTRL
, timerdiv0
, TIMER0_DIV
) |
303 IO_STATE(R_TIMER_CTRL
, i1
, nop
) |
304 IO_STATE(R_TIMER_CTRL
, tm1
, run
) |
305 IO_STATE(R_TIMER_CTRL
, clksel1
, c19k2Hz
) |
306 IO_STATE(R_TIMER_CTRL
, i0
, nop
) |
307 IO_STATE(R_TIMER_CTRL
, tm0
, run
) |
308 IO_STATE(R_TIMER_CTRL
, clksel0
, flexible
);
310 *R_TIMER_PRESCALE
= PRESCALE_VALUE
;
314 IO_STATE(R_IRQ_MASK0_SET
, timer0
, set
); /* unmask the timer irq */
316 /* now actually register the timer irq handler that calls timer_interrupt() */
318 setup_irq(2, &irq2
); /* irq 2 is the timer0 irq in etrax */
320 /* enable watchdog if we should use one */
322 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
323 printk("Enabling watchdog...\n");
326 /* If we use the hardware watchdog, we want to trap it as an NMI
327 and dump registers before it resets us. For this to happen, we
328 must set the "m" NMI enable flag (which once set, is unset only
329 when an NMI is taken).
331 The same goes for the external NMI, but that doesn't have any
332 driver or infrastructure support yet. */
336 IO_STATE(R_IRQ_MASK0_SET
, watchdog_nmi
, set
);
338 IO_STATE(R_VECT_MASK_SET
, nmi
, set
);