arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
   3  *
   4  * Author: Andy Fleming <afleming@freescale.com>
   5  *
   6  * Based on 83xx/mpc8360e_pb.c by:
   7  *         Li Yang <LeoLi@freescale.com>
   8  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   9  *
  10  * Description:
  11  * MPC85xx MDS board specific routines.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/initrd.h>
  31 #include <linux/module.h>
  32 #include <linux/fsl_devices.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_device.h>
  35 #include <linux/phy.h>
  36 #include <linux/lmb.h>
  37
  38 #include <asm/system.h>
  39 #include <asm/atomic.h>
  40 #include <asm/time.h>
  41 #include <asm/io.h>
  42 #include <asm/machdep.h>
  43 #include <asm/pci-bridge.h>
  44 #include <asm/irq.h>
  45 #include <mm/mmu_decl.h>
  46 #include <asm/prom.h>
  47 #include <asm/udbg.h>
  48 #include <sysdev/fsl_soc.h>
  49 #include <sysdev/fsl_pci.h>
  50 #include <sysdev/simple_gpio.h>
  51 #include <asm/qe.h>
  52 #include <asm/qe_ic.h>
  53 #include <asm/mpic.h>
  54 #include <asm/swiotlb.h>
  55
  56 #undef DEBUG
  57 #ifdef DEBUG
  58 #define DBG(fmt...) udbg_printf(fmt)
  59 #else
  60 #define DBG(fmt...)
  61 #endif
  62
  63 #define MV88E1111_SCR   0x10
  64 #define MV88E1111_SCR_125CLK    0x0010
  65 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
  66 {
  67         int scr;
  68         int err;
  69
  70         /* Workaround for the 125 CLK Toggle */
  71         scr = phy_read(phydev, MV88E1111_SCR);
  72
  73         if (scr < 0)
  74                 return scr;
  75
  76         err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
  77
  78         if (err)
  79                 return err;
  80
  81         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  82
  83         if (err)
  84                 return err;
  85
  86         scr = phy_read(phydev, MV88E1111_SCR);
  87
  88         if (scr < 0)
  89                 return scr;
  90
  91         err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
  92
  93         return err;
  94 }
  95
  96 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
  97 {
  98         int temp;
  99         int err;
 100
 101         /* Errata */
 102         err = phy_write(phydev,29, 0x0006);
 103
 104         if (err)
 105                 return err;
 106
 107         temp = phy_read(phydev, 30);
 108
 109         if (temp < 0)
 110                 return temp;
 111
 112         temp = (temp & (~0x8000)) | 0x4000;
 113         err = phy_write(phydev,30, temp);
 114
 115         if (err)
 116                 return err;
 117
 118         err = phy_write(phydev,29, 0x000a);
 119
 120         if (err)
 121                 return err;
 122
 123         temp = phy_read(phydev, 30);
 124
 125         if (temp < 0)
 126                 return temp;
 127
 128         temp = phy_read(phydev, 30);
 129
 130         if (temp < 0)
 131                 return temp;
 132
 133         temp &= ~0x0020;
 134
 135         err = phy_write(phydev,30,temp);
 136
 137         if (err)
 138                 return err;
 139
 140         /* Disable automatic MDI/MDIX selection */
 141         temp = phy_read(phydev, 16);
 142
 143         if (temp < 0)
 144                 return temp;
 145
 146         temp &= ~0x0060;
 147         err = phy_write(phydev,16,temp);
 148
 149         return err;
 150 }
 151
 152 /* ************************************************************************
 153  *
 154  * Setup the architecture
 155  *
 156  */
 157 #ifdef CONFIG_SMP
 158 extern void __init mpc85xx_smp_init(void);
 159 #endif
 160
 161 static void __init mpc85xx_mds_setup_arch(void)
 162 {
 163         struct device_node *np;
 164         static u8 __iomem *bcsr_regs = NULL;
 165 #ifdef CONFIG_PCI
 166         struct pci_controller *hose;
 167 #endif
 168         dma_addr_t max = 0xffffffff;
 169
 170         if (ppc_md.progress)
 171                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
 172
 173         /* Map BCSR area */
 174         np = of_find_node_by_name(NULL, "bcsr");
 175         if (np != NULL) {
 176                 struct resource res;
 177
 178                 of_address_to_resource(np, 0, &res);
 179                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
 180                 of_node_put(np);
 181         }
 182
 183 #ifdef CONFIG_PCI
 184         for_each_node_by_type(np, "pci") {
 185                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 186                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 187                         struct resource rsrc;
 188                         of_address_to_resource(np, 0, &rsrc);
 189                         if ((rsrc.start & 0xfffff) == 0x8000)
 190                                 fsl_add_bridge(np, 1);
 191                         else
 192                                 fsl_add_bridge(np, 0);
 193
 194                         hose = pci_find_hose_for_OF_device(np);
 195                         max = min(max, hose->dma_window_base_cur +
 196                                         hose->dma_window_size);
 197                 }
 198         }
 199 #endif
 200
 201 #ifdef CONFIG_SMP
 202         mpc85xx_smp_init();
 203 #endif
 204
 205 #ifdef CONFIG_QUICC_ENGINE
 206         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
 207         if (!np) {
 208                 np = of_find_node_by_name(NULL, "qe");
 209                 if (!np)
 210                         return;
 211         }
 212
 213         qe_reset();
 214         of_node_put(np);
 215
 216         np = of_find_node_by_name(NULL, "par_io");
 217         if (np) {
 218                 struct device_node *ucc;
 219
 220                 par_io_init(np);
 221                 of_node_put(np);
 222
 223                 for_each_node_by_name(ucc, "ucc")
 224                         par_io_of_config(ucc);
 225         }
 226
 227         if (bcsr_regs) {
 228                 if (machine_is(mpc8568_mds)) {
 229 #define BCSR_UCC1_GETH_EN       (0x1 << 7)
 230 #define BCSR_UCC2_GETH_EN       (0x1 << 7)
 231 #define BCSR_UCC1_MODE_MSK      (0x3 << 4)
 232 #define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 233
 234                         /* Turn off UCC1 & UCC2 */
 235                         clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 236                         clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 237
 238                         /* Mode is RGMII, all bits clear */
 239                         clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
 240                                                  BCSR_UCC2_MODE_MSK);
 241
 242                         /* Turn UCC1 & UCC2 on */
 243                         setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 244                         setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 245                 } else if (machine_is(mpc8569_mds)) {
 246 #define BCSR7_UCC12_GETHnRST    (0x1 << 2)
 247 #define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
 248 #define BCSR_UCC_RGMII          (0x1 << 6)
 249 #define BCSR_UCC_RTBI           (0x1 << 5)
 250                         /*
 251                          * U-Boot mangles interrupt polarity for Marvell PHYs,
 252                          * so reset built-in and UEM Marvell PHYs, this puts
 253                          * the PHYs into their normal state.
 254                          */
 255                         clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
 256                         setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 257
 258                         setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
 259                         clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 260
 261                         for (np = NULL; (np = of_find_compatible_node(np,
 262                                                         "network",
 263                                                         "ucc_geth")) != NULL;) {
 264                                 const unsigned int *prop;
 265                                 int ucc_num;
 266
 267                                 prop = of_get_property(np, "cell-index", NULL);
 268                                 if (prop == NULL)
 269                                         continue;
 270
 271                                 ucc_num = *prop - 1;
 272
 273                                 prop = of_get_property(np, "phy-connection-type", NULL);
 274                                 if (prop == NULL)
 275                                         continue;
 276
 277                                 if (strcmp("rtbi", (const char *)prop) == 0)
 278                                         clrsetbits_8(&bcsr_regs[7 + ucc_num],
 279                                                 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
 280                         }
 281
 282                 } else if (machine_is(p1021_mds)) {
 283 #define BCSR11_ENET_MICRST     (0x1 << 5)
 284                         /* Reset Micrel PHY */
 285                         clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
 286                         setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
 287                 }
 288
 289                 iounmap(bcsr_regs);
 290         }
 291
 292         if (machine_is(p1021_mds)) {
 293 #define MPC85xx_PMUXCR_OFFSET           0x60
 294 #define MPC85xx_PMUXCR_QE0              0x00008000
 295 #define MPC85xx_PMUXCR_QE3              0x00001000
 296 #define MPC85xx_PMUXCR_QE9              0x00000040
 297 #define MPC85xx_PMUXCR_QE12             0x00000008
 298                 static __be32 __iomem *pmuxcr;
 299
 300                 np = of_find_node_by_name(NULL, "global-utilities");
 301
 302                 if (np) {
 303                         pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
 304
 305                         if (!pmuxcr)
 306                                 printk(KERN_EMERG "Error: Alternate function"
 307                                         " signal multiplex control register not"
 308                                         " mapped!\n");
 309                         else
 310                         /* P1021 has pins muxed for QE and other functions. To
 311                          * enable QE UEC mode, we need to set bit QE0 for UCC1
 312                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
 313                          * and QE12 for QE MII management singals in PMUXCR
 314                          * register.
 315                          */
 316                                 setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
 317                                                   MPC85xx_PMUXCR_QE3 |
 318                                                   MPC85xx_PMUXCR_QE9 |
 319                                                   MPC85xx_PMUXCR_QE12);
 320
 321                         of_node_put(np);
 322                 }
 323
 324         }
 325 #endif  /* CONFIG_QUICC_ENGINE */
 326
 327 #ifdef CONFIG_SWIOTLB
 328         if (lmb_end_of_DRAM() > max) {
 329                 ppc_swiotlb_enable = 1;
 330                 set_pci_dma_ops(&swiotlb_dma_ops);
 331                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
 332         }
 333 #endif
 334 }
 335
 336
 337 static int __init board_fixups(void)
 338 {
 339         char phy_id[20];
 340         char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
 341         struct device_node *mdio;
 342         struct resource res;
 343         int i;
 344
 345         for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
 346                 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
 347
 348                 of_address_to_resource(mdio, 0, &res);
 349                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
 350                         (unsigned long long)res.start, 1);
 351
 352                 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
 353                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
 354
 355                 /* Register a workaround for errata */
 356                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
 357                         (unsigned long long)res.start, 7);
 358                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
 359
 360                 of_node_put(mdio);
 361         }
 362
 363         return 0;
 364 }
 365 machine_arch_initcall(mpc8568_mds, board_fixups);
 366 machine_arch_initcall(mpc8569_mds, board_fixups);
 367
 368 static struct of_device_id mpc85xx_ids[] = {
 369         { .type = "soc", },
 370         { .compatible = "soc", },
 371         { .compatible = "simple-bus", },
 372         { .type = "qe", },
 373         { .compatible = "fsl,qe", },
 374         { .compatible = "gianfar", },
 375         { .compatible = "fsl,rapidio-delta", },
 376         { .compatible = "fsl,mpc8548-guts", },
 377         { .compatible = "gpio-leds", },
 378         {},
 379 };
 380
 381 static struct of_device_id p1021_ids[] = {
 382         { .type = "soc", },
 383         { .compatible = "soc", },
 384         { .compatible = "simple-bus", },
 385         { .type = "qe", },
 386         { .compatible = "fsl,qe", },
 387         { .compatible = "gianfar", },
 388         {},
 389 };
 390
 391 static int __init mpc85xx_publish_devices(void)
 392 {
 393         if (machine_is(mpc8568_mds))
 394                 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
 395         if (machine_is(mpc8569_mds))
 396                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 397
 398         /* Publish the QE devices */
 399         of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
 400
 401         return 0;
 402 }
 403
 404 static int __init p1021_publish_devices(void)
 405 {
 406         /* Publish the QE devices */
 407         of_platform_bus_probe(NULL, p1021_ids, NULL);
 408
 409         return 0;
 410 }
 411
 412 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
 413 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
 414 machine_device_initcall(p1021_mds, p1021_publish_devices);
 415
 416 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
 417 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
 418 machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
 419
 420 static void __init mpc85xx_mds_pic_init(void)
 421 {
 422         struct mpic *mpic;
 423         struct resource r;
 424         struct device_node *np = NULL;
 425
 426         np = of_find_node_by_type(NULL, "open-pic");
 427         if (!np)
 428                 return;
 429
 430         if (of_address_to_resource(np, 0, &r)) {
 431                 printk(KERN_ERR "Failed to map mpic register space\n");
 432                 of_node_put(np);
 433                 return;
 434         }
 435
 436         mpic = mpic_alloc(np, r.start,
 437                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
 438                         MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
 439                         0, 256, " OpenPIC  ");
 440         BUG_ON(mpic == NULL);
 441         of_node_put(np);
 442
 443         mpic_init(mpic);
 444
 445 #ifdef CONFIG_QUICC_ENGINE
 446         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 447         if (!np) {
 448                 np = of_find_node_by_type(NULL, "qeic");
 449                 if (!np)
 450                         return;
 451         }
 452         if (machine_is(p1021_mds))
 453                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
 454                                 qe_ic_cascade_high_mpic);
 455         else
 456                 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
 457         of_node_put(np);
 458 #endif                          /* CONFIG_QUICC_ENGINE */
 459 }
 460
 461 static int __init mpc85xx_mds_probe(void)
 462 {
 463         unsigned long root = of_get_flat_dt_root();
 464
 465         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 466 }
 467
 468 define_machine(mpc8568_mds) {
 469         .name           = "MPC8568 MDS",
 470         .probe          = mpc85xx_mds_probe,
 471         .setup_arch     = mpc85xx_mds_setup_arch,
 472         .init_IRQ       = mpc85xx_mds_pic_init,
 473         .get_irq        = mpic_get_irq,
 474         .restart        = fsl_rstcr_restart,
 475         .calibrate_decr = generic_calibrate_decr,
 476         .progress       = udbg_progress,
 477 #ifdef CONFIG_PCI
 478         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 479 #endif
 480 };
 481
 482 static int __init mpc8569_mds_probe(void)
 483 {
 484         unsigned long root = of_get_flat_dt_root();
 485
 486         return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
 487 }
 488
 489 define_machine(mpc8569_mds) {
 490         .name           = "MPC8569 MDS",
 491         .probe          = mpc8569_mds_probe,
 492         .setup_arch     = mpc85xx_mds_setup_arch,
 493         .init_IRQ       = mpc85xx_mds_pic_init,
 494         .get_irq        = mpic_get_irq,
 495         .restart        = fsl_rstcr_restart,
 496         .calibrate_decr = generic_calibrate_decr,
 497         .progress       = udbg_progress,
 498 #ifdef CONFIG_PCI
 499         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 500 #endif
 501 };
 502
 503 static int __init p1021_mds_probe(void)
 504 {
 505         unsigned long root = of_get_flat_dt_root();
 506
 507         return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
 508
 509 }
 510
 511 define_machine(p1021_mds) {
 512         .name           = "P1021 MDS",
 513         .probe          = p1021_mds_probe,
 514         .setup_arch     = mpc85xx_mds_setup_arch,
 515         .init_IRQ       = mpc85xx_mds_pic_init,
 516         .get_irq        = mpic_get_irq,
 517         .restart        = fsl_rstcr_restart,
 518         .calibrate_decr = generic_calibrate_decr,
 519         .progress       = udbg_progress,
 520 #ifdef CONFIG_PCI
 521         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 522 #endif
 523 };
 524