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Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs
[linux/fpc-iii.git] / drivers / net / bnx2.c
blob949d7a9dcf9269b4ccef78703ffb7e1701767237
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/bitops.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33 #include <linux/delay.h>
34 #include <asm/byteorder.h>
35 #include <asm/page.h>
36 #include <linux/time.h>
37 #include <linux/ethtool.h>
38 #include <linux/mii.h>
39 #include <linux/if_vlan.h>
40 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
41 #define BCM_VLAN 1
42 #endif
43 #include <net/ip.h>
44 #include <net/tcp.h>
45 #include <net/checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/prefetch.h>
49 #include <linux/cache.h>
50 #include <linux/firmware.h>
51 #include <linux/log2.h>
52
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54 #define BCM_CNIC 1
55 #include "cnic_if.h"
56 #endif
57 #include "bnx2.h"
58 #include "bnx2_fw.h"
59
60 #define DRV_MODULE_NAME "bnx2"
61 #define DRV_MODULE_VERSION "2.0.15"
62 #define DRV_MODULE_RELDATE "May 4, 2010"
63 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
64 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
65 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j15.fw"
66 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
67 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
68
69 #define RUN_AT(x) (jiffies + (x))
70
71 /* Time in jiffies before concluding the transmitter is hung. */
72 #define TX_TIMEOUT (5*HZ)
73
74 static char version[] __devinitdata =
75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
78 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
79 MODULE_LICENSE("GPL");
80 MODULE_VERSION(DRV_MODULE_VERSION);
81 MODULE_FIRMWARE(FW_MIPS_FILE_06);
82 MODULE_FIRMWARE(FW_RV2P_FILE_06);
83 MODULE_FIRMWARE(FW_MIPS_FILE_09);
84 MODULE_FIRMWARE(FW_RV2P_FILE_09);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
86
87 static int disable_msi = 0;
88
89 module_param(disable_msi, int, 0);
90 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
91
92 typedef enum {
93 BCM5706 = 0,
94 NC370T,
95 NC370I,
96 BCM5706S,
97 NC370F,
98 BCM5708,
99 BCM5708S,
100 BCM5709,
101 BCM5709S,
102 BCM5716,
103 BCM5716S,
104 } board_t;
105
106 /* indexed by board_t, above */
107 static struct {
108 char *name;
109 } board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
121 };
122
123 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
146 { 0, }
147 };
148
149 static const struct flash_spec flash_table[] =
150 {
151 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
153 /* Slow EEPROM */
154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 "EEPROM - slow"},
158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 "Entry 0001"},
163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 0100"},
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
196 /* Fast EEPROM */
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 "EEPROM - fast"},
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1001"},
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1010"},
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1100"},
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1101"},
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
236 };
237
238 static const struct flash_spec flash_5709 = {
239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
245 };
246
247 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248
249 static void bnx2_init_napi(struct bnx2 *bp);
250 static void bnx2_del_napi(struct bnx2 *bp);
251
252 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
253 {
254 u32 diff;
255
256 smp_mb();
257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
261 diff = txr->tx_prod - txr->tx_cons;
262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
267 return (bp->tx_ring_size - diff);
268 }
269
270 static u32
271 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272 {
273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
280 }
281
282 static void
283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284 {
285 spin_lock_bh(&bp->indirect_lock);
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
288 spin_unlock_bh(&bp->indirect_lock);
289 }
290
291 static void
292 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293 {
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295 }
296
297 static u32
298 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299 {
300 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
301 }
302
303 static void
304 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305 {
306 offset += cid_addr;
307 spin_lock_bh(&bp->indirect_lock);
308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
324 spin_unlock_bh(&bp->indirect_lock);
325 }
326
327 #ifdef BCM_CNIC
328 static int
329 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330 {
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348 }
349
350 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351 {
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375 }
376
377 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379 {
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
389 bp->cnic_data = data;
390 rcu_assign_pointer(bp->cnic_ops, ops);
391
392 cp->num_irq = 0;
393 cp->drv_state = CNIC_DRV_STATE_REGD;
394
395 bnx2_setup_cnic_irq_info(bp);
396
397 return 0;
398 }
399
400 static int bnx2_unregister_cnic(struct net_device *dev)
401 {
402 struct bnx2 *bp = netdev_priv(dev);
403 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
405
406 mutex_lock(&bp->cnic_lock);
407 cp->drv_state = 0;
408 bnapi->cnic_present = 0;
409 rcu_assign_pointer(bp->cnic_ops, NULL);
410 mutex_unlock(&bp->cnic_lock);
411 synchronize_rcu();
412 return 0;
413 }
414
415 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
416 {
417 struct bnx2 *bp = netdev_priv(dev);
418 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
419
420 cp->drv_owner = THIS_MODULE;
421 cp->chip_id = bp->chip_id;
422 cp->pdev = bp->pdev;
423 cp->io_base = bp->regview;
424 cp->drv_ctl = bnx2_drv_ctl;
425 cp->drv_register_cnic = bnx2_register_cnic;
426 cp->drv_unregister_cnic = bnx2_unregister_cnic;
427
428 return cp;
429 }
430 EXPORT_SYMBOL(bnx2_cnic_probe);
431
432 static void
433 bnx2_cnic_stop(struct bnx2 *bp)
434 {
435 struct cnic_ops *c_ops;
436 struct cnic_ctl_info info;
437
438 mutex_lock(&bp->cnic_lock);
439 c_ops = bp->cnic_ops;
440 if (c_ops) {
441 info.cmd = CNIC_CTL_STOP_CMD;
442 c_ops->cnic_ctl(bp->cnic_data, &info);
443 }
444 mutex_unlock(&bp->cnic_lock);
445 }
446
447 static void
448 bnx2_cnic_start(struct bnx2 *bp)
449 {
450 struct cnic_ops *c_ops;
451 struct cnic_ctl_info info;
452
453 mutex_lock(&bp->cnic_lock);
454 c_ops = bp->cnic_ops;
455 if (c_ops) {
456 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
457 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
458
459 bnapi->cnic_tag = bnapi->last_status_idx;
460 }
461 info.cmd = CNIC_CTL_START_CMD;
462 c_ops->cnic_ctl(bp->cnic_data, &info);
463 }
464 mutex_unlock(&bp->cnic_lock);
465 }
466
467 #else
468
469 static void
470 bnx2_cnic_stop(struct bnx2 *bp)
471 {
472 }
473
474 static void
475 bnx2_cnic_start(struct bnx2 *bp)
476 {
477 }
478
479 #endif
480
481 static int
482 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
483 {
484 u32 val1;
485 int i, ret;
486
487 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
488 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
489 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
490
491 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
492 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
493
494 udelay(40);
495 }
496
497 val1 = (bp->phy_addr << 21) | (reg << 16) |
498 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
499 BNX2_EMAC_MDIO_COMM_START_BUSY;
500 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
501
502 for (i = 0; i < 50; i++) {
503 udelay(10);
504
505 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
506 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
507 udelay(5);
508
509 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
510 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
511
512 break;
513 }
514 }
515
516 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
517 *val = 0x0;
518 ret = -EBUSY;
519 }
520 else {
521 *val = val1;
522 ret = 0;
523 }
524
525 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
526 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
527 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
528
529 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
530 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
531
532 udelay(40);
533 }
534
535 return ret;
536 }
537
538 static int
539 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
540 {
541 u32 val1;
542 int i, ret;
543
544 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
545 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
546 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
547
548 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
549 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
550
551 udelay(40);
552 }
553
554 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
555 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
556 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
557 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
558
559 for (i = 0; i < 50; i++) {
560 udelay(10);
561
562 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
563 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
564 udelay(5);
565 break;
566 }
567 }
568
569 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
570 ret = -EBUSY;
571 else
572 ret = 0;
573
574 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
575 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
576 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
577
578 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
579 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
580
581 udelay(40);
582 }
583
584 return ret;
585 }
586
587 static void
588 bnx2_disable_int(struct bnx2 *bp)
589 {
590 int i;
591 struct bnx2_napi *bnapi;
592
593 for (i = 0; i < bp->irq_nvecs; i++) {
594 bnapi = &bp->bnx2_napi[i];
595 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
596 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
597 }
598 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
599 }
600
601 static void
602 bnx2_enable_int(struct bnx2 *bp)
603 {
604 int i;
605 struct bnx2_napi *bnapi;
606
607 for (i = 0; i < bp->irq_nvecs; i++) {
608 bnapi = &bp->bnx2_napi[i];
609
610 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
611 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
612 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
613 bnapi->last_status_idx);
614
615 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
616 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
617 bnapi->last_status_idx);
618 }
619 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
620 }
621
622 static void
623 bnx2_disable_int_sync(struct bnx2 *bp)
624 {
625 int i;
626
627 atomic_inc(&bp->intr_sem);
628 if (!netif_running(bp->dev))
629 return;
630
631 bnx2_disable_int(bp);
632 for (i = 0; i < bp->irq_nvecs; i++)
633 synchronize_irq(bp->irq_tbl[i].vector);
634 }
635
636 static void
637 bnx2_napi_disable(struct bnx2 *bp)
638 {
639 int i;
640
641 for (i = 0; i < bp->irq_nvecs; i++)
642 napi_disable(&bp->bnx2_napi[i].napi);
643 }
644
645 static void
646 bnx2_napi_enable(struct bnx2 *bp)
647 {
648 int i;
649
650 for (i = 0; i < bp->irq_nvecs; i++)
651 napi_enable(&bp->bnx2_napi[i].napi);
652 }
653
654 static void
655 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
656 {
657 if (stop_cnic)
658 bnx2_cnic_stop(bp);
659 if (netif_running(bp->dev)) {
660 bnx2_napi_disable(bp);
661 netif_tx_disable(bp->dev);
662 }
663 bnx2_disable_int_sync(bp);
664 netif_carrier_off(bp->dev); /* prevent tx timeout */
665 }
666
667 static void
668 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
669 {
670 if (atomic_dec_and_test(&bp->intr_sem)) {
671 if (netif_running(bp->dev)) {
672 netif_tx_wake_all_queues(bp->dev);
673 spin_lock_bh(&bp->phy_lock);
674 if (bp->link_up)
675 netif_carrier_on(bp->dev);
676 spin_unlock_bh(&bp->phy_lock);
677 bnx2_napi_enable(bp);
678 bnx2_enable_int(bp);
679 if (start_cnic)
680 bnx2_cnic_start(bp);
681 }
682 }
683 }
684
685 static void
686 bnx2_free_tx_mem(struct bnx2 *bp)
687 {
688 int i;
689
690 for (i = 0; i < bp->num_tx_rings; i++) {
691 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
692 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
693
694 if (txr->tx_desc_ring) {
695 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
696 txr->tx_desc_ring,
697 txr->tx_desc_mapping);
698 txr->tx_desc_ring = NULL;
699 }
700 kfree(txr->tx_buf_ring);
701 txr->tx_buf_ring = NULL;
702 }
703 }
704
705 static void
706 bnx2_free_rx_mem(struct bnx2 *bp)
707 {
708 int i;
709
710 for (i = 0; i < bp->num_rx_rings; i++) {
711 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
712 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
713 int j;
714
715 for (j = 0; j < bp->rx_max_ring; j++) {
716 if (rxr->rx_desc_ring[j])
717 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
718 rxr->rx_desc_ring[j],
719 rxr->rx_desc_mapping[j]);
720 rxr->rx_desc_ring[j] = NULL;
721 }
722 vfree(rxr->rx_buf_ring);
723 rxr->rx_buf_ring = NULL;
724
725 for (j = 0; j < bp->rx_max_pg_ring; j++) {
726 if (rxr->rx_pg_desc_ring[j])
727 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
728 rxr->rx_pg_desc_ring[j],
729 rxr->rx_pg_desc_mapping[j]);
730 rxr->rx_pg_desc_ring[j] = NULL;
731 }
732 vfree(rxr->rx_pg_ring);
733 rxr->rx_pg_ring = NULL;
734 }
735 }
736
737 static int
738 bnx2_alloc_tx_mem(struct bnx2 *bp)
739 {
740 int i;
741
742 for (i = 0; i < bp->num_tx_rings; i++) {
743 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
744 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
745
746 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
747 if (txr->tx_buf_ring == NULL)
748 return -ENOMEM;
749
750 txr->tx_desc_ring =
751 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
752 &txr->tx_desc_mapping);
753 if (txr->tx_desc_ring == NULL)
754 return -ENOMEM;
755 }
756 return 0;
757 }
758
759 static int
760 bnx2_alloc_rx_mem(struct bnx2 *bp)
761 {
762 int i;
763
764 for (i = 0; i < bp->num_rx_rings; i++) {
765 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
766 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
767 int j;
768
769 rxr->rx_buf_ring =
770 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
771 if (rxr->rx_buf_ring == NULL)
772 return -ENOMEM;
773
774 memset(rxr->rx_buf_ring, 0,
775 SW_RXBD_RING_SIZE * bp->rx_max_ring);
776
777 for (j = 0; j < bp->rx_max_ring; j++) {
778 rxr->rx_desc_ring[j] =
779 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
780 &rxr->rx_desc_mapping[j]);
781 if (rxr->rx_desc_ring[j] == NULL)
782 return -ENOMEM;
783
784 }
785
786 if (bp->rx_pg_ring_size) {
787 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
788 bp->rx_max_pg_ring);
789 if (rxr->rx_pg_ring == NULL)
790 return -ENOMEM;
791
792 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
793 bp->rx_max_pg_ring);
794 }
795
796 for (j = 0; j < bp->rx_max_pg_ring; j++) {
797 rxr->rx_pg_desc_ring[j] =
798 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
799 &rxr->rx_pg_desc_mapping[j]);
800 if (rxr->rx_pg_desc_ring[j] == NULL)
801 return -ENOMEM;
802
803 }
804 }
805 return 0;
806 }
807
808 static void
809 bnx2_free_mem(struct bnx2 *bp)
810 {
811 int i;
812 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
813
814 bnx2_free_tx_mem(bp);
815 bnx2_free_rx_mem(bp);
816
817 for (i = 0; i < bp->ctx_pages; i++) {
818 if (bp->ctx_blk[i]) {
819 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
820 bp->ctx_blk[i],
821 bp->ctx_blk_mapping[i]);
822 bp->ctx_blk[i] = NULL;
823 }
824 }
825 if (bnapi->status_blk.msi) {
826 pci_free_consistent(bp->pdev, bp->status_stats_size,
827 bnapi->status_blk.msi,
828 bp->status_blk_mapping);
829 bnapi->status_blk.msi = NULL;
830 bp->stats_blk = NULL;
831 }
832 }
833
834 static int
835 bnx2_alloc_mem(struct bnx2 *bp)
836 {
837 int i, status_blk_size, err;
838 struct bnx2_napi *bnapi;
839 void *status_blk;
840
841 /* Combine status and statistics blocks into one allocation. */
842 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
843 if (bp->flags & BNX2_FLAG_MSIX_CAP)
844 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
845 BNX2_SBLK_MSIX_ALIGN_SIZE);
846 bp->status_stats_size = status_blk_size +
847 sizeof(struct statistics_block);
848
849 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
850 &bp->status_blk_mapping);
851 if (status_blk == NULL)
852 goto alloc_mem_err;
853
854 memset(status_blk, 0, bp->status_stats_size);
855
856 bnapi = &bp->bnx2_napi[0];
857 bnapi->status_blk.msi = status_blk;
858 bnapi->hw_tx_cons_ptr =
859 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
860 bnapi->hw_rx_cons_ptr =
861 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
862 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
863 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
864 struct status_block_msix *sblk;
865
866 bnapi = &bp->bnx2_napi[i];
867
868 sblk = (void *) (status_blk +
869 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
870 bnapi->status_blk.msix = sblk;
871 bnapi->hw_tx_cons_ptr =
872 &sblk->status_tx_quick_consumer_index;
873 bnapi->hw_rx_cons_ptr =
874 &sblk->status_rx_quick_consumer_index;
875 bnapi->int_num = i << 24;
876 }
877 }
878
879 bp->stats_blk = status_blk + status_blk_size;
880
881 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
882
883 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
884 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
885 if (bp->ctx_pages == 0)
886 bp->ctx_pages = 1;
887 for (i = 0; i < bp->ctx_pages; i++) {
888 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
889 BCM_PAGE_SIZE,
890 &bp->ctx_blk_mapping[i]);
891 if (bp->ctx_blk[i] == NULL)
892 goto alloc_mem_err;
893 }
894 }
895
896 err = bnx2_alloc_rx_mem(bp);
897 if (err)
898 goto alloc_mem_err;
899
900 err = bnx2_alloc_tx_mem(bp);
901 if (err)
902 goto alloc_mem_err;
903
904 return 0;
905
906 alloc_mem_err:
907 bnx2_free_mem(bp);
908 return -ENOMEM;
909 }
910
911 static void
912 bnx2_report_fw_link(struct bnx2 *bp)
913 {
914 u32 fw_link_status = 0;
915
916 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
917 return;
918
919 if (bp->link_up) {
920 u32 bmsr;
921
922 switch (bp->line_speed) {
923 case SPEED_10:
924 if (bp->duplex == DUPLEX_HALF)
925 fw_link_status = BNX2_LINK_STATUS_10HALF;
926 else
927 fw_link_status = BNX2_LINK_STATUS_10FULL;
928 break;
929 case SPEED_100:
930 if (bp->duplex == DUPLEX_HALF)
931 fw_link_status = BNX2_LINK_STATUS_100HALF;
932 else
933 fw_link_status = BNX2_LINK_STATUS_100FULL;
934 break;
935 case SPEED_1000:
936 if (bp->duplex == DUPLEX_HALF)
937 fw_link_status = BNX2_LINK_STATUS_1000HALF;
938 else
939 fw_link_status = BNX2_LINK_STATUS_1000FULL;
940 break;
941 case SPEED_2500:
942 if (bp->duplex == DUPLEX_HALF)
943 fw_link_status = BNX2_LINK_STATUS_2500HALF;
944 else
945 fw_link_status = BNX2_LINK_STATUS_2500FULL;
946 break;
947 }
948
949 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
950
951 if (bp->autoneg) {
952 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
953
954 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
955 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
956
957 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
958 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
959 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
960 else
961 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
962 }
963 }
964 else
965 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
966
967 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
968 }
969
970 static char *
971 bnx2_xceiver_str(struct bnx2 *bp)
972 {
973 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
974 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
975 "Copper"));
976 }
977
978 static void
979 bnx2_report_link(struct bnx2 *bp)
980 {
981 if (bp->link_up) {
982 netif_carrier_on(bp->dev);
983 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
984 bnx2_xceiver_str(bp),
985 bp->line_speed,
986 bp->duplex == DUPLEX_FULL ? "full" : "half");
987
988 if (bp->flow_ctrl) {
989 if (bp->flow_ctrl & FLOW_CTRL_RX) {
990 pr_cont(", receive ");
991 if (bp->flow_ctrl & FLOW_CTRL_TX)
992 pr_cont("& transmit ");
993 }
994 else {
995 pr_cont(", transmit ");
996 }
997 pr_cont("flow control ON");
998 }
999 pr_cont("\n");
1000 } else {
1001 netif_carrier_off(bp->dev);
1002 netdev_err(bp->dev, "NIC %s Link is Down\n",
1003 bnx2_xceiver_str(bp));
1004 }
1005
1006 bnx2_report_fw_link(bp);
1007 }
1008
1009 static void
1010 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1011 {
1012 u32 local_adv, remote_adv;
1013
1014 bp->flow_ctrl = 0;
1015 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1016 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1017
1018 if (bp->duplex == DUPLEX_FULL) {
1019 bp->flow_ctrl = bp->req_flow_ctrl;
1020 }
1021 return;
1022 }
1023
1024 if (bp->duplex != DUPLEX_FULL) {
1025 return;
1026 }
1027
1028 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1029 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1030 u32 val;
1031
1032 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1033 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1034 bp->flow_ctrl |= FLOW_CTRL_TX;
1035 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1036 bp->flow_ctrl |= FLOW_CTRL_RX;
1037 return;
1038 }
1039
1040 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1041 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1042
1043 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1044 u32 new_local_adv = 0;
1045 u32 new_remote_adv = 0;
1046
1047 if (local_adv & ADVERTISE_1000XPAUSE)
1048 new_local_adv |= ADVERTISE_PAUSE_CAP;
1049 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1050 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1051 if (remote_adv & ADVERTISE_1000XPAUSE)
1052 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1053 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1054 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1055
1056 local_adv = new_local_adv;
1057 remote_adv = new_remote_adv;
1058 }
1059
1060 /* See Table 28B-3 of 802.3ab-1999 spec. */
1061 if (local_adv & ADVERTISE_PAUSE_CAP) {
1062 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1063 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1064 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1065 }
1066 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1067 bp->flow_ctrl = FLOW_CTRL_RX;
1068 }
1069 }
1070 else {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073 }
1074 }
1075 }
1076 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1077 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1078 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1079
1080 bp->flow_ctrl = FLOW_CTRL_TX;
1081 }
1082 }
1083 }
1084
1085 static int
1086 bnx2_5709s_linkup(struct bnx2 *bp)
1087 {
1088 u32 val, speed;
1089
1090 bp->link_up = 1;
1091
1092 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1093 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1094 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1095
1096 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1097 bp->line_speed = bp->req_line_speed;
1098 bp->duplex = bp->req_duplex;
1099 return 0;
1100 }
1101 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1102 switch (speed) {
1103 case MII_BNX2_GP_TOP_AN_SPEED_10:
1104 bp->line_speed = SPEED_10;
1105 break;
1106 case MII_BNX2_GP_TOP_AN_SPEED_100:
1107 bp->line_speed = SPEED_100;
1108 break;
1109 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1110 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1111 bp->line_speed = SPEED_1000;
1112 break;
1113 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1114 bp->line_speed = SPEED_2500;
1115 break;
1116 }
1117 if (val & MII_BNX2_GP_TOP_AN_FD)
1118 bp->duplex = DUPLEX_FULL;
1119 else
1120 bp->duplex = DUPLEX_HALF;
1121 return 0;
1122 }
1123
1124 static int
1125 bnx2_5708s_linkup(struct bnx2 *bp)
1126 {
1127 u32 val;
1128
1129 bp->link_up = 1;
1130 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1131 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1132 case BCM5708S_1000X_STAT1_SPEED_10:
1133 bp->line_speed = SPEED_10;
1134 break;
1135 case BCM5708S_1000X_STAT1_SPEED_100:
1136 bp->line_speed = SPEED_100;
1137 break;
1138 case BCM5708S_1000X_STAT1_SPEED_1G:
1139 bp->line_speed = SPEED_1000;
1140 break;
1141 case BCM5708S_1000X_STAT1_SPEED_2G5:
1142 bp->line_speed = SPEED_2500;
1143 break;
1144 }
1145 if (val & BCM5708S_1000X_STAT1_FD)
1146 bp->duplex = DUPLEX_FULL;
1147 else
1148 bp->duplex = DUPLEX_HALF;
1149
1150 return 0;
1151 }
1152
1153 static int
1154 bnx2_5706s_linkup(struct bnx2 *bp)
1155 {
1156 u32 bmcr, local_adv, remote_adv, common;
1157
1158 bp->link_up = 1;
1159 bp->line_speed = SPEED_1000;
1160
1161 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1162 if (bmcr & BMCR_FULLDPLX) {
1163 bp->duplex = DUPLEX_FULL;
1164 }
1165 else {
1166 bp->duplex = DUPLEX_HALF;
1167 }
1168
1169 if (!(bmcr & BMCR_ANENABLE)) {
1170 return 0;
1171 }
1172
1173 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1174 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1175
1176 common = local_adv & remote_adv;
1177 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1178
1179 if (common & ADVERTISE_1000XFULL) {
1180 bp->duplex = DUPLEX_FULL;
1181 }
1182 else {
1183 bp->duplex = DUPLEX_HALF;
1184 }
1185 }
1186
1187 return 0;
1188 }
1189
1190 static int
1191 bnx2_copper_linkup(struct bnx2 *bp)
1192 {
1193 u32 bmcr;
1194
1195 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1196 if (bmcr & BMCR_ANENABLE) {
1197 u32 local_adv, remote_adv, common;
1198
1199 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1200 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1201
1202 common = local_adv & (remote_adv >> 2);
1203 if (common & ADVERTISE_1000FULL) {
1204 bp->line_speed = SPEED_1000;
1205 bp->duplex = DUPLEX_FULL;
1206 }
1207 else if (common & ADVERTISE_1000HALF) {
1208 bp->line_speed = SPEED_1000;
1209 bp->duplex = DUPLEX_HALF;
1210 }
1211 else {
1212 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1213 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1214
1215 common = local_adv & remote_adv;
1216 if (common & ADVERTISE_100FULL) {
1217 bp->line_speed = SPEED_100;
1218 bp->duplex = DUPLEX_FULL;
1219 }
1220 else if (common & ADVERTISE_100HALF) {
1221 bp->line_speed = SPEED_100;
1222 bp->duplex = DUPLEX_HALF;
1223 }
1224 else if (common & ADVERTISE_10FULL) {
1225 bp->line_speed = SPEED_10;
1226 bp->duplex = DUPLEX_FULL;
1227 }
1228 else if (common & ADVERTISE_10HALF) {
1229 bp->line_speed = SPEED_10;
1230 bp->duplex = DUPLEX_HALF;
1231 }
1232 else {
1233 bp->line_speed = 0;
1234 bp->link_up = 0;
1235 }
1236 }
1237 }
1238 else {
1239 if (bmcr & BMCR_SPEED100) {
1240 bp->line_speed = SPEED_100;
1241 }
1242 else {
1243 bp->line_speed = SPEED_10;
1244 }
1245 if (bmcr & BMCR_FULLDPLX) {
1246 bp->duplex = DUPLEX_FULL;
1247 }
1248 else {
1249 bp->duplex = DUPLEX_HALF;
1250 }
1251 }
1252
1253 return 0;
1254 }
1255
1256 static void
1257 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1258 {
1259 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1260
1261 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1262 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1263 val |= 0x02 << 8;
1264
1265 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1266 u32 lo_water, hi_water;
1267
1268 if (bp->flow_ctrl & FLOW_CTRL_TX)
1269 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1270 else
1271 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1272 if (lo_water >= bp->rx_ring_size)
1273 lo_water = 0;
1274
1275 hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
1276
1277 if (hi_water <= lo_water)
1278 lo_water = 0;
1279
1280 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1281 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1282
1283 if (hi_water > 0xf)
1284 hi_water = 0xf;
1285 else if (hi_water == 0)
1286 lo_water = 0;
1287 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1288 }
1289 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1290 }
1291
1292 static void
1293 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1294 {
1295 int i;
1296 u32 cid;
1297
1298 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1299 if (i == 1)
1300 cid = RX_RSS_CID;
1301 bnx2_init_rx_context(bp, cid);
1302 }
1303 }
1304
1305 static void
1306 bnx2_set_mac_link(struct bnx2 *bp)
1307 {
1308 u32 val;
1309
1310 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1311 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1312 (bp->duplex == DUPLEX_HALF)) {
1313 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1314 }
1315
1316 /* Configure the EMAC mode register. */
1317 val = REG_RD(bp, BNX2_EMAC_MODE);
1318
1319 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1320 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1321 BNX2_EMAC_MODE_25G_MODE);
1322
1323 if (bp->link_up) {
1324 switch (bp->line_speed) {
1325 case SPEED_10:
1326 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1327 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1328 break;
1329 }
1330 /* fall through */
1331 case SPEED_100:
1332 val |= BNX2_EMAC_MODE_PORT_MII;
1333 break;
1334 case SPEED_2500:
1335 val |= BNX2_EMAC_MODE_25G_MODE;
1336 /* fall through */
1337 case SPEED_1000:
1338 val |= BNX2_EMAC_MODE_PORT_GMII;
1339 break;
1340 }
1341 }
1342 else {
1343 val |= BNX2_EMAC_MODE_PORT_GMII;
1344 }
1345
1346 /* Set the MAC to operate in the appropriate duplex mode. */
1347 if (bp->duplex == DUPLEX_HALF)
1348 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1349 REG_WR(bp, BNX2_EMAC_MODE, val);
1350
1351 /* Enable/disable rx PAUSE. */
1352 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1353
1354 if (bp->flow_ctrl & FLOW_CTRL_RX)
1355 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1356 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1357
1358 /* Enable/disable tx PAUSE. */
1359 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1360 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1361
1362 if (bp->flow_ctrl & FLOW_CTRL_TX)
1363 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1364 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1365
1366 /* Acknowledge the interrupt. */
1367 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1368
1369 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1370 bnx2_init_all_rx_contexts(bp);
1371 }
1372
1373 static void
1374 bnx2_enable_bmsr1(struct bnx2 *bp)
1375 {
1376 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1377 (CHIP_NUM(bp) == CHIP_NUM_5709))
1378 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1379 MII_BNX2_BLK_ADDR_GP_STATUS);
1380 }
1381
1382 static void
1383 bnx2_disable_bmsr1(struct bnx2 *bp)
1384 {
1385 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1386 (CHIP_NUM(bp) == CHIP_NUM_5709))
1387 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1388 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1389 }
1390
1391 static int
1392 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1393 {
1394 u32 up1;
1395 int ret = 1;
1396
1397 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1398 return 0;
1399
1400 if (bp->autoneg & AUTONEG_SPEED)
1401 bp->advertising |= ADVERTISED_2500baseX_Full;
1402
1403 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1404 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1405
1406 bnx2_read_phy(bp, bp->mii_up1, &up1);
1407 if (!(up1 & BCM5708S_UP1_2G5)) {
1408 up1 |= BCM5708S_UP1_2G5;
1409 bnx2_write_phy(bp, bp->mii_up1, up1);
1410 ret = 0;
1411 }
1412
1413 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1414 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1415 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1416
1417 return ret;
1418 }
1419
1420 static int
1421 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1422 {
1423 u32 up1;
1424 int ret = 0;
1425
1426 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1427 return 0;
1428
1429 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1430 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1431
1432 bnx2_read_phy(bp, bp->mii_up1, &up1);
1433 if (up1 & BCM5708S_UP1_2G5) {
1434 up1 &= ~BCM5708S_UP1_2G5;
1435 bnx2_write_phy(bp, bp->mii_up1, up1);
1436 ret = 1;
1437 }
1438
1439 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1440 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1441 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1442
1443 return ret;
1444 }
1445
1446 static void
1447 bnx2_enable_forced_2g5(struct bnx2 *bp)
1448 {
1449 u32 bmcr;
1450
1451 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1452 return;
1453
1454 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1455 u32 val;
1456
1457 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1458 MII_BNX2_BLK_ADDR_SERDES_DIG);
1459 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1460 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1461 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1462 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1463
1464 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1465 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1466 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1467
1468 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1469 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1470 bmcr |= BCM5708S_BMCR_FORCE_2500;
1471 } else {
1472 return;
1473 }
1474
1475 if (bp->autoneg & AUTONEG_SPEED) {
1476 bmcr &= ~BMCR_ANENABLE;
1477 if (bp->req_duplex == DUPLEX_FULL)
1478 bmcr |= BMCR_FULLDPLX;
1479 }
1480 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1481 }
1482
1483 static void
1484 bnx2_disable_forced_2g5(struct bnx2 *bp)
1485 {
1486 u32 bmcr;
1487
1488 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1489 return;
1490
1491 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1492 u32 val;
1493
1494 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1495 MII_BNX2_BLK_ADDR_SERDES_DIG);
1496 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1497 val &= ~MII_BNX2_SD_MISC1_FORCE;
1498 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1499
1500 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1501 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1502 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1503
1504 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1505 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1506 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1507 } else {
1508 return;
1509 }
1510
1511 if (bp->autoneg & AUTONEG_SPEED)
1512 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1513 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1514 }
1515
1516 static void
1517 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1518 {
1519 u32 val;
1520
1521 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1522 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1523 if (start)
1524 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1525 else
1526 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1527 }
1528
1529 static int
1530 bnx2_set_link(struct bnx2 *bp)
1531 {
1532 u32 bmsr;
1533 u8 link_up;
1534
1535 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1536 bp->link_up = 1;
1537 return 0;
1538 }
1539
1540 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1541 return 0;
1542
1543 link_up = bp->link_up;
1544
1545 bnx2_enable_bmsr1(bp);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1548 bnx2_disable_bmsr1(bp);
1549
1550 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1551 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1552 u32 val, an_dbg;
1553
1554 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1555 bnx2_5706s_force_link_dn(bp, 0);
1556 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1557 }
1558 val = REG_RD(bp, BNX2_EMAC_STATUS);
1559
1560 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1563
1564 if ((val & BNX2_EMAC_STATUS_LINK) &&
1565 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1566 bmsr |= BMSR_LSTATUS;
1567 else
1568 bmsr &= ~BMSR_LSTATUS;
1569 }
1570
1571 if (bmsr & BMSR_LSTATUS) {
1572 bp->link_up = 1;
1573
1574 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1575 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1576 bnx2_5706s_linkup(bp);
1577 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1578 bnx2_5708s_linkup(bp);
1579 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1580 bnx2_5709s_linkup(bp);
1581 }
1582 else {
1583 bnx2_copper_linkup(bp);
1584 }
1585 bnx2_resolve_flow_ctrl(bp);
1586 }
1587 else {
1588 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1589 (bp->autoneg & AUTONEG_SPEED))
1590 bnx2_disable_forced_2g5(bp);
1591
1592 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1593 u32 bmcr;
1594
1595 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1596 bmcr |= BMCR_ANENABLE;
1597 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1598
1599 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1600 }
1601 bp->link_up = 0;
1602 }
1603
1604 if (bp->link_up != link_up) {
1605 bnx2_report_link(bp);
1606 }
1607
1608 bnx2_set_mac_link(bp);
1609
1610 return 0;
1611 }
1612
1613 static int
1614 bnx2_reset_phy(struct bnx2 *bp)
1615 {
1616 int i;
1617 u32 reg;
1618
1619 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1620
1621 #define PHY_RESET_MAX_WAIT 100
1622 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1623 udelay(10);
1624
1625 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1626 if (!(reg & BMCR_RESET)) {
1627 udelay(20);
1628 break;
1629 }
1630 }
1631 if (i == PHY_RESET_MAX_WAIT) {
1632 return -EBUSY;
1633 }
1634 return 0;
1635 }
1636
1637 static u32
1638 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1639 {
1640 u32 adv = 0;
1641
1642 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1643 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1644
1645 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1646 adv = ADVERTISE_1000XPAUSE;
1647 }
1648 else {
1649 adv = ADVERTISE_PAUSE_CAP;
1650 }
1651 }
1652 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1653 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1654 adv = ADVERTISE_1000XPSE_ASYM;
1655 }
1656 else {
1657 adv = ADVERTISE_PAUSE_ASYM;
1658 }
1659 }
1660 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1661 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1662 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1663 }
1664 else {
1665 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1666 }
1667 }
1668 return adv;
1669 }
1670
1671 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1672
1673 static int
1674 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1675 __releases(&bp->phy_lock)
1676 __acquires(&bp->phy_lock)
1677 {
1678 u32 speed_arg = 0, pause_adv;
1679
1680 pause_adv = bnx2_phy_get_pause_adv(bp);
1681
1682 if (bp->autoneg & AUTONEG_SPEED) {
1683 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1684 if (bp->advertising & ADVERTISED_10baseT_Half)
1685 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1686 if (bp->advertising & ADVERTISED_10baseT_Full)
1687 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1688 if (bp->advertising & ADVERTISED_100baseT_Half)
1689 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1690 if (bp->advertising & ADVERTISED_100baseT_Full)
1691 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1692 if (bp->advertising & ADVERTISED_1000baseT_Full)
1693 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1694 if (bp->advertising & ADVERTISED_2500baseX_Full)
1695 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1696 } else {
1697 if (bp->req_line_speed == SPEED_2500)
1698 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1699 else if (bp->req_line_speed == SPEED_1000)
1700 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1701 else if (bp->req_line_speed == SPEED_100) {
1702 if (bp->req_duplex == DUPLEX_FULL)
1703 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1704 else
1705 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1706 } else if (bp->req_line_speed == SPEED_10) {
1707 if (bp->req_duplex == DUPLEX_FULL)
1708 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1709 else
1710 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1711 }
1712 }
1713
1714 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1715 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1716 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1717 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1718
1719 if (port == PORT_TP)
1720 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1721 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1722
1723 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1724
1725 spin_unlock_bh(&bp->phy_lock);
1726 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1727 spin_lock_bh(&bp->phy_lock);
1728
1729 return 0;
1730 }
1731
1732 static int
1733 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1734 __releases(&bp->phy_lock)
1735 __acquires(&bp->phy_lock)
1736 {
1737 u32 adv, bmcr;
1738 u32 new_adv = 0;
1739
1740 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1741 return (bnx2_setup_remote_phy(bp, port));
1742
1743 if (!(bp->autoneg & AUTONEG_SPEED)) {
1744 u32 new_bmcr;
1745 int force_link_down = 0;
1746
1747 if (bp->req_line_speed == SPEED_2500) {
1748 if (!bnx2_test_and_enable_2g5(bp))
1749 force_link_down = 1;
1750 } else if (bp->req_line_speed == SPEED_1000) {
1751 if (bnx2_test_and_disable_2g5(bp))
1752 force_link_down = 1;
1753 }
1754 bnx2_read_phy(bp, bp->mii_adv, &adv);
1755 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1756
1757 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1758 new_bmcr = bmcr & ~BMCR_ANENABLE;
1759 new_bmcr |= BMCR_SPEED1000;
1760
1761 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1762 if (bp->req_line_speed == SPEED_2500)
1763 bnx2_enable_forced_2g5(bp);
1764 else if (bp->req_line_speed == SPEED_1000) {
1765 bnx2_disable_forced_2g5(bp);
1766 new_bmcr &= ~0x2000;
1767 }
1768
1769 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1770 if (bp->req_line_speed == SPEED_2500)
1771 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1772 else
1773 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1774 }
1775
1776 if (bp->req_duplex == DUPLEX_FULL) {
1777 adv |= ADVERTISE_1000XFULL;
1778 new_bmcr |= BMCR_FULLDPLX;
1779 }
1780 else {
1781 adv |= ADVERTISE_1000XHALF;
1782 new_bmcr &= ~BMCR_FULLDPLX;
1783 }
1784 if ((new_bmcr != bmcr) || (force_link_down)) {
1785 /* Force a link down visible on the other side */
1786 if (bp->link_up) {
1787 bnx2_write_phy(bp, bp->mii_adv, adv &
1788 ~(ADVERTISE_1000XFULL |
1789 ADVERTISE_1000XHALF));
1790 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1791 BMCR_ANRESTART | BMCR_ANENABLE);
1792
1793 bp->link_up = 0;
1794 netif_carrier_off(bp->dev);
1795 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1796 bnx2_report_link(bp);
1797 }
1798 bnx2_write_phy(bp, bp->mii_adv, adv);
1799 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1800 } else {
1801 bnx2_resolve_flow_ctrl(bp);
1802 bnx2_set_mac_link(bp);
1803 }
1804 return 0;
1805 }
1806
1807 bnx2_test_and_enable_2g5(bp);
1808
1809 if (bp->advertising & ADVERTISED_1000baseT_Full)
1810 new_adv |= ADVERTISE_1000XFULL;
1811
1812 new_adv |= bnx2_phy_get_pause_adv(bp);
1813
1814 bnx2_read_phy(bp, bp->mii_adv, &adv);
1815 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1816
1817 bp->serdes_an_pending = 0;
1818 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1819 /* Force a link down visible on the other side */
1820 if (bp->link_up) {
1821 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1822 spin_unlock_bh(&bp->phy_lock);
1823 msleep(20);
1824 spin_lock_bh(&bp->phy_lock);
1825 }
1826
1827 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1828 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1829 BMCR_ANENABLE);
1830 /* Speed up link-up time when the link partner
1831 * does not autonegotiate which is very common
1832 * in blade servers. Some blade servers use
1833 * IPMI for kerboard input and it's important
1834 * to minimize link disruptions. Autoneg. involves
1835 * exchanging base pages plus 3 next pages and
1836 * normally completes in about 120 msec.
1837 */
1838 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1839 bp->serdes_an_pending = 1;
1840 mod_timer(&bp->timer, jiffies + bp->current_interval);
1841 } else {
1842 bnx2_resolve_flow_ctrl(bp);
1843 bnx2_set_mac_link(bp);
1844 }
1845
1846 return 0;
1847 }
1848
1849 #define ETHTOOL_ALL_FIBRE_SPEED \
1850 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1851 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1852 (ADVERTISED_1000baseT_Full)
1853
1854 #define ETHTOOL_ALL_COPPER_SPEED \
1855 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1856 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1857 ADVERTISED_1000baseT_Full)
1858
1859 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1860 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1861
1862 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1863
1864 static void
1865 bnx2_set_default_remote_link(struct bnx2 *bp)
1866 {
1867 u32 link;
1868
1869 if (bp->phy_port == PORT_TP)
1870 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1871 else
1872 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1873
1874 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1875 bp->req_line_speed = 0;
1876 bp->autoneg |= AUTONEG_SPEED;
1877 bp->advertising = ADVERTISED_Autoneg;
1878 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1879 bp->advertising |= ADVERTISED_10baseT_Half;
1880 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1881 bp->advertising |= ADVERTISED_10baseT_Full;
1882 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1883 bp->advertising |= ADVERTISED_100baseT_Half;
1884 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1885 bp->advertising |= ADVERTISED_100baseT_Full;
1886 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1887 bp->advertising |= ADVERTISED_1000baseT_Full;
1888 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1889 bp->advertising |= ADVERTISED_2500baseX_Full;
1890 } else {
1891 bp->autoneg = 0;
1892 bp->advertising = 0;
1893 bp->req_duplex = DUPLEX_FULL;
1894 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1895 bp->req_line_speed = SPEED_10;
1896 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1897 bp->req_duplex = DUPLEX_HALF;
1898 }
1899 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1900 bp->req_line_speed = SPEED_100;
1901 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1902 bp->req_duplex = DUPLEX_HALF;
1903 }
1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1905 bp->req_line_speed = SPEED_1000;
1906 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1907 bp->req_line_speed = SPEED_2500;
1908 }
1909 }
1910
1911 static void
1912 bnx2_set_default_link(struct bnx2 *bp)
1913 {
1914 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1915 bnx2_set_default_remote_link(bp);
1916 return;
1917 }
1918
1919 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1920 bp->req_line_speed = 0;
1921 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1922 u32 reg;
1923
1924 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1925
1926 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1927 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1928 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1929 bp->autoneg = 0;
1930 bp->req_line_speed = bp->line_speed = SPEED_1000;
1931 bp->req_duplex = DUPLEX_FULL;
1932 }
1933 } else
1934 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1935 }
1936
1937 static void
1938 bnx2_send_heart_beat(struct bnx2 *bp)
1939 {
1940 u32 msg;
1941 u32 addr;
1942
1943 spin_lock(&bp->indirect_lock);
1944 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1945 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1947 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1948 spin_unlock(&bp->indirect_lock);
1949 }
1950
1951 static void
1952 bnx2_remote_phy_event(struct bnx2 *bp)
1953 {
1954 u32 msg;
1955 u8 link_up = bp->link_up;
1956 u8 old_port;
1957
1958 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1959
1960 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1961 bnx2_send_heart_beat(bp);
1962
1963 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1964
1965 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1966 bp->link_up = 0;
1967 else {
1968 u32 speed;
1969
1970 bp->link_up = 1;
1971 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1972 bp->duplex = DUPLEX_FULL;
1973 switch (speed) {
1974 case BNX2_LINK_STATUS_10HALF:
1975 bp->duplex = DUPLEX_HALF;
1976 case BNX2_LINK_STATUS_10FULL:
1977 bp->line_speed = SPEED_10;
1978 break;
1979 case BNX2_LINK_STATUS_100HALF:
1980 bp->duplex = DUPLEX_HALF;
1981 case BNX2_LINK_STATUS_100BASE_T4:
1982 case BNX2_LINK_STATUS_100FULL:
1983 bp->line_speed = SPEED_100;
1984 break;
1985 case BNX2_LINK_STATUS_1000HALF:
1986 bp->duplex = DUPLEX_HALF;
1987 case BNX2_LINK_STATUS_1000FULL:
1988 bp->line_speed = SPEED_1000;
1989 break;
1990 case BNX2_LINK_STATUS_2500HALF:
1991 bp->duplex = DUPLEX_HALF;
1992 case BNX2_LINK_STATUS_2500FULL:
1993 bp->line_speed = SPEED_2500;
1994 break;
1995 default:
1996 bp->line_speed = 0;
1997 break;
1998 }
1999
2000 bp->flow_ctrl = 0;
2001 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2002 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2003 if (bp->duplex == DUPLEX_FULL)
2004 bp->flow_ctrl = bp->req_flow_ctrl;
2005 } else {
2006 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2007 bp->flow_ctrl |= FLOW_CTRL_TX;
2008 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2009 bp->flow_ctrl |= FLOW_CTRL_RX;
2010 }
2011
2012 old_port = bp->phy_port;
2013 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2014 bp->phy_port = PORT_FIBRE;
2015 else
2016 bp->phy_port = PORT_TP;
2017
2018 if (old_port != bp->phy_port)
2019 bnx2_set_default_link(bp);
2020
2021 }
2022 if (bp->link_up != link_up)
2023 bnx2_report_link(bp);
2024
2025 bnx2_set_mac_link(bp);
2026 }
2027
2028 static int
2029 bnx2_set_remote_link(struct bnx2 *bp)
2030 {
2031 u32 evt_code;
2032
2033 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2034 switch (evt_code) {
2035 case BNX2_FW_EVT_CODE_LINK_EVENT:
2036 bnx2_remote_phy_event(bp);
2037 break;
2038 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2039 default:
2040 bnx2_send_heart_beat(bp);
2041 break;
2042 }
2043 return 0;
2044 }
2045
2046 static int
2047 bnx2_setup_copper_phy(struct bnx2 *bp)
2048 __releases(&bp->phy_lock)
2049 __acquires(&bp->phy_lock)
2050 {
2051 u32 bmcr;
2052 u32 new_bmcr;
2053
2054 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2055
2056 if (bp->autoneg & AUTONEG_SPEED) {
2057 u32 adv_reg, adv1000_reg;
2058 u32 new_adv_reg = 0;
2059 u32 new_adv1000_reg = 0;
2060
2061 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2062 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2063 ADVERTISE_PAUSE_ASYM);
2064
2065 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2066 adv1000_reg &= PHY_ALL_1000_SPEED;
2067
2068 if (bp->advertising & ADVERTISED_10baseT_Half)
2069 new_adv_reg |= ADVERTISE_10HALF;
2070 if (bp->advertising & ADVERTISED_10baseT_Full)
2071 new_adv_reg |= ADVERTISE_10FULL;
2072 if (bp->advertising & ADVERTISED_100baseT_Half)
2073 new_adv_reg |= ADVERTISE_100HALF;
2074 if (bp->advertising & ADVERTISED_100baseT_Full)
2075 new_adv_reg |= ADVERTISE_100FULL;
2076 if (bp->advertising & ADVERTISED_1000baseT_Full)
2077 new_adv1000_reg |= ADVERTISE_1000FULL;
2078
2079 new_adv_reg |= ADVERTISE_CSMA;
2080
2081 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2082
2083 if ((adv1000_reg != new_adv1000_reg) ||
2084 (adv_reg != new_adv_reg) ||
2085 ((bmcr & BMCR_ANENABLE) == 0)) {
2086
2087 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2088 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2089 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2090 BMCR_ANENABLE);
2091 }
2092 else if (bp->link_up) {
2093 /* Flow ctrl may have changed from auto to forced */
2094 /* or vice-versa. */
2095
2096 bnx2_resolve_flow_ctrl(bp);
2097 bnx2_set_mac_link(bp);
2098 }
2099 return 0;
2100 }
2101
2102 new_bmcr = 0;
2103 if (bp->req_line_speed == SPEED_100) {
2104 new_bmcr |= BMCR_SPEED100;
2105 }
2106 if (bp->req_duplex == DUPLEX_FULL) {
2107 new_bmcr |= BMCR_FULLDPLX;
2108 }
2109 if (new_bmcr != bmcr) {
2110 u32 bmsr;
2111
2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2114
2115 if (bmsr & BMSR_LSTATUS) {
2116 /* Force link down */
2117 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2118 spin_unlock_bh(&bp->phy_lock);
2119 msleep(50);
2120 spin_lock_bh(&bp->phy_lock);
2121
2122 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2123 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2124 }
2125
2126 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2127
2128 /* Normally, the new speed is setup after the link has
2129 * gone down and up again. In some cases, link will not go
2130 * down so we need to set up the new speed here.
2131 */
2132 if (bmsr & BMSR_LSTATUS) {
2133 bp->line_speed = bp->req_line_speed;
2134 bp->duplex = bp->req_duplex;
2135 bnx2_resolve_flow_ctrl(bp);
2136 bnx2_set_mac_link(bp);
2137 }
2138 } else {
2139 bnx2_resolve_flow_ctrl(bp);
2140 bnx2_set_mac_link(bp);
2141 }
2142 return 0;
2143 }
2144
2145 static int
2146 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2147 __releases(&bp->phy_lock)
2148 __acquires(&bp->phy_lock)
2149 {
2150 if (bp->loopback == MAC_LOOPBACK)
2151 return 0;
2152
2153 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2154 return (bnx2_setup_serdes_phy(bp, port));
2155 }
2156 else {
2157 return (bnx2_setup_copper_phy(bp));
2158 }
2159 }
2160
2161 static int
2162 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2163 {
2164 u32 val;
2165
2166 bp->mii_bmcr = MII_BMCR + 0x10;
2167 bp->mii_bmsr = MII_BMSR + 0x10;
2168 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2169 bp->mii_adv = MII_ADVERTISE + 0x10;
2170 bp->mii_lpa = MII_LPA + 0x10;
2171 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2172
2173 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2174 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2175
2176 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2177 if (reset_phy)
2178 bnx2_reset_phy(bp);
2179
2180 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2181
2182 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2183 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2184 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2185 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2186
2187 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2188 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2189 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2190 val |= BCM5708S_UP1_2G5;
2191 else
2192 val &= ~BCM5708S_UP1_2G5;
2193 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2194
2195 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2196 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2197 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2198 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2199
2200 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2201
2202 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2203 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2204 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2205
2206 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2207
2208 return 0;
2209 }
2210
2211 static int
2212 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2213 {
2214 u32 val;
2215
2216 if (reset_phy)
2217 bnx2_reset_phy(bp);
2218
2219 bp->mii_up1 = BCM5708S_UP1;
2220
2221 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2222 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2223 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2224
2225 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2226 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2227 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2228
2229 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2230 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2231 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2232
2233 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2234 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2235 val |= BCM5708S_UP1_2G5;
2236 bnx2_write_phy(bp, BCM5708S_UP1, val);
2237 }
2238
2239 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2240 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2241 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2242 /* increase tx signal amplitude */
2243 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2244 BCM5708S_BLK_ADDR_TX_MISC);
2245 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2246 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2247 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2248 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2249 }
2250
2251 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2252 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2253
2254 if (val) {
2255 u32 is_backplane;
2256
2257 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2258 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2259 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2260 BCM5708S_BLK_ADDR_TX_MISC);
2261 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2262 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2263 BCM5708S_BLK_ADDR_DIG);
2264 }
2265 }
2266 return 0;
2267 }
2268
2269 static int
2270 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2271 {
2272 if (reset_phy)
2273 bnx2_reset_phy(bp);
2274
2275 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2276
2277 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2278 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2279
2280 if (bp->dev->mtu > 1500) {
2281 u32 val;
2282
2283 /* Set extended packet length bit */
2284 bnx2_write_phy(bp, 0x18, 0x7);
2285 bnx2_read_phy(bp, 0x18, &val);
2286 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2287
2288 bnx2_write_phy(bp, 0x1c, 0x6c00);
2289 bnx2_read_phy(bp, 0x1c, &val);
2290 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2291 }
2292 else {
2293 u32 val;
2294
2295 bnx2_write_phy(bp, 0x18, 0x7);
2296 bnx2_read_phy(bp, 0x18, &val);
2297 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2298
2299 bnx2_write_phy(bp, 0x1c, 0x6c00);
2300 bnx2_read_phy(bp, 0x1c, &val);
2301 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2302 }
2303
2304 return 0;
2305 }
2306
2307 static int
2308 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2309 {
2310 u32 val;
2311
2312 if (reset_phy)
2313 bnx2_reset_phy(bp);
2314
2315 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2316 bnx2_write_phy(bp, 0x18, 0x0c00);
2317 bnx2_write_phy(bp, 0x17, 0x000a);
2318 bnx2_write_phy(bp, 0x15, 0x310b);
2319 bnx2_write_phy(bp, 0x17, 0x201f);
2320 bnx2_write_phy(bp, 0x15, 0x9506);
2321 bnx2_write_phy(bp, 0x17, 0x401f);
2322 bnx2_write_phy(bp, 0x15, 0x14e2);
2323 bnx2_write_phy(bp, 0x18, 0x0400);
2324 }
2325
2326 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2327 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2328 MII_BNX2_DSP_EXPAND_REG | 0x8);
2329 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2330 val &= ~(1 << 8);
2331 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2332 }
2333
2334 if (bp->dev->mtu > 1500) {
2335 /* Set extended packet length bit */
2336 bnx2_write_phy(bp, 0x18, 0x7);
2337 bnx2_read_phy(bp, 0x18, &val);
2338 bnx2_write_phy(bp, 0x18, val | 0x4000);
2339
2340 bnx2_read_phy(bp, 0x10, &val);
2341 bnx2_write_phy(bp, 0x10, val | 0x1);
2342 }
2343 else {
2344 bnx2_write_phy(bp, 0x18, 0x7);
2345 bnx2_read_phy(bp, 0x18, &val);
2346 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2347
2348 bnx2_read_phy(bp, 0x10, &val);
2349 bnx2_write_phy(bp, 0x10, val & ~0x1);
2350 }
2351
2352 /* ethernet@wirespeed */
2353 bnx2_write_phy(bp, 0x18, 0x7007);
2354 bnx2_read_phy(bp, 0x18, &val);
2355 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2356 return 0;
2357 }
2358
2359
2360 static int
2361 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2362 __releases(&bp->phy_lock)
2363 __acquires(&bp->phy_lock)
2364 {
2365 u32 val;
2366 int rc = 0;
2367
2368 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2369 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2370
2371 bp->mii_bmcr = MII_BMCR;
2372 bp->mii_bmsr = MII_BMSR;
2373 bp->mii_bmsr1 = MII_BMSR;
2374 bp->mii_adv = MII_ADVERTISE;
2375 bp->mii_lpa = MII_LPA;
2376
2377 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2378
2379 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2380 goto setup_phy;
2381
2382 bnx2_read_phy(bp, MII_PHYSID1, &val);
2383 bp->phy_id = val << 16;
2384 bnx2_read_phy(bp, MII_PHYSID2, &val);
2385 bp->phy_id |= val & 0xffff;
2386
2387 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2388 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2389 rc = bnx2_init_5706s_phy(bp, reset_phy);
2390 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2391 rc = bnx2_init_5708s_phy(bp, reset_phy);
2392 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2393 rc = bnx2_init_5709s_phy(bp, reset_phy);
2394 }
2395 else {
2396 rc = bnx2_init_copper_phy(bp, reset_phy);
2397 }
2398
2399 setup_phy:
2400 if (!rc)
2401 rc = bnx2_setup_phy(bp, bp->phy_port);
2402
2403 return rc;
2404 }
2405
2406 static int
2407 bnx2_set_mac_loopback(struct bnx2 *bp)
2408 {
2409 u32 mac_mode;
2410
2411 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2412 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2413 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2414 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2415 bp->link_up = 1;
2416 return 0;
2417 }
2418
2419 static int bnx2_test_link(struct bnx2 *);
2420
2421 static int
2422 bnx2_set_phy_loopback(struct bnx2 *bp)
2423 {
2424 u32 mac_mode;
2425 int rc, i;
2426
2427 spin_lock_bh(&bp->phy_lock);
2428 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2429 BMCR_SPEED1000);
2430 spin_unlock_bh(&bp->phy_lock);
2431 if (rc)
2432 return rc;
2433
2434 for (i = 0; i < 10; i++) {
2435 if (bnx2_test_link(bp) == 0)
2436 break;
2437 msleep(100);
2438 }
2439
2440 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2441 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2442 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2443 BNX2_EMAC_MODE_25G_MODE);
2444
2445 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2446 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2447 bp->link_up = 1;
2448 return 0;
2449 }
2450
2451 static int
2452 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2453 {
2454 int i;
2455 u32 val;
2456
2457 bp->fw_wr_seq++;
2458 msg_data |= bp->fw_wr_seq;
2459
2460 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2461
2462 if (!ack)
2463 return 0;
2464
2465 /* wait for an acknowledgement. */
2466 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2467 msleep(10);
2468
2469 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2470
2471 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2472 break;
2473 }
2474 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2475 return 0;
2476
2477 /* If we timed out, inform the firmware that this is the case. */
2478 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2479 if (!silent)
2480 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2481
2482 msg_data &= ~BNX2_DRV_MSG_CODE;
2483 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2484
2485 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2486
2487 return -EBUSY;
2488 }
2489
2490 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2491 return -EIO;
2492
2493 return 0;
2494 }
2495
2496 static int
2497 bnx2_init_5709_context(struct bnx2 *bp)
2498 {
2499 int i, ret = 0;
2500 u32 val;
2501
2502 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2503 val |= (BCM_PAGE_BITS - 8) << 16;
2504 REG_WR(bp, BNX2_CTX_COMMAND, val);
2505 for (i = 0; i < 10; i++) {
2506 val = REG_RD(bp, BNX2_CTX_COMMAND);
2507 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2508 break;
2509 udelay(2);
2510 }
2511 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2512 return -EBUSY;
2513
2514 for (i = 0; i < bp->ctx_pages; i++) {
2515 int j;
2516
2517 if (bp->ctx_blk[i])
2518 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2519 else
2520 return -ENOMEM;
2521
2522 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2523 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2524 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2525 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2526 (u64) bp->ctx_blk_mapping[i] >> 32);
2527 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2528 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2529 for (j = 0; j < 10; j++) {
2530
2531 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2532 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2533 break;
2534 udelay(5);
2535 }
2536 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2537 ret = -EBUSY;
2538 break;
2539 }
2540 }
2541 return ret;
2542 }
2543
2544 static void
2545 bnx2_init_context(struct bnx2 *bp)
2546 {
2547 u32 vcid;
2548
2549 vcid = 96;
2550 while (vcid) {
2551 u32 vcid_addr, pcid_addr, offset;
2552 int i;
2553
2554 vcid--;
2555
2556 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2557 u32 new_vcid;
2558
2559 vcid_addr = GET_PCID_ADDR(vcid);
2560 if (vcid & 0x8) {
2561 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2562 }
2563 else {
2564 new_vcid = vcid;
2565 }
2566 pcid_addr = GET_PCID_ADDR(new_vcid);
2567 }
2568 else {
2569 vcid_addr = GET_CID_ADDR(vcid);
2570 pcid_addr = vcid_addr;
2571 }
2572
2573 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2574 vcid_addr += (i << PHY_CTX_SHIFT);
2575 pcid_addr += (i << PHY_CTX_SHIFT);
2576
2577 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2578 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2579
2580 /* Zero out the context. */
2581 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2582 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2583 }
2584 }
2585 }
2586
2587 static int
2588 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2589 {
2590 u16 *good_mbuf;
2591 u32 good_mbuf_cnt;
2592 u32 val;
2593
2594 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2595 if (good_mbuf == NULL) {
2596 pr_err("Failed to allocate memory in %s\n", __func__);
2597 return -ENOMEM;
2598 }
2599
2600 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2601 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2602
2603 good_mbuf_cnt = 0;
2604
2605 /* Allocate a bunch of mbufs and save the good ones in an array. */
2606 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2607 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2608 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2609 BNX2_RBUF_COMMAND_ALLOC_REQ);
2610
2611 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2612
2613 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2614
2615 /* The addresses with Bit 9 set are bad memory blocks. */
2616 if (!(val & (1 << 9))) {
2617 good_mbuf[good_mbuf_cnt] = (u16) val;
2618 good_mbuf_cnt++;
2619 }
2620
2621 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2622 }
2623
2624 /* Free the good ones back to the mbuf pool thus discarding
2625 * all the bad ones. */
2626 while (good_mbuf_cnt) {
2627 good_mbuf_cnt--;
2628
2629 val = good_mbuf[good_mbuf_cnt];
2630 val = (val << 9) | val | 1;
2631
2632 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2633 }
2634 kfree(good_mbuf);
2635 return 0;
2636 }
2637
2638 static void
2639 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2640 {
2641 u32 val;
2642
2643 val = (mac_addr[0] << 8) | mac_addr[1];
2644
2645 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2646
2647 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2648 (mac_addr[4] << 8) | mac_addr[5];
2649
2650 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2651 }
2652
2653 static inline int
2654 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2655 {
2656 dma_addr_t mapping;
2657 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2658 struct rx_bd *rxbd =
2659 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2660 struct page *page = alloc_page(GFP_ATOMIC);
2661
2662 if (!page)
2663 return -ENOMEM;
2664 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2665 PCI_DMA_FROMDEVICE);
2666 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2667 __free_page(page);
2668 return -EIO;
2669 }
2670
2671 rx_pg->page = page;
2672 dma_unmap_addr_set(rx_pg, mapping, mapping);
2673 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2674 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2675 return 0;
2676 }
2677
2678 static void
2679 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2680 {
2681 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2682 struct page *page = rx_pg->page;
2683
2684 if (!page)
2685 return;
2686
2687 pci_unmap_page(bp->pdev, dma_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2688 PCI_DMA_FROMDEVICE);
2689
2690 __free_page(page);
2691 rx_pg->page = NULL;
2692 }
2693
2694 static inline int
2695 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2696 {
2697 struct sk_buff *skb;
2698 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2699 dma_addr_t mapping;
2700 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2701 unsigned long align;
2702
2703 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2704 if (skb == NULL) {
2705 return -ENOMEM;
2706 }
2707
2708 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2709 skb_reserve(skb, BNX2_RX_ALIGN - align);
2710
2711 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2712 PCI_DMA_FROMDEVICE);
2713 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2714 dev_kfree_skb(skb);
2715 return -EIO;
2716 }
2717
2718 rx_buf->skb = skb;
2719 rx_buf->desc = (struct l2_fhdr *) skb->data;
2720 dma_unmap_addr_set(rx_buf, mapping, mapping);
2721
2722 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2723 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2724
2725 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2726
2727 return 0;
2728 }
2729
2730 static int
2731 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2732 {
2733 struct status_block *sblk = bnapi->status_blk.msi;
2734 u32 new_link_state, old_link_state;
2735 int is_set = 1;
2736
2737 new_link_state = sblk->status_attn_bits & event;
2738 old_link_state = sblk->status_attn_bits_ack & event;
2739 if (new_link_state != old_link_state) {
2740 if (new_link_state)
2741 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2742 else
2743 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2744 } else
2745 is_set = 0;
2746
2747 return is_set;
2748 }
2749
2750 static void
2751 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2752 {
2753 spin_lock(&bp->phy_lock);
2754
2755 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2756 bnx2_set_link(bp);
2757 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2758 bnx2_set_remote_link(bp);
2759
2760 spin_unlock(&bp->phy_lock);
2761
2762 }
2763
2764 static inline u16
2765 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2766 {
2767 u16 cons;
2768
2769 /* Tell compiler that status block fields can change. */
2770 barrier();
2771 cons = *bnapi->hw_tx_cons_ptr;
2772 barrier();
2773 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2774 cons++;
2775 return cons;
2776 }
2777
2778 static int
2779 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2780 {
2781 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2782 u16 hw_cons, sw_cons, sw_ring_cons;
2783 int tx_pkt = 0, index;
2784 struct netdev_queue *txq;
2785
2786 index = (bnapi - bp->bnx2_napi);
2787 txq = netdev_get_tx_queue(bp->dev, index);
2788
2789 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2790 sw_cons = txr->tx_cons;
2791
2792 while (sw_cons != hw_cons) {
2793 struct sw_tx_bd *tx_buf;
2794 struct sk_buff *skb;
2795 int i, last;
2796
2797 sw_ring_cons = TX_RING_IDX(sw_cons);
2798
2799 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2800 skb = tx_buf->skb;
2801
2802 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2803 prefetch(&skb->end);
2804
2805 /* partial BD completions possible with TSO packets */
2806 if (tx_buf->is_gso) {
2807 u16 last_idx, last_ring_idx;
2808
2809 last_idx = sw_cons + tx_buf->nr_frags + 1;
2810 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2811 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2812 last_idx++;
2813 }
2814 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2815 break;
2816 }
2817 }
2818
2819 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
2820 skb_headlen(skb), PCI_DMA_TODEVICE);
2821
2822 tx_buf->skb = NULL;
2823 last = tx_buf->nr_frags;
2824
2825 for (i = 0; i < last; i++) {
2826 sw_cons = NEXT_TX_BD(sw_cons);
2827
2828 pci_unmap_page(bp->pdev,
2829 dma_unmap_addr(
2830 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2831 mapping),
2832 skb_shinfo(skb)->frags[i].size,
2833 PCI_DMA_TODEVICE);
2834 }
2835
2836 sw_cons = NEXT_TX_BD(sw_cons);
2837
2838 dev_kfree_skb(skb);
2839 tx_pkt++;
2840 if (tx_pkt == budget)
2841 break;
2842
2843 if (hw_cons == sw_cons)
2844 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2845 }
2846
2847 txr->hw_tx_cons = hw_cons;
2848 txr->tx_cons = sw_cons;
2849
2850 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2851 * before checking for netif_tx_queue_stopped(). Without the
2852 * memory barrier, there is a small possibility that bnx2_start_xmit()
2853 * will miss it and cause the queue to be stopped forever.
2854 */
2855 smp_mb();
2856
2857 if (unlikely(netif_tx_queue_stopped(txq)) &&
2858 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2859 __netif_tx_lock(txq, smp_processor_id());
2860 if ((netif_tx_queue_stopped(txq)) &&
2861 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2862 netif_tx_wake_queue(txq);
2863 __netif_tx_unlock(txq);
2864 }
2865
2866 return tx_pkt;
2867 }
2868
2869 static void
2870 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2871 struct sk_buff *skb, int count)
2872 {
2873 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2874 struct rx_bd *cons_bd, *prod_bd;
2875 int i;
2876 u16 hw_prod, prod;
2877 u16 cons = rxr->rx_pg_cons;
2878
2879 cons_rx_pg = &rxr->rx_pg_ring[cons];
2880
2881 /* The caller was unable to allocate a new page to replace the
2882 * last one in the frags array, so we need to recycle that page
2883 * and then free the skb.
2884 */
2885 if (skb) {
2886 struct page *page;
2887 struct skb_shared_info *shinfo;
2888
2889 shinfo = skb_shinfo(skb);
2890 shinfo->nr_frags--;
2891 page = shinfo->frags[shinfo->nr_frags].page;
2892 shinfo->frags[shinfo->nr_frags].page = NULL;
2893
2894 cons_rx_pg->page = page;
2895 dev_kfree_skb(skb);
2896 }
2897
2898 hw_prod = rxr->rx_pg_prod;
2899
2900 for (i = 0; i < count; i++) {
2901 prod = RX_PG_RING_IDX(hw_prod);
2902
2903 prod_rx_pg = &rxr->rx_pg_ring[prod];
2904 cons_rx_pg = &rxr->rx_pg_ring[cons];
2905 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2906 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2907
2908 if (prod != cons) {
2909 prod_rx_pg->page = cons_rx_pg->page;
2910 cons_rx_pg->page = NULL;
2911 dma_unmap_addr_set(prod_rx_pg, mapping,
2912 dma_unmap_addr(cons_rx_pg, mapping));
2913
2914 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2915 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2916
2917 }
2918 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2919 hw_prod = NEXT_RX_BD(hw_prod);
2920 }
2921 rxr->rx_pg_prod = hw_prod;
2922 rxr->rx_pg_cons = cons;
2923 }
2924
2925 static inline void
2926 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2927 struct sk_buff *skb, u16 cons, u16 prod)
2928 {
2929 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2930 struct rx_bd *cons_bd, *prod_bd;
2931
2932 cons_rx_buf = &rxr->rx_buf_ring[cons];
2933 prod_rx_buf = &rxr->rx_buf_ring[prod];
2934
2935 pci_dma_sync_single_for_device(bp->pdev,
2936 dma_unmap_addr(cons_rx_buf, mapping),
2937 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2938
2939 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2940
2941 prod_rx_buf->skb = skb;
2942 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
2943
2944 if (cons == prod)
2945 return;
2946
2947 dma_unmap_addr_set(prod_rx_buf, mapping,
2948 dma_unmap_addr(cons_rx_buf, mapping));
2949
2950 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2951 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2952 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2953 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2954 }
2955
2956 static int
2957 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2958 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2959 u32 ring_idx)
2960 {
2961 int err;
2962 u16 prod = ring_idx & 0xffff;
2963
2964 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2965 if (unlikely(err)) {
2966 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2967 if (hdr_len) {
2968 unsigned int raw_len = len + 4;
2969 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2970
2971 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2972 }
2973 return err;
2974 }
2975
2976 skb_reserve(skb, BNX2_RX_OFFSET);
2977 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2978 PCI_DMA_FROMDEVICE);
2979
2980 if (hdr_len == 0) {
2981 skb_put(skb, len);
2982 return 0;
2983 } else {
2984 unsigned int i, frag_len, frag_size, pages;
2985 struct sw_pg *rx_pg;
2986 u16 pg_cons = rxr->rx_pg_cons;
2987 u16 pg_prod = rxr->rx_pg_prod;
2988
2989 frag_size = len + 4 - hdr_len;
2990 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2991 skb_put(skb, hdr_len);
2992
2993 for (i = 0; i < pages; i++) {
2994 dma_addr_t mapping_old;
2995
2996 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2997 if (unlikely(frag_len <= 4)) {
2998 unsigned int tail = 4 - frag_len;
2999
3000 rxr->rx_pg_cons = pg_cons;
3001 rxr->rx_pg_prod = pg_prod;
3002 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3003 pages - i);
3004 skb->len -= tail;
3005 if (i == 0) {
3006 skb->tail -= tail;
3007 } else {
3008 skb_frag_t *frag =
3009 &skb_shinfo(skb)->frags[i - 1];
3010 frag->size -= tail;
3011 skb->data_len -= tail;
3012 skb->truesize -= tail;
3013 }
3014 return 0;
3015 }
3016 rx_pg = &rxr->rx_pg_ring[pg_cons];
3017
3018 /* Don't unmap yet. If we're unable to allocate a new
3019 * page, we need to recycle the page and the DMA addr.
3020 */
3021 mapping_old = dma_unmap_addr(rx_pg, mapping);
3022 if (i == pages - 1)
3023 frag_len -= 4;
3024
3025 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3026 rx_pg->page = NULL;
3027
3028 err = bnx2_alloc_rx_page(bp, rxr,
3029 RX_PG_RING_IDX(pg_prod));
3030 if (unlikely(err)) {
3031 rxr->rx_pg_cons = pg_cons;
3032 rxr->rx_pg_prod = pg_prod;
3033 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3034 pages - i);
3035 return err;
3036 }
3037
3038 pci_unmap_page(bp->pdev, mapping_old,
3039 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3040
3041 frag_size -= frag_len;
3042 skb->data_len += frag_len;
3043 skb->truesize += frag_len;
3044 skb->len += frag_len;
3045
3046 pg_prod = NEXT_RX_BD(pg_prod);
3047 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3048 }
3049 rxr->rx_pg_prod = pg_prod;
3050 rxr->rx_pg_cons = pg_cons;
3051 }
3052 return 0;
3053 }
3054
3055 static inline u16
3056 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3057 {
3058 u16 cons;
3059
3060 /* Tell compiler that status block fields can change. */
3061 barrier();
3062 cons = *bnapi->hw_rx_cons_ptr;
3063 barrier();
3064 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3065 cons++;
3066 return cons;
3067 }
3068
3069 static int
3070 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3071 {
3072 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3073 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3074 struct l2_fhdr *rx_hdr;
3075 int rx_pkt = 0, pg_ring_used = 0;
3076 struct pci_dev *pdev = bp->pdev;
3077
3078 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3079 sw_cons = rxr->rx_cons;
3080 sw_prod = rxr->rx_prod;
3081
3082 /* Memory barrier necessary as speculative reads of the rx
3083 * buffer can be ahead of the index in the status block
3084 */
3085 rmb();
3086 while (sw_cons != hw_cons) {
3087 unsigned int len, hdr_len;
3088 u32 status;
3089 struct sw_bd *rx_buf, *next_rx_buf;
3090 struct sk_buff *skb;
3091 dma_addr_t dma_addr;
3092 u16 vtag = 0;
3093 int hw_vlan __maybe_unused = 0;
3094
3095 sw_ring_cons = RX_RING_IDX(sw_cons);
3096 sw_ring_prod = RX_RING_IDX(sw_prod);
3097
3098 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3099 skb = rx_buf->skb;
3100 prefetchw(skb);
3101
3102 if (!get_dma_ops(&pdev->dev)->sync_single_for_cpu) {
3103 next_rx_buf =
3104 &rxr->rx_buf_ring[
3105 RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3106 prefetch(next_rx_buf->desc);
3107 }
3108 rx_buf->skb = NULL;
3109
3110 dma_addr = dma_unmap_addr(rx_buf, mapping);
3111
3112 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3113 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3114 PCI_DMA_FROMDEVICE);
3115
3116 rx_hdr = rx_buf->desc;
3117 len = rx_hdr->l2_fhdr_pkt_len;
3118 status = rx_hdr->l2_fhdr_status;
3119
3120 hdr_len = 0;
3121 if (status & L2_FHDR_STATUS_SPLIT) {
3122 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3123 pg_ring_used = 1;
3124 } else if (len > bp->rx_jumbo_thresh) {
3125 hdr_len = bp->rx_jumbo_thresh;
3126 pg_ring_used = 1;
3127 }
3128
3129 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3130 L2_FHDR_ERRORS_PHY_DECODE |
3131 L2_FHDR_ERRORS_ALIGNMENT |
3132 L2_FHDR_ERRORS_TOO_SHORT |
3133 L2_FHDR_ERRORS_GIANT_FRAME))) {
3134
3135 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3136 sw_ring_prod);
3137 if (pg_ring_used) {
3138 int pages;
3139
3140 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3141
3142 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3143 }
3144 goto next_rx;
3145 }
3146
3147 len -= 4;
3148
3149 if (len <= bp->rx_copy_thresh) {
3150 struct sk_buff *new_skb;
3151
3152 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3153 if (new_skb == NULL) {
3154 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3155 sw_ring_prod);
3156 goto next_rx;
3157 }
3158
3159 /* aligned copy */
3160 skb_copy_from_linear_data_offset(skb,
3161 BNX2_RX_OFFSET - 6,
3162 new_skb->data, len + 6);
3163 skb_reserve(new_skb, 6);
3164 skb_put(new_skb, len);
3165
3166 bnx2_reuse_rx_skb(bp, rxr, skb,
3167 sw_ring_cons, sw_ring_prod);
3168
3169 skb = new_skb;
3170 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3171 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3172 goto next_rx;
3173
3174 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3175 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3176 vtag = rx_hdr->l2_fhdr_vlan_tag;
3177 #ifdef BCM_VLAN
3178 if (bp->vlgrp)
3179 hw_vlan = 1;
3180 else
3181 #endif
3182 {
3183 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3184 __skb_push(skb, 4);
3185
3186 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3187 ve->h_vlan_proto = htons(ETH_P_8021Q);
3188 ve->h_vlan_TCI = htons(vtag);
3189 len += 4;
3190 }
3191 }
3192
3193 skb->protocol = eth_type_trans(skb, bp->dev);
3194
3195 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3196 (ntohs(skb->protocol) != 0x8100)) {
3197
3198 dev_kfree_skb(skb);
3199 goto next_rx;
3200
3201 }
3202
3203 skb->ip_summed = CHECKSUM_NONE;
3204 if (bp->rx_csum &&
3205 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3206 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3207
3208 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3209 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3210 skb->ip_summed = CHECKSUM_UNNECESSARY;
3211 }
3212
3213 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3214
3215 #ifdef BCM_VLAN
3216 if (hw_vlan)
3217 vlan_gro_receive(&bnapi->napi, bp->vlgrp, vtag, skb);
3218 else
3219 #endif
3220 napi_gro_receive(&bnapi->napi, skb);
3221
3222 rx_pkt++;
3223
3224 next_rx:
3225 sw_cons = NEXT_RX_BD(sw_cons);
3226 sw_prod = NEXT_RX_BD(sw_prod);
3227
3228 if ((rx_pkt == budget))
3229 break;
3230
3231 /* Refresh hw_cons to see if there is new work */
3232 if (sw_cons == hw_cons) {
3233 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3234 rmb();
3235 }
3236 }
3237 rxr->rx_cons = sw_cons;
3238 rxr->rx_prod = sw_prod;
3239
3240 if (pg_ring_used)
3241 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3242
3243 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3244
3245 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3246
3247 mmiowb();
3248
3249 return rx_pkt;
3250
3251 }
3252
3253 /* MSI ISR - The only difference between this and the INTx ISR
3254 * is that the MSI interrupt is always serviced.
3255 */
3256 static irqreturn_t
3257 bnx2_msi(int irq, void *dev_instance)
3258 {
3259 struct bnx2_napi *bnapi = dev_instance;
3260 struct bnx2 *bp = bnapi->bp;
3261
3262 prefetch(bnapi->status_blk.msi);
3263 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3264 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3265 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3266
3267 /* Return here if interrupt is disabled. */
3268 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3269 return IRQ_HANDLED;
3270
3271 napi_schedule(&bnapi->napi);
3272
3273 return IRQ_HANDLED;
3274 }
3275
3276 static irqreturn_t
3277 bnx2_msi_1shot(int irq, void *dev_instance)
3278 {
3279 struct bnx2_napi *bnapi = dev_instance;
3280 struct bnx2 *bp = bnapi->bp;
3281
3282 prefetch(bnapi->status_blk.msi);
3283
3284 /* Return here if interrupt is disabled. */
3285 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3286 return IRQ_HANDLED;
3287
3288 napi_schedule(&bnapi->napi);
3289
3290 return IRQ_HANDLED;
3291 }
3292
3293 static irqreturn_t
3294 bnx2_interrupt(int irq, void *dev_instance)
3295 {
3296 struct bnx2_napi *bnapi = dev_instance;
3297 struct bnx2 *bp = bnapi->bp;
3298 struct status_block *sblk = bnapi->status_blk.msi;
3299
3300 /* When using INTx, it is possible for the interrupt to arrive
3301 * at the CPU before the status block posted prior to the
3302 * interrupt. Reading a register will flush the status block.
3303 * When using MSI, the MSI message will always complete after
3304 * the status block write.
3305 */
3306 if ((sblk->status_idx == bnapi->last_status_idx) &&
3307 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3308 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3309 return IRQ_NONE;
3310
3311 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3312 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3313 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3314
3315 /* Read back to deassert IRQ immediately to avoid too many
3316 * spurious interrupts.
3317 */
3318 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3319
3320 /* Return here if interrupt is shared and is disabled. */
3321 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3322 return IRQ_HANDLED;
3323
3324 if (napi_schedule_prep(&bnapi->napi)) {
3325 bnapi->last_status_idx = sblk->status_idx;
3326 __napi_schedule(&bnapi->napi);
3327 }
3328
3329 return IRQ_HANDLED;
3330 }
3331
3332 static inline int
3333 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3334 {
3335 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3336 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3337
3338 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3339 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3340 return 1;
3341 return 0;
3342 }
3343
3344 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3345 STATUS_ATTN_BITS_TIMER_ABORT)
3346
3347 static inline int
3348 bnx2_has_work(struct bnx2_napi *bnapi)
3349 {
3350 struct status_block *sblk = bnapi->status_blk.msi;
3351
3352 if (bnx2_has_fast_work(bnapi))
3353 return 1;
3354
3355 #ifdef BCM_CNIC
3356 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3357 return 1;
3358 #endif
3359
3360 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3361 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3362 return 1;
3363
3364 return 0;
3365 }
3366
3367 static void
3368 bnx2_chk_missed_msi(struct bnx2 *bp)
3369 {
3370 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3371 u32 msi_ctrl;
3372
3373 if (bnx2_has_work(bnapi)) {
3374 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3375 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3376 return;
3377
3378 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3379 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3380 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3381 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3382 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3383 }
3384 }
3385
3386 bp->idle_chk_status_idx = bnapi->last_status_idx;
3387 }
3388
3389 #ifdef BCM_CNIC
3390 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3391 {
3392 struct cnic_ops *c_ops;
3393
3394 if (!bnapi->cnic_present)
3395 return;
3396
3397 rcu_read_lock();
3398 c_ops = rcu_dereference(bp->cnic_ops);
3399 if (c_ops)
3400 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3401 bnapi->status_blk.msi);
3402 rcu_read_unlock();
3403 }
3404 #endif
3405
3406 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3407 {
3408 struct status_block *sblk = bnapi->status_blk.msi;
3409 u32 status_attn_bits = sblk->status_attn_bits;
3410 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3411
3412 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3413 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3414
3415 bnx2_phy_int(bp, bnapi);
3416
3417 /* This is needed to take care of transient status
3418 * during link changes.
3419 */
3420 REG_WR(bp, BNX2_HC_COMMAND,
3421 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3422 REG_RD(bp, BNX2_HC_COMMAND);
3423 }
3424 }
3425
3426 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3427 int work_done, int budget)
3428 {
3429 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3430 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3431
3432 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3433 bnx2_tx_int(bp, bnapi, 0);
3434
3435 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3436 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3437
3438 return work_done;
3439 }
3440
3441 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3442 {
3443 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3444 struct bnx2 *bp = bnapi->bp;
3445 int work_done = 0;
3446 struct status_block_msix *sblk = bnapi->status_blk.msix;
3447
3448 while (1) {
3449 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3450 if (unlikely(work_done >= budget))
3451 break;
3452
3453 bnapi->last_status_idx = sblk->status_idx;
3454 /* status idx must be read before checking for more work. */
3455 rmb();
3456 if (likely(!bnx2_has_fast_work(bnapi))) {
3457
3458 napi_complete(napi);
3459 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3460 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3461 bnapi->last_status_idx);
3462 break;
3463 }
3464 }
3465 return work_done;
3466 }
3467
3468 static int bnx2_poll(struct napi_struct *napi, int budget)
3469 {
3470 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3471 struct bnx2 *bp = bnapi->bp;
3472 int work_done = 0;
3473 struct status_block *sblk = bnapi->status_blk.msi;
3474
3475 while (1) {
3476 bnx2_poll_link(bp, bnapi);
3477
3478 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3479
3480 #ifdef BCM_CNIC
3481 bnx2_poll_cnic(bp, bnapi);
3482 #endif
3483
3484 /* bnapi->last_status_idx is used below to tell the hw how
3485 * much work has been processed, so we must read it before
3486 * checking for more work.
3487 */
3488 bnapi->last_status_idx = sblk->status_idx;
3489
3490 if (unlikely(work_done >= budget))
3491 break;
3492
3493 rmb();
3494 if (likely(!bnx2_has_work(bnapi))) {
3495 napi_complete(napi);
3496 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3497 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3498 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3499 bnapi->last_status_idx);
3500 break;
3501 }
3502 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3503 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3504 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3505 bnapi->last_status_idx);
3506
3507 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3508 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3509 bnapi->last_status_idx);
3510 break;
3511 }
3512 }
3513
3514 return work_done;
3515 }
3516
3517 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3518 * from set_multicast.
3519 */
3520 static void
3521 bnx2_set_rx_mode(struct net_device *dev)
3522 {
3523 struct bnx2 *bp = netdev_priv(dev);
3524 u32 rx_mode, sort_mode;
3525 struct netdev_hw_addr *ha;
3526 int i;
3527
3528 if (!netif_running(dev))
3529 return;
3530
3531 spin_lock_bh(&bp->phy_lock);
3532
3533 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3534 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3535 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3536 #ifdef BCM_VLAN
3537 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3538 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3539 #else
3540 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3541 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3542 #endif
3543 if (dev->flags & IFF_PROMISC) {
3544 /* Promiscuous mode. */
3545 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3546 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3547 BNX2_RPM_SORT_USER0_PROM_VLAN;
3548 }
3549 else if (dev->flags & IFF_ALLMULTI) {
3550 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3551 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3552 0xffffffff);
3553 }
3554 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3555 }
3556 else {
3557 /* Accept one or more multicast(s). */
3558 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3559 u32 regidx;
3560 u32 bit;
3561 u32 crc;
3562
3563 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3564
3565 netdev_for_each_mc_addr(ha, dev) {
3566 crc = ether_crc_le(ETH_ALEN, ha->addr);
3567 bit = crc & 0xff;
3568 regidx = (bit & 0xe0) >> 5;
3569 bit &= 0x1f;
3570 mc_filter[regidx] |= (1 << bit);
3571 }
3572
3573 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3574 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3575 mc_filter[i]);
3576 }
3577
3578 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3579 }
3580
3581 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3582 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3583 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3584 BNX2_RPM_SORT_USER0_PROM_VLAN;
3585 } else if (!(dev->flags & IFF_PROMISC)) {
3586 /* Add all entries into to the match filter list */
3587 i = 0;
3588 netdev_for_each_uc_addr(ha, dev) {
3589 bnx2_set_mac_addr(bp, ha->addr,
3590 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3591 sort_mode |= (1 <<
3592 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3593 i++;
3594 }
3595
3596 }
3597
3598 if (rx_mode != bp->rx_mode) {
3599 bp->rx_mode = rx_mode;
3600 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3601 }
3602
3603 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3604 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3605 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3606
3607 spin_unlock_bh(&bp->phy_lock);
3608 }
3609
3610 static int __devinit
3611 check_fw_section(const struct firmware *fw,
3612 const struct bnx2_fw_file_section *section,
3613 u32 alignment, bool non_empty)
3614 {
3615 u32 offset = be32_to_cpu(section->offset);
3616 u32 len = be32_to_cpu(section->len);
3617
3618 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3619 return -EINVAL;
3620 if ((non_empty && len == 0) || len > fw->size - offset ||
3621 len & (alignment - 1))
3622 return -EINVAL;
3623 return 0;
3624 }
3625
3626 static int __devinit
3627 check_mips_fw_entry(const struct firmware *fw,
3628 const struct bnx2_mips_fw_file_entry *entry)
3629 {
3630 if (check_fw_section(fw, &entry->text, 4, true) ||
3631 check_fw_section(fw, &entry->data, 4, false) ||
3632 check_fw_section(fw, &entry->rodata, 4, false))
3633 return -EINVAL;
3634 return 0;
3635 }
3636
3637 static int __devinit
3638 bnx2_request_firmware(struct bnx2 *bp)
3639 {
3640 const char *mips_fw_file, *rv2p_fw_file;
3641 const struct bnx2_mips_fw_file *mips_fw;
3642 const struct bnx2_rv2p_fw_file *rv2p_fw;
3643 int rc;
3644
3645 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3646 mips_fw_file = FW_MIPS_FILE_09;
3647 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3648 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3649 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3650 else
3651 rv2p_fw_file = FW_RV2P_FILE_09;
3652 } else {
3653 mips_fw_file = FW_MIPS_FILE_06;
3654 rv2p_fw_file = FW_RV2P_FILE_06;
3655 }
3656
3657 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3658 if (rc) {
3659 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3660 return rc;
3661 }
3662
3663 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3664 if (rc) {
3665 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3666 return rc;
3667 }
3668 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3669 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3670 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3671 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3672 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3673 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3674 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3675 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3676 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3677 return -EINVAL;
3678 }
3679 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3680 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3681 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3682 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3683 return -EINVAL;
3684 }
3685
3686 return 0;
3687 }
3688
3689 static u32
3690 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3691 {
3692 switch (idx) {
3693 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3694 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3695 rv2p_code |= RV2P_BD_PAGE_SIZE;
3696 break;
3697 }
3698 return rv2p_code;
3699 }
3700
3701 static int
3702 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3703 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3704 {
3705 u32 rv2p_code_len, file_offset;
3706 __be32 *rv2p_code;
3707 int i;
3708 u32 val, cmd, addr;
3709
3710 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3711 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3712
3713 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3714
3715 if (rv2p_proc == RV2P_PROC1) {
3716 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3717 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3718 } else {
3719 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3720 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3721 }
3722
3723 for (i = 0; i < rv2p_code_len; i += 8) {
3724 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3725 rv2p_code++;
3726 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3727 rv2p_code++;
3728
3729 val = (i / 8) | cmd;
3730 REG_WR(bp, addr, val);
3731 }
3732
3733 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3734 for (i = 0; i < 8; i++) {
3735 u32 loc, code;
3736
3737 loc = be32_to_cpu(fw_entry->fixup[i]);
3738 if (loc && ((loc * 4) < rv2p_code_len)) {
3739 code = be32_to_cpu(*(rv2p_code + loc - 1));
3740 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3741 code = be32_to_cpu(*(rv2p_code + loc));
3742 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3743 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3744
3745 val = (loc / 2) | cmd;
3746 REG_WR(bp, addr, val);
3747 }
3748 }
3749
3750 /* Reset the processor, un-stall is done later. */
3751 if (rv2p_proc == RV2P_PROC1) {
3752 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3753 }
3754 else {
3755 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3756 }
3757
3758 return 0;
3759 }
3760
3761 static int
3762 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3763 const struct bnx2_mips_fw_file_entry *fw_entry)
3764 {
3765 u32 addr, len, file_offset;
3766 __be32 *data;
3767 u32 offset;
3768 u32 val;
3769
3770 /* Halt the CPU. */
3771 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3772 val |= cpu_reg->mode_value_halt;
3773 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3774 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3775
3776 /* Load the Text area. */
3777 addr = be32_to_cpu(fw_entry->text.addr);
3778 len = be32_to_cpu(fw_entry->text.len);
3779 file_offset = be32_to_cpu(fw_entry->text.offset);
3780 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3781
3782 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3783 if (len) {
3784 int j;
3785
3786 for (j = 0; j < (len / 4); j++, offset += 4)
3787 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3788 }
3789
3790 /* Load the Data area. */
3791 addr = be32_to_cpu(fw_entry->data.addr);
3792 len = be32_to_cpu(fw_entry->data.len);
3793 file_offset = be32_to_cpu(fw_entry->data.offset);
3794 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3795
3796 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3797 if (len) {
3798 int j;
3799
3800 for (j = 0; j < (len / 4); j++, offset += 4)
3801 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3802 }
3803
3804 /* Load the Read-Only area. */
3805 addr = be32_to_cpu(fw_entry->rodata.addr);
3806 len = be32_to_cpu(fw_entry->rodata.len);
3807 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3808 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3809
3810 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3811 if (len) {
3812 int j;
3813
3814 for (j = 0; j < (len / 4); j++, offset += 4)
3815 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3816 }
3817
3818 /* Clear the pre-fetch instruction. */
3819 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3820
3821 val = be32_to_cpu(fw_entry->start_addr);
3822 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3823
3824 /* Start the CPU. */
3825 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3826 val &= ~cpu_reg->mode_value_halt;
3827 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3828 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3829
3830 return 0;
3831 }
3832
3833 static int
3834 bnx2_init_cpus(struct bnx2 *bp)
3835 {
3836 const struct bnx2_mips_fw_file *mips_fw =
3837 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3838 const struct bnx2_rv2p_fw_file *rv2p_fw =
3839 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3840 int rc;
3841
3842 /* Initialize the RV2P processor. */
3843 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3844 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3845
3846 /* Initialize the RX Processor. */
3847 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3848 if (rc)
3849 goto init_cpu_err;
3850
3851 /* Initialize the TX Processor. */
3852 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3853 if (rc)
3854 goto init_cpu_err;
3855
3856 /* Initialize the TX Patch-up Processor. */
3857 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3858 if (rc)
3859 goto init_cpu_err;
3860
3861 /* Initialize the Completion Processor. */
3862 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3863 if (rc)
3864 goto init_cpu_err;
3865
3866 /* Initialize the Command Processor. */
3867 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3868
3869 init_cpu_err:
3870 return rc;
3871 }
3872
3873 static int
3874 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3875 {
3876 u16 pmcsr;
3877
3878 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3879
3880 switch (state) {
3881 case PCI_D0: {
3882 u32 val;
3883
3884 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3885 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3886 PCI_PM_CTRL_PME_STATUS);
3887
3888 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3889 /* delay required during transition out of D3hot */
3890 msleep(20);
3891
3892 val = REG_RD(bp, BNX2_EMAC_MODE);
3893 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3894 val &= ~BNX2_EMAC_MODE_MPKT;
3895 REG_WR(bp, BNX2_EMAC_MODE, val);
3896
3897 val = REG_RD(bp, BNX2_RPM_CONFIG);
3898 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3899 REG_WR(bp, BNX2_RPM_CONFIG, val);
3900 break;
3901 }
3902 case PCI_D3hot: {
3903 int i;
3904 u32 val, wol_msg;
3905
3906 if (bp->wol) {
3907 u32 advertising;
3908 u8 autoneg;
3909
3910 autoneg = bp->autoneg;
3911 advertising = bp->advertising;
3912
3913 if (bp->phy_port == PORT_TP) {
3914 bp->autoneg = AUTONEG_SPEED;
3915 bp->advertising = ADVERTISED_10baseT_Half |
3916 ADVERTISED_10baseT_Full |
3917 ADVERTISED_100baseT_Half |
3918 ADVERTISED_100baseT_Full |
3919 ADVERTISED_Autoneg;
3920 }
3921
3922 spin_lock_bh(&bp->phy_lock);
3923 bnx2_setup_phy(bp, bp->phy_port);
3924 spin_unlock_bh(&bp->phy_lock);
3925
3926 bp->autoneg = autoneg;
3927 bp->advertising = advertising;
3928
3929 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3930
3931 val = REG_RD(bp, BNX2_EMAC_MODE);
3932
3933 /* Enable port mode. */
3934 val &= ~BNX2_EMAC_MODE_PORT;
3935 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3936 BNX2_EMAC_MODE_ACPI_RCVD |
3937 BNX2_EMAC_MODE_MPKT;
3938 if (bp->phy_port == PORT_TP)
3939 val |= BNX2_EMAC_MODE_PORT_MII;
3940 else {
3941 val |= BNX2_EMAC_MODE_PORT_GMII;
3942 if (bp->line_speed == SPEED_2500)
3943 val |= BNX2_EMAC_MODE_25G_MODE;
3944 }
3945
3946 REG_WR(bp, BNX2_EMAC_MODE, val);
3947
3948 /* receive all multicast */
3949 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3950 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3951 0xffffffff);
3952 }
3953 REG_WR(bp, BNX2_EMAC_RX_MODE,
3954 BNX2_EMAC_RX_MODE_SORT_MODE);
3955
3956 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3957 BNX2_RPM_SORT_USER0_MC_EN;
3958 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3959 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3960 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3961 BNX2_RPM_SORT_USER0_ENA);
3962
3963 /* Need to enable EMAC and RPM for WOL. */
3964 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3965 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3966 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3967 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3968
3969 val = REG_RD(bp, BNX2_RPM_CONFIG);
3970 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3971 REG_WR(bp, BNX2_RPM_CONFIG, val);
3972
3973 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3974 }
3975 else {
3976 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3977 }
3978
3979 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3980 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3981 1, 0);
3982
3983 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3984 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3985 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3986
3987 if (bp->wol)
3988 pmcsr |= 3;
3989 }
3990 else {
3991 pmcsr |= 3;
3992 }
3993 if (bp->wol) {
3994 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3995 }
3996 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3997 pmcsr);
3998
3999 /* No more memory access after this point until
4000 * device is brought back to D0.
4001 */
4002 udelay(50);
4003 break;
4004 }
4005 default:
4006 return -EINVAL;
4007 }
4008 return 0;
4009 }
4010
4011 static int
4012 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4013 {
4014 u32 val;
4015 int j;
4016
4017 /* Request access to the flash interface. */
4018 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4019 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4020 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4021 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4022 break;
4023
4024 udelay(5);
4025 }
4026
4027 if (j >= NVRAM_TIMEOUT_COUNT)
4028 return -EBUSY;
4029
4030 return 0;
4031 }
4032
4033 static int
4034 bnx2_release_nvram_lock(struct bnx2 *bp)
4035 {
4036 int j;
4037 u32 val;
4038
4039 /* Relinquish nvram interface. */
4040 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4041
4042 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4043 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4044 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4045 break;
4046
4047 udelay(5);
4048 }
4049
4050 if (j >= NVRAM_TIMEOUT_COUNT)
4051 return -EBUSY;
4052
4053 return 0;
4054 }
4055
4056
4057 static int
4058 bnx2_enable_nvram_write(struct bnx2 *bp)
4059 {
4060 u32 val;
4061
4062 val = REG_RD(bp, BNX2_MISC_CFG);
4063 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4064
4065 if (bp->flash_info->flags & BNX2_NV_WREN) {
4066 int j;
4067
4068 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4069 REG_WR(bp, BNX2_NVM_COMMAND,
4070 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4071
4072 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4073 udelay(5);
4074
4075 val = REG_RD(bp, BNX2_NVM_COMMAND);
4076 if (val & BNX2_NVM_COMMAND_DONE)
4077 break;
4078 }
4079
4080 if (j >= NVRAM_TIMEOUT_COUNT)
4081 return -EBUSY;
4082 }
4083 return 0;
4084 }
4085
4086 static void
4087 bnx2_disable_nvram_write(struct bnx2 *bp)
4088 {
4089 u32 val;
4090
4091 val = REG_RD(bp, BNX2_MISC_CFG);
4092 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4093 }
4094
4095
4096 static void
4097 bnx2_enable_nvram_access(struct bnx2 *bp)
4098 {
4099 u32 val;
4100
4101 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4102 /* Enable both bits, even on read. */
4103 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4104 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4105 }
4106
4107 static void
4108 bnx2_disable_nvram_access(struct bnx2 *bp)
4109 {
4110 u32 val;
4111
4112 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4113 /* Disable both bits, even after read. */
4114 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4115 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4116 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4117 }
4118
4119 static int
4120 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4121 {
4122 u32 cmd;
4123 int j;
4124
4125 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4126 /* Buffered flash, no erase needed */
4127 return 0;
4128
4129 /* Build an erase command */
4130 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4131 BNX2_NVM_COMMAND_DOIT;
4132
4133 /* Need to clear DONE bit separately. */
4134 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4135
4136 /* Address of the NVRAM to read from. */
4137 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4138
4139 /* Issue an erase command. */
4140 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4141
4142 /* Wait for completion. */
4143 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4144 u32 val;
4145
4146 udelay(5);
4147
4148 val = REG_RD(bp, BNX2_NVM_COMMAND);
4149 if (val & BNX2_NVM_COMMAND_DONE)
4150 break;
4151 }
4152
4153 if (j >= NVRAM_TIMEOUT_COUNT)
4154 return -EBUSY;
4155
4156 return 0;
4157 }
4158
4159 static int
4160 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4161 {
4162 u32 cmd;
4163 int j;
4164
4165 /* Build the command word. */
4166 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4167
4168 /* Calculate an offset of a buffered flash, not needed for 5709. */
4169 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4170 offset = ((offset / bp->flash_info->page_size) <<
4171 bp->flash_info->page_bits) +
4172 (offset % bp->flash_info->page_size);
4173 }
4174
4175 /* Need to clear DONE bit separately. */
4176 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4177
4178 /* Address of the NVRAM to read from. */
4179 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4180
4181 /* Issue a read command. */
4182 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4183
4184 /* Wait for completion. */
4185 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4186 u32 val;
4187
4188 udelay(5);
4189
4190 val = REG_RD(bp, BNX2_NVM_COMMAND);
4191 if (val & BNX2_NVM_COMMAND_DONE) {
4192 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4193 memcpy(ret_val, &v, 4);
4194 break;
4195 }
4196 }
4197 if (j >= NVRAM_TIMEOUT_COUNT)
4198 return -EBUSY;
4199
4200 return 0;
4201 }
4202
4203
4204 static int
4205 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4206 {
4207 u32 cmd;
4208 __be32 val32;
4209 int j;
4210
4211 /* Build the command word. */
4212 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4213
4214 /* Calculate an offset of a buffered flash, not needed for 5709. */
4215 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4216 offset = ((offset / bp->flash_info->page_size) <<
4217 bp->flash_info->page_bits) +
4218 (offset % bp->flash_info->page_size);
4219 }
4220
4221 /* Need to clear DONE bit separately. */
4222 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4223
4224 memcpy(&val32, val, 4);
4225
4226 /* Write the data. */
4227 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4228
4229 /* Address of the NVRAM to write to. */
4230 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4231
4232 /* Issue the write command. */
4233 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4234
4235 /* Wait for completion. */
4236 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4237 udelay(5);
4238
4239 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4240 break;
4241 }
4242 if (j >= NVRAM_TIMEOUT_COUNT)
4243 return -EBUSY;
4244
4245 return 0;
4246 }
4247
4248 static int
4249 bnx2_init_nvram(struct bnx2 *bp)
4250 {
4251 u32 val;
4252 int j, entry_count, rc = 0;
4253 const struct flash_spec *flash;
4254
4255 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4256 bp->flash_info = &flash_5709;
4257 goto get_flash_size;
4258 }
4259
4260 /* Determine the selected interface. */
4261 val = REG_RD(bp, BNX2_NVM_CFG1);
4262
4263 entry_count = ARRAY_SIZE(flash_table);
4264
4265 if (val & 0x40000000) {
4266
4267 /* Flash interface has been reconfigured */
4268 for (j = 0, flash = &flash_table[0]; j < entry_count;
4269 j++, flash++) {
4270 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4271 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4272 bp->flash_info = flash;
4273 break;
4274 }
4275 }
4276 }
4277 else {
4278 u32 mask;
4279 /* Not yet been reconfigured */
4280
4281 if (val & (1 << 23))
4282 mask = FLASH_BACKUP_STRAP_MASK;
4283 else
4284 mask = FLASH_STRAP_MASK;
4285
4286 for (j = 0, flash = &flash_table[0]; j < entry_count;
4287 j++, flash++) {
4288
4289 if ((val & mask) == (flash->strapping & mask)) {
4290 bp->flash_info = flash;
4291
4292 /* Request access to the flash interface. */
4293 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4294 return rc;
4295
4296 /* Enable access to flash interface */
4297 bnx2_enable_nvram_access(bp);
4298
4299 /* Reconfigure the flash interface */
4300 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4301 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4302 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4303 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4304
4305 /* Disable access to flash interface */
4306 bnx2_disable_nvram_access(bp);
4307 bnx2_release_nvram_lock(bp);
4308
4309 break;
4310 }
4311 }
4312 } /* if (val & 0x40000000) */
4313
4314 if (j == entry_count) {
4315 bp->flash_info = NULL;
4316 pr_alert("Unknown flash/EEPROM type\n");
4317 return -ENODEV;
4318 }
4319
4320 get_flash_size:
4321 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4322 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4323 if (val)
4324 bp->flash_size = val;
4325 else
4326 bp->flash_size = bp->flash_info->total_size;
4327
4328 return rc;
4329 }
4330
4331 static int
4332 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4333 int buf_size)
4334 {
4335 int rc = 0;
4336 u32 cmd_flags, offset32, len32, extra;
4337
4338 if (buf_size == 0)
4339 return 0;
4340
4341 /* Request access to the flash interface. */
4342 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4343 return rc;
4344
4345 /* Enable access to flash interface */
4346 bnx2_enable_nvram_access(bp);
4347
4348 len32 = buf_size;
4349 offset32 = offset;
4350 extra = 0;
4351
4352 cmd_flags = 0;
4353
4354 if (offset32 & 3) {
4355 u8 buf[4];
4356 u32 pre_len;
4357
4358 offset32 &= ~3;
4359 pre_len = 4 - (offset & 3);
4360
4361 if (pre_len >= len32) {
4362 pre_len = len32;
4363 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4364 BNX2_NVM_COMMAND_LAST;
4365 }
4366 else {
4367 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4368 }
4369
4370 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4371
4372 if (rc)
4373 return rc;
4374
4375 memcpy(ret_buf, buf + (offset & 3), pre_len);
4376
4377 offset32 += 4;
4378 ret_buf += pre_len;
4379 len32 -= pre_len;
4380 }
4381 if (len32 & 3) {
4382 extra = 4 - (len32 & 3);
4383 len32 = (len32 + 4) & ~3;
4384 }
4385
4386 if (len32 == 4) {
4387 u8 buf[4];
4388
4389 if (cmd_flags)
4390 cmd_flags = BNX2_NVM_COMMAND_LAST;
4391 else
4392 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4393 BNX2_NVM_COMMAND_LAST;
4394
4395 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4396
4397 memcpy(ret_buf, buf, 4 - extra);
4398 }
4399 else if (len32 > 0) {
4400 u8 buf[4];
4401
4402 /* Read the first word. */
4403 if (cmd_flags)
4404 cmd_flags = 0;
4405 else
4406 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4407
4408 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4409
4410 /* Advance to the next dword. */
4411 offset32 += 4;
4412 ret_buf += 4;
4413 len32 -= 4;
4414
4415 while (len32 > 4 && rc == 0) {
4416 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4417
4418 /* Advance to the next dword. */
4419 offset32 += 4;
4420 ret_buf += 4;
4421 len32 -= 4;
4422 }
4423
4424 if (rc)
4425 return rc;
4426
4427 cmd_flags = BNX2_NVM_COMMAND_LAST;
4428 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4429
4430 memcpy(ret_buf, buf, 4 - extra);
4431 }
4432
4433 /* Disable access to flash interface */
4434 bnx2_disable_nvram_access(bp);
4435
4436 bnx2_release_nvram_lock(bp);
4437
4438 return rc;
4439 }
4440
4441 static int
4442 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4443 int buf_size)
4444 {
4445 u32 written, offset32, len32;
4446 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4447 int rc = 0;
4448 int align_start, align_end;
4449
4450 buf = data_buf;
4451 offset32 = offset;
4452 len32 = buf_size;
4453 align_start = align_end = 0;
4454
4455 if ((align_start = (offset32 & 3))) {
4456 offset32 &= ~3;
4457 len32 += align_start;
4458 if (len32 < 4)
4459 len32 = 4;
4460 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4461 return rc;
4462 }
4463
4464 if (len32 & 3) {
4465 align_end = 4 - (len32 & 3);
4466 len32 += align_end;
4467 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4468 return rc;
4469 }
4470
4471 if (align_start || align_end) {
4472 align_buf = kmalloc(len32, GFP_KERNEL);
4473 if (align_buf == NULL)
4474 return -ENOMEM;
4475 if (align_start) {
4476 memcpy(align_buf, start, 4);
4477 }
4478 if (align_end) {
4479 memcpy(align_buf + len32 - 4, end, 4);
4480 }
4481 memcpy(align_buf + align_start, data_buf, buf_size);
4482 buf = align_buf;
4483 }
4484
4485 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4486 flash_buffer = kmalloc(264, GFP_KERNEL);
4487 if (flash_buffer == NULL) {
4488 rc = -ENOMEM;
4489 goto nvram_write_end;
4490 }
4491 }
4492
4493 written = 0;
4494 while ((written < len32) && (rc == 0)) {
4495 u32 page_start, page_end, data_start, data_end;
4496 u32 addr, cmd_flags;
4497 int i;
4498
4499 /* Find the page_start addr */
4500 page_start = offset32 + written;
4501 page_start -= (page_start % bp->flash_info->page_size);
4502 /* Find the page_end addr */
4503 page_end = page_start + bp->flash_info->page_size;
4504 /* Find the data_start addr */
4505 data_start = (written == 0) ? offset32 : page_start;
4506 /* Find the data_end addr */
4507 data_end = (page_end > offset32 + len32) ?
4508 (offset32 + len32) : page_end;
4509
4510 /* Request access to the flash interface. */
4511 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4512 goto nvram_write_end;
4513
4514 /* Enable access to flash interface */
4515 bnx2_enable_nvram_access(bp);
4516
4517 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4518 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4519 int j;
4520
4521 /* Read the whole page into the buffer
4522 * (non-buffer flash only) */
4523 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4524 if (j == (bp->flash_info->page_size - 4)) {
4525 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4526 }
4527 rc = bnx2_nvram_read_dword(bp,
4528 page_start + j,
4529 &flash_buffer[j],
4530 cmd_flags);
4531
4532 if (rc)
4533 goto nvram_write_end;
4534
4535 cmd_flags = 0;
4536 }
4537 }
4538
4539 /* Enable writes to flash interface (unlock write-protect) */
4540 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4541 goto nvram_write_end;
4542
4543 /* Loop to write back the buffer data from page_start to
4544 * data_start */
4545 i = 0;
4546 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4547 /* Erase the page */
4548 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4549 goto nvram_write_end;
4550
4551 /* Re-enable the write again for the actual write */
4552 bnx2_enable_nvram_write(bp);
4553
4554 for (addr = page_start; addr < data_start;
4555 addr += 4, i += 4) {
4556
4557 rc = bnx2_nvram_write_dword(bp, addr,
4558 &flash_buffer[i], cmd_flags);
4559
4560 if (rc != 0)
4561 goto nvram_write_end;
4562
4563 cmd_flags = 0;
4564 }
4565 }
4566
4567 /* Loop to write the new data from data_start to data_end */
4568 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4569 if ((addr == page_end - 4) ||
4570 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4571 (addr == data_end - 4))) {
4572
4573 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4574 }
4575 rc = bnx2_nvram_write_dword(bp, addr, buf,
4576 cmd_flags);
4577
4578 if (rc != 0)
4579 goto nvram_write_end;
4580
4581 cmd_flags = 0;
4582 buf += 4;
4583 }
4584
4585 /* Loop to write back the buffer data from data_end
4586 * to page_end */
4587 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4588 for (addr = data_end; addr < page_end;
4589 addr += 4, i += 4) {
4590
4591 if (addr == page_end-4) {
4592 cmd_flags = BNX2_NVM_COMMAND_LAST;
4593 }
4594 rc = bnx2_nvram_write_dword(bp, addr,
4595 &flash_buffer[i], cmd_flags);
4596
4597 if (rc != 0)
4598 goto nvram_write_end;
4599
4600 cmd_flags = 0;
4601 }
4602 }
4603
4604 /* Disable writes to flash interface (lock write-protect) */
4605 bnx2_disable_nvram_write(bp);
4606
4607 /* Disable access to flash interface */
4608 bnx2_disable_nvram_access(bp);
4609 bnx2_release_nvram_lock(bp);
4610
4611 /* Increment written */
4612 written += data_end - data_start;
4613 }
4614
4615 nvram_write_end:
4616 kfree(flash_buffer);
4617 kfree(align_buf);
4618 return rc;
4619 }
4620
4621 static void
4622 bnx2_init_fw_cap(struct bnx2 *bp)
4623 {
4624 u32 val, sig = 0;
4625
4626 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4627 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4628
4629 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4630 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4631
4632 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4633 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4634 return;
4635
4636 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4637 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4638 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4639 }
4640
4641 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4642 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4643 u32 link;
4644
4645 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4646
4647 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4648 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4649 bp->phy_port = PORT_FIBRE;
4650 else
4651 bp->phy_port = PORT_TP;
4652
4653 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4654 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4655 }
4656
4657 if (netif_running(bp->dev) && sig)
4658 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4659 }
4660
4661 static void
4662 bnx2_setup_msix_tbl(struct bnx2 *bp)
4663 {
4664 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4665
4666 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4667 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4668 }
4669
4670 static int
4671 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4672 {
4673 u32 val;
4674 int i, rc = 0;
4675 u8 old_port;
4676
4677 /* Wait for the current PCI transaction to complete before
4678 * issuing a reset. */
4679 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4680 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4681 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4682 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4683 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4684 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4685 udelay(5);
4686
4687 /* Wait for the firmware to tell us it is ok to issue a reset. */
4688 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4689
4690 /* Deposit a driver reset signature so the firmware knows that
4691 * this is a soft reset. */
4692 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4693 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4694
4695 /* Do a dummy read to force the chip to complete all current transaction
4696 * before we issue a reset. */
4697 val = REG_RD(bp, BNX2_MISC_ID);
4698
4699 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4700 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4701 REG_RD(bp, BNX2_MISC_COMMAND);
4702 udelay(5);
4703
4704 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4705 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4706
4707 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4708
4709 } else {
4710 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4711 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4712 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4713
4714 /* Chip reset. */
4715 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4716
4717 /* Reading back any register after chip reset will hang the
4718 * bus on 5706 A0 and A1. The msleep below provides plenty
4719 * of margin for write posting.
4720 */
4721 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4722 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4723 msleep(20);
4724
4725 /* Reset takes approximate 30 usec */
4726 for (i = 0; i < 10; i++) {
4727 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4728 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4729 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4730 break;
4731 udelay(10);
4732 }
4733
4734 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4735 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4736 pr_err("Chip reset did not complete\n");
4737 return -EBUSY;
4738 }
4739 }
4740
4741 /* Make sure byte swapping is properly configured. */
4742 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4743 if (val != 0x01020304) {
4744 pr_err("Chip not in correct endian mode\n");
4745 return -ENODEV;
4746 }
4747
4748 /* Wait for the firmware to finish its initialization. */
4749 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4750 if (rc)
4751 return rc;
4752
4753 spin_lock_bh(&bp->phy_lock);
4754 old_port = bp->phy_port;
4755 bnx2_init_fw_cap(bp);
4756 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4757 old_port != bp->phy_port)
4758 bnx2_set_default_remote_link(bp);
4759 spin_unlock_bh(&bp->phy_lock);
4760
4761 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4762 /* Adjust the voltage regular to two steps lower. The default
4763 * of this register is 0x0000000e. */
4764 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4765
4766 /* Remove bad rbuf memory from the free pool. */
4767 rc = bnx2_alloc_bad_rbuf(bp);
4768 }
4769
4770 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4771 bnx2_setup_msix_tbl(bp);
4772 /* Prevent MSIX table reads and write from timing out */
4773 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4774 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4775 }
4776
4777 return rc;
4778 }
4779
4780 static int
4781 bnx2_init_chip(struct bnx2 *bp)
4782 {
4783 u32 val, mtu;
4784 int rc, i;
4785
4786 /* Make sure the interrupt is not active. */
4787 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4788
4789 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4790 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4791 #ifdef __BIG_ENDIAN
4792 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4793 #endif
4794 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4795 DMA_READ_CHANS << 12 |
4796 DMA_WRITE_CHANS << 16;
4797
4798 val |= (0x2 << 20) | (1 << 11);
4799
4800 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4801 val |= (1 << 23);
4802
4803 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4804 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4805 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4806
4807 REG_WR(bp, BNX2_DMA_CONFIG, val);
4808
4809 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4810 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4811 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4812 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4813 }
4814
4815 if (bp->flags & BNX2_FLAG_PCIX) {
4816 u16 val16;
4817
4818 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4819 &val16);
4820 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4821 val16 & ~PCI_X_CMD_ERO);
4822 }
4823
4824 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4825 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4826 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4827 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4828
4829 /* Initialize context mapping and zero out the quick contexts. The
4830 * context block must have already been enabled. */
4831 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4832 rc = bnx2_init_5709_context(bp);
4833 if (rc)
4834 return rc;
4835 } else
4836 bnx2_init_context(bp);
4837
4838 if ((rc = bnx2_init_cpus(bp)) != 0)
4839 return rc;
4840
4841 bnx2_init_nvram(bp);
4842
4843 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4844
4845 val = REG_RD(bp, BNX2_MQ_CONFIG);
4846 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4847 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4848 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4849 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4850 if (CHIP_REV(bp) == CHIP_REV_Ax)
4851 val |= BNX2_MQ_CONFIG_HALT_DIS;
4852 }
4853
4854 REG_WR(bp, BNX2_MQ_CONFIG, val);
4855
4856 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4857 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4858 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4859
4860 val = (BCM_PAGE_BITS - 8) << 24;
4861 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4862
4863 /* Configure page size. */
4864 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4865 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4866 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4867 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4868
4869 val = bp->mac_addr[0] +
4870 (bp->mac_addr[1] << 8) +
4871 (bp->mac_addr[2] << 16) +
4872 bp->mac_addr[3] +
4873 (bp->mac_addr[4] << 8) +
4874 (bp->mac_addr[5] << 16);
4875 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4876
4877 /* Program the MTU. Also include 4 bytes for CRC32. */
4878 mtu = bp->dev->mtu;
4879 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4880 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4881 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4882 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4883
4884 if (mtu < 1500)
4885 mtu = 1500;
4886
4887 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4888 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4889 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4890
4891 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4892 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4893 bp->bnx2_napi[i].last_status_idx = 0;
4894
4895 bp->idle_chk_status_idx = 0xffff;
4896
4897 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4898
4899 /* Set up how to generate a link change interrupt. */
4900 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4901
4902 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4903 (u64) bp->status_blk_mapping & 0xffffffff);
4904 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4905
4906 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4907 (u64) bp->stats_blk_mapping & 0xffffffff);
4908 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4909 (u64) bp->stats_blk_mapping >> 32);
4910
4911 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4912 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4913
4914 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4915 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4916
4917 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4918 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4919
4920 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4921
4922 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4923
4924 REG_WR(bp, BNX2_HC_COM_TICKS,
4925 (bp->com_ticks_int << 16) | bp->com_ticks);
4926
4927 REG_WR(bp, BNX2_HC_CMD_TICKS,
4928 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4929
4930 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4931 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4932 else
4933 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4934 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4935
4936 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4937 val = BNX2_HC_CONFIG_COLLECT_STATS;
4938 else {
4939 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4940 BNX2_HC_CONFIG_COLLECT_STATS;
4941 }
4942
4943 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4944 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4945 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4946
4947 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4948 }
4949
4950 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4951 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4952
4953 REG_WR(bp, BNX2_HC_CONFIG, val);
4954
4955 for (i = 1; i < bp->irq_nvecs; i++) {
4956 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4957 BNX2_HC_SB_CONFIG_1;
4958
4959 REG_WR(bp, base,
4960 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4961 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4962 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4963
4964 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4965 (bp->tx_quick_cons_trip_int << 16) |
4966 bp->tx_quick_cons_trip);
4967
4968 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4969 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4970
4971 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4972 (bp->rx_quick_cons_trip_int << 16) |
4973 bp->rx_quick_cons_trip);
4974
4975 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4976 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4977 }
4978
4979 /* Clear internal stats counters. */
4980 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4981
4982 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4983
4984 /* Initialize the receive filter. */
4985 bnx2_set_rx_mode(bp->dev);
4986
4987 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4988 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4989 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4990 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4991 }
4992 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4993 1, 0);
4994
4995 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4996 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4997
4998 udelay(20);
4999
5000 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5001
5002 return rc;
5003 }
5004
5005 static void
5006 bnx2_clear_ring_states(struct bnx2 *bp)
5007 {
5008 struct bnx2_napi *bnapi;
5009 struct bnx2_tx_ring_info *txr;
5010 struct bnx2_rx_ring_info *rxr;
5011 int i;
5012
5013 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5014 bnapi = &bp->bnx2_napi[i];
5015 txr = &bnapi->tx_ring;
5016 rxr = &bnapi->rx_ring;
5017
5018 txr->tx_cons = 0;
5019 txr->hw_tx_cons = 0;
5020 rxr->rx_prod_bseq = 0;
5021 rxr->rx_prod = 0;
5022 rxr->rx_cons = 0;
5023 rxr->rx_pg_prod = 0;
5024 rxr->rx_pg_cons = 0;
5025 }
5026 }
5027
5028 static void
5029 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5030 {
5031 u32 val, offset0, offset1, offset2, offset3;
5032 u32 cid_addr = GET_CID_ADDR(cid);
5033
5034 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5035 offset0 = BNX2_L2CTX_TYPE_XI;
5036 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5037 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5038 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5039 } else {
5040 offset0 = BNX2_L2CTX_TYPE;
5041 offset1 = BNX2_L2CTX_CMD_TYPE;
5042 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5043 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5044 }
5045 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5046 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5047
5048 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5049 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5050
5051 val = (u64) txr->tx_desc_mapping >> 32;
5052 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5053
5054 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5055 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5056 }
5057
5058 static void
5059 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5060 {
5061 struct tx_bd *txbd;
5062 u32 cid = TX_CID;
5063 struct bnx2_napi *bnapi;
5064 struct bnx2_tx_ring_info *txr;
5065
5066 bnapi = &bp->bnx2_napi[ring_num];
5067 txr = &bnapi->tx_ring;
5068
5069 if (ring_num == 0)
5070 cid = TX_CID;
5071 else
5072 cid = TX_TSS_CID + ring_num - 1;
5073
5074 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5075
5076 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5077
5078 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5079 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5080
5081 txr->tx_prod = 0;
5082 txr->tx_prod_bseq = 0;
5083
5084 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5085 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5086
5087 bnx2_init_tx_context(bp, cid, txr);
5088 }
5089
5090 static void
5091 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5092 int num_rings)
5093 {
5094 int i;
5095 struct rx_bd *rxbd;
5096
5097 for (i = 0; i < num_rings; i++) {
5098 int j;
5099
5100 rxbd = &rx_ring[i][0];
5101 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5102 rxbd->rx_bd_len = buf_size;
5103 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5104 }
5105 if (i == (num_rings - 1))
5106 j = 0;
5107 else
5108 j = i + 1;
5109 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5110 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5111 }
5112 }
5113
5114 static void
5115 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5116 {
5117 int i;
5118 u16 prod, ring_prod;
5119 u32 cid, rx_cid_addr, val;
5120 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5121 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5122
5123 if (ring_num == 0)
5124 cid = RX_CID;
5125 else
5126 cid = RX_RSS_CID + ring_num - 1;
5127
5128 rx_cid_addr = GET_CID_ADDR(cid);
5129
5130 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5131 bp->rx_buf_use_size, bp->rx_max_ring);
5132
5133 bnx2_init_rx_context(bp, cid);
5134
5135 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5136 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5137 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5138 }
5139
5140 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5141 if (bp->rx_pg_ring_size) {
5142 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5143 rxr->rx_pg_desc_mapping,
5144 PAGE_SIZE, bp->rx_max_pg_ring);
5145 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5146 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5147 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5148 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5149
5150 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5151 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5152
5153 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5154 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5155
5156 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5157 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5158 }
5159
5160 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5161 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5162
5163 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5164 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5165
5166 ring_prod = prod = rxr->rx_pg_prod;
5167 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5168 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) {
5169 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5170 ring_num, i, bp->rx_pg_ring_size);
5171 break;
5172 }
5173 prod = NEXT_RX_BD(prod);
5174 ring_prod = RX_PG_RING_IDX(prod);
5175 }
5176 rxr->rx_pg_prod = prod;
5177
5178 ring_prod = prod = rxr->rx_prod;
5179 for (i = 0; i < bp->rx_ring_size; i++) {
5180 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) {
5181 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5182 ring_num, i, bp->rx_ring_size);
5183 break;
5184 }
5185 prod = NEXT_RX_BD(prod);
5186 ring_prod = RX_RING_IDX(prod);
5187 }
5188 rxr->rx_prod = prod;
5189
5190 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5191 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5192 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5193
5194 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5195 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5196
5197 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5198 }
5199
5200 static void
5201 bnx2_init_all_rings(struct bnx2 *bp)
5202 {
5203 int i;
5204 u32 val;
5205
5206 bnx2_clear_ring_states(bp);
5207
5208 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5209 for (i = 0; i < bp->num_tx_rings; i++)
5210 bnx2_init_tx_ring(bp, i);
5211
5212 if (bp->num_tx_rings > 1)
5213 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5214 (TX_TSS_CID << 7));
5215
5216 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5217 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5218
5219 for (i = 0; i < bp->num_rx_rings; i++)
5220 bnx2_init_rx_ring(bp, i);
5221
5222 if (bp->num_rx_rings > 1) {
5223 u32 tbl_32;
5224 u8 *tbl = (u8 *) &tbl_32;
5225
5226 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5227 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5228
5229 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5230 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5231 if ((i % 4) == 3)
5232 bnx2_reg_wr_ind(bp,
5233 BNX2_RXP_SCRATCH_RSS_TBL + i,
5234 cpu_to_be32(tbl_32));
5235 }
5236
5237 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5238 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5239
5240 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5241
5242 }
5243 }
5244
5245 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5246 {
5247 u32 max, num_rings = 1;
5248
5249 while (ring_size > MAX_RX_DESC_CNT) {
5250 ring_size -= MAX_RX_DESC_CNT;
5251 num_rings++;
5252 }
5253 /* round to next power of 2 */
5254 max = max_size;
5255 while ((max & num_rings) == 0)
5256 max >>= 1;
5257
5258 if (num_rings != max)
5259 max <<= 1;
5260
5261 return max;
5262 }
5263
5264 static void
5265 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5266 {
5267 u32 rx_size, rx_space, jumbo_size;
5268
5269 /* 8 for CRC and VLAN */
5270 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5271
5272 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5273 sizeof(struct skb_shared_info);
5274
5275 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5276 bp->rx_pg_ring_size = 0;
5277 bp->rx_max_pg_ring = 0;
5278 bp->rx_max_pg_ring_idx = 0;
5279 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5280 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5281
5282 jumbo_size = size * pages;
5283 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5284 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5285
5286 bp->rx_pg_ring_size = jumbo_size;
5287 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5288 MAX_RX_PG_RINGS);
5289 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5290 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5291 bp->rx_copy_thresh = 0;
5292 }
5293
5294 bp->rx_buf_use_size = rx_size;
5295 /* hw alignment */
5296 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5297 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5298 bp->rx_ring_size = size;
5299 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5300 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5301 }
5302
5303 static void
5304 bnx2_free_tx_skbs(struct bnx2 *bp)
5305 {
5306 int i;
5307
5308 for (i = 0; i < bp->num_tx_rings; i++) {
5309 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5310 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5311 int j;
5312
5313 if (txr->tx_buf_ring == NULL)
5314 continue;
5315
5316 for (j = 0; j < TX_DESC_CNT; ) {
5317 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5318 struct sk_buff *skb = tx_buf->skb;
5319 int k, last;
5320
5321 if (skb == NULL) {
5322 j++;
5323 continue;
5324 }
5325
5326 pci_unmap_single(bp->pdev,
5327 dma_unmap_addr(tx_buf, mapping),
5328 skb_headlen(skb),
5329 PCI_DMA_TODEVICE);
5330
5331 tx_buf->skb = NULL;
5332
5333 last = tx_buf->nr_frags;
5334 j++;
5335 for (k = 0; k < last; k++, j++) {
5336 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5337 pci_unmap_page(bp->pdev,
5338 dma_unmap_addr(tx_buf, mapping),
5339 skb_shinfo(skb)->frags[k].size,
5340 PCI_DMA_TODEVICE);
5341 }
5342 dev_kfree_skb(skb);
5343 }
5344 }
5345 }
5346
5347 static void
5348 bnx2_free_rx_skbs(struct bnx2 *bp)
5349 {
5350 int i;
5351
5352 for (i = 0; i < bp->num_rx_rings; i++) {
5353 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5354 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5355 int j;
5356
5357 if (rxr->rx_buf_ring == NULL)
5358 return;
5359
5360 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5361 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5362 struct sk_buff *skb = rx_buf->skb;
5363
5364 if (skb == NULL)
5365 continue;
5366
5367 pci_unmap_single(bp->pdev,
5368 dma_unmap_addr(rx_buf, mapping),
5369 bp->rx_buf_use_size,
5370 PCI_DMA_FROMDEVICE);
5371
5372 rx_buf->skb = NULL;
5373
5374 dev_kfree_skb(skb);
5375 }
5376 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5377 bnx2_free_rx_page(bp, rxr, j);
5378 }
5379 }
5380
5381 static void
5382 bnx2_free_skbs(struct bnx2 *bp)
5383 {
5384 bnx2_free_tx_skbs(bp);
5385 bnx2_free_rx_skbs(bp);
5386 }
5387
5388 static int
5389 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5390 {
5391 int rc;
5392
5393 rc = bnx2_reset_chip(bp, reset_code);
5394 bnx2_free_skbs(bp);
5395 if (rc)
5396 return rc;
5397
5398 if ((rc = bnx2_init_chip(bp)) != 0)
5399 return rc;
5400
5401 bnx2_init_all_rings(bp);
5402 return 0;
5403 }
5404
5405 static int
5406 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5407 {
5408 int rc;
5409
5410 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5411 return rc;
5412
5413 spin_lock_bh(&bp->phy_lock);
5414 bnx2_init_phy(bp, reset_phy);
5415 bnx2_set_link(bp);
5416 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5417 bnx2_remote_phy_event(bp);
5418 spin_unlock_bh(&bp->phy_lock);
5419 return 0;
5420 }
5421
5422 static int
5423 bnx2_shutdown_chip(struct bnx2 *bp)
5424 {
5425 u32 reset_code;
5426
5427 if (bp->flags & BNX2_FLAG_NO_WOL)
5428 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5429 else if (bp->wol)
5430 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5431 else
5432 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5433
5434 return bnx2_reset_chip(bp, reset_code);
5435 }
5436
5437 static int
5438 bnx2_test_registers(struct bnx2 *bp)
5439 {
5440 int ret;
5441 int i, is_5709;
5442 static const struct {
5443 u16 offset;
5444 u16 flags;
5445 #define BNX2_FL_NOT_5709 1
5446 u32 rw_mask;
5447 u32 ro_mask;
5448 } reg_tbl[] = {
5449 { 0x006c, 0, 0x00000000, 0x0000003f },
5450 { 0x0090, 0, 0xffffffff, 0x00000000 },
5451 { 0x0094, 0, 0x00000000, 0x00000000 },
5452
5453 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5454 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5455 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5456 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5457 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5458 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5459 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5460 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5461 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5462
5463 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5464 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5465 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5466 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5467 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5468 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5469
5470 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5471 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5472 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5473
5474 { 0x1000, 0, 0x00000000, 0x00000001 },
5475 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5476
5477 { 0x1408, 0, 0x01c00800, 0x00000000 },
5478 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5479 { 0x14a8, 0, 0x00000000, 0x000001ff },
5480 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5481 { 0x14b0, 0, 0x00000002, 0x00000001 },
5482 { 0x14b8, 0, 0x00000000, 0x00000000 },
5483 { 0x14c0, 0, 0x00000000, 0x00000009 },
5484 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5485 { 0x14cc, 0, 0x00000000, 0x00000001 },
5486 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5487
5488 { 0x1800, 0, 0x00000000, 0x00000001 },
5489 { 0x1804, 0, 0x00000000, 0x00000003 },
5490
5491 { 0x2800, 0, 0x00000000, 0x00000001 },
5492 { 0x2804, 0, 0x00000000, 0x00003f01 },
5493 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5494 { 0x2810, 0, 0xffff0000, 0x00000000 },
5495 { 0x2814, 0, 0xffff0000, 0x00000000 },
5496 { 0x2818, 0, 0xffff0000, 0x00000000 },
5497 { 0x281c, 0, 0xffff0000, 0x00000000 },
5498 { 0x2834, 0, 0xffffffff, 0x00000000 },
5499 { 0x2840, 0, 0x00000000, 0xffffffff },
5500 { 0x2844, 0, 0x00000000, 0xffffffff },
5501 { 0x2848, 0, 0xffffffff, 0x00000000 },
5502 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5503
5504 { 0x2c00, 0, 0x00000000, 0x00000011 },
5505 { 0x2c04, 0, 0x00000000, 0x00030007 },
5506
5507 { 0x3c00, 0, 0x00000000, 0x00000001 },
5508 { 0x3c04, 0, 0x00000000, 0x00070000 },
5509 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5510 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5511 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5512 { 0x3c14, 0, 0x00000000, 0xffffffff },
5513 { 0x3c18, 0, 0x00000000, 0xffffffff },
5514 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5515 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5516
5517 { 0x5004, 0, 0x00000000, 0x0000007f },
5518 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5519
5520 { 0x5c00, 0, 0x00000000, 0x00000001 },
5521 { 0x5c04, 0, 0x00000000, 0x0003000f },
5522 { 0x5c08, 0, 0x00000003, 0x00000000 },
5523 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5524 { 0x5c10, 0, 0x00000000, 0xffffffff },
5525 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5526 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5527 { 0x5c88, 0, 0x00000000, 0x00077373 },
5528 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5529
5530 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5531 { 0x680c, 0, 0xffffffff, 0x00000000 },
5532 { 0x6810, 0, 0xffffffff, 0x00000000 },
5533 { 0x6814, 0, 0xffffffff, 0x00000000 },
5534 { 0x6818, 0, 0xffffffff, 0x00000000 },
5535 { 0x681c, 0, 0xffffffff, 0x00000000 },
5536 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5537 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5538 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5539 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5540 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5541 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5542 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5543 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5544 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5545 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5546 { 0x684c, 0, 0xffffffff, 0x00000000 },
5547 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5548 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5549 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5550 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5551 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5552 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5553
5554 { 0xffff, 0, 0x00000000, 0x00000000 },
5555 };
5556
5557 ret = 0;
5558 is_5709 = 0;
5559 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5560 is_5709 = 1;
5561
5562 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5563 u32 offset, rw_mask, ro_mask, save_val, val;
5564 u16 flags = reg_tbl[i].flags;
5565
5566 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5567 continue;
5568
5569 offset = (u32) reg_tbl[i].offset;
5570 rw_mask = reg_tbl[i].rw_mask;
5571 ro_mask = reg_tbl[i].ro_mask;
5572
5573 save_val = readl(bp->regview + offset);
5574
5575 writel(0, bp->regview + offset);
5576
5577 val = readl(bp->regview + offset);
5578 if ((val & rw_mask) != 0) {
5579 goto reg_test_err;
5580 }
5581
5582 if ((val & ro_mask) != (save_val & ro_mask)) {
5583 goto reg_test_err;
5584 }
5585
5586 writel(0xffffffff, bp->regview + offset);
5587
5588 val = readl(bp->regview + offset);
5589 if ((val & rw_mask) != rw_mask) {
5590 goto reg_test_err;
5591 }
5592
5593 if ((val & ro_mask) != (save_val & ro_mask)) {
5594 goto reg_test_err;
5595 }
5596
5597 writel(save_val, bp->regview + offset);
5598 continue;
5599
5600 reg_test_err:
5601 writel(save_val, bp->regview + offset);
5602 ret = -ENODEV;
5603 break;
5604 }
5605 return ret;
5606 }
5607
5608 static int
5609 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5610 {
5611 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5612 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5613 int i;
5614
5615 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5616 u32 offset;
5617
5618 for (offset = 0; offset < size; offset += 4) {
5619
5620 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5621
5622 if (bnx2_reg_rd_ind(bp, start + offset) !=
5623 test_pattern[i]) {
5624 return -ENODEV;
5625 }
5626 }
5627 }
5628 return 0;
5629 }
5630
5631 static int
5632 bnx2_test_memory(struct bnx2 *bp)
5633 {
5634 int ret = 0;
5635 int i;
5636 static struct mem_entry {
5637 u32 offset;
5638 u32 len;
5639 } mem_tbl_5706[] = {
5640 { 0x60000, 0x4000 },
5641 { 0xa0000, 0x3000 },
5642 { 0xe0000, 0x4000 },
5643 { 0x120000, 0x4000 },
5644 { 0x1a0000, 0x4000 },
5645 { 0x160000, 0x4000 },
5646 { 0xffffffff, 0 },
5647 },
5648 mem_tbl_5709[] = {
5649 { 0x60000, 0x4000 },
5650 { 0xa0000, 0x3000 },
5651 { 0xe0000, 0x4000 },
5652 { 0x120000, 0x4000 },
5653 { 0x1a0000, 0x4000 },
5654 { 0xffffffff, 0 },
5655 };
5656 struct mem_entry *mem_tbl;
5657
5658 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5659 mem_tbl = mem_tbl_5709;
5660 else
5661 mem_tbl = mem_tbl_5706;
5662
5663 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5664 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5665 mem_tbl[i].len)) != 0) {
5666 return ret;
5667 }
5668 }
5669
5670 return ret;
5671 }
5672
5673 #define BNX2_MAC_LOOPBACK 0
5674 #define BNX2_PHY_LOOPBACK 1
5675
5676 static int
5677 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5678 {
5679 unsigned int pkt_size, num_pkts, i;
5680 struct sk_buff *skb, *rx_skb;
5681 unsigned char *packet;
5682 u16 rx_start_idx, rx_idx;
5683 dma_addr_t map;
5684 struct tx_bd *txbd;
5685 struct sw_bd *rx_buf;
5686 struct l2_fhdr *rx_hdr;
5687 int ret = -ENODEV;
5688 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5689 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5690 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5691
5692 tx_napi = bnapi;
5693
5694 txr = &tx_napi->tx_ring;
5695 rxr = &bnapi->rx_ring;
5696 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5697 bp->loopback = MAC_LOOPBACK;
5698 bnx2_set_mac_loopback(bp);
5699 }
5700 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5701 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5702 return 0;
5703
5704 bp->loopback = PHY_LOOPBACK;
5705 bnx2_set_phy_loopback(bp);
5706 }
5707 else
5708 return -EINVAL;
5709
5710 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5711 skb = netdev_alloc_skb(bp->dev, pkt_size);
5712 if (!skb)
5713 return -ENOMEM;
5714 packet = skb_put(skb, pkt_size);
5715 memcpy(packet, bp->dev->dev_addr, 6);
5716 memset(packet + 6, 0x0, 8);
5717 for (i = 14; i < pkt_size; i++)
5718 packet[i] = (unsigned char) (i & 0xff);
5719
5720 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5721 PCI_DMA_TODEVICE);
5722 if (pci_dma_mapping_error(bp->pdev, map)) {
5723 dev_kfree_skb(skb);
5724 return -EIO;
5725 }
5726
5727 REG_WR(bp, BNX2_HC_COMMAND,
5728 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5729
5730 REG_RD(bp, BNX2_HC_COMMAND);
5731
5732 udelay(5);
5733 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5734
5735 num_pkts = 0;
5736
5737 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5738
5739 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5740 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5741 txbd->tx_bd_mss_nbytes = pkt_size;
5742 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5743
5744 num_pkts++;
5745 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5746 txr->tx_prod_bseq += pkt_size;
5747
5748 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5749 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5750
5751 udelay(100);
5752
5753 REG_WR(bp, BNX2_HC_COMMAND,
5754 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5755
5756 REG_RD(bp, BNX2_HC_COMMAND);
5757
5758 udelay(5);
5759
5760 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5761 dev_kfree_skb(skb);
5762
5763 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5764 goto loopback_test_done;
5765
5766 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5767 if (rx_idx != rx_start_idx + num_pkts) {
5768 goto loopback_test_done;
5769 }
5770
5771 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5772 rx_skb = rx_buf->skb;
5773
5774 rx_hdr = rx_buf->desc;
5775 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5776
5777 pci_dma_sync_single_for_cpu(bp->pdev,
5778 dma_unmap_addr(rx_buf, mapping),
5779 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5780
5781 if (rx_hdr->l2_fhdr_status &
5782 (L2_FHDR_ERRORS_BAD_CRC |
5783 L2_FHDR_ERRORS_PHY_DECODE |
5784 L2_FHDR_ERRORS_ALIGNMENT |
5785 L2_FHDR_ERRORS_TOO_SHORT |
5786 L2_FHDR_ERRORS_GIANT_FRAME)) {
5787
5788 goto loopback_test_done;
5789 }
5790
5791 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5792 goto loopback_test_done;
5793 }
5794
5795 for (i = 14; i < pkt_size; i++) {
5796 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5797 goto loopback_test_done;
5798 }
5799 }
5800
5801 ret = 0;
5802
5803 loopback_test_done:
5804 bp->loopback = 0;
5805 return ret;
5806 }
5807
5808 #define BNX2_MAC_LOOPBACK_FAILED 1
5809 #define BNX2_PHY_LOOPBACK_FAILED 2
5810 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5811 BNX2_PHY_LOOPBACK_FAILED)
5812
5813 static int
5814 bnx2_test_loopback(struct bnx2 *bp)
5815 {
5816 int rc = 0;
5817
5818 if (!netif_running(bp->dev))
5819 return BNX2_LOOPBACK_FAILED;
5820
5821 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5822 spin_lock_bh(&bp->phy_lock);
5823 bnx2_init_phy(bp, 1);
5824 spin_unlock_bh(&bp->phy_lock);
5825 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5826 rc |= BNX2_MAC_LOOPBACK_FAILED;
5827 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5828 rc |= BNX2_PHY_LOOPBACK_FAILED;
5829 return rc;
5830 }
5831
5832 #define NVRAM_SIZE 0x200
5833 #define CRC32_RESIDUAL 0xdebb20e3
5834
5835 static int
5836 bnx2_test_nvram(struct bnx2 *bp)
5837 {
5838 __be32 buf[NVRAM_SIZE / 4];
5839 u8 *data = (u8 *) buf;
5840 int rc = 0;
5841 u32 magic, csum;
5842
5843 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5844 goto test_nvram_done;
5845
5846 magic = be32_to_cpu(buf[0]);
5847 if (magic != 0x669955aa) {
5848 rc = -ENODEV;
5849 goto test_nvram_done;
5850 }
5851
5852 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5853 goto test_nvram_done;
5854
5855 csum = ether_crc_le(0x100, data);
5856 if (csum != CRC32_RESIDUAL) {
5857 rc = -ENODEV;
5858 goto test_nvram_done;
5859 }
5860
5861 csum = ether_crc_le(0x100, data + 0x100);
5862 if (csum != CRC32_RESIDUAL) {
5863 rc = -ENODEV;
5864 }
5865
5866 test_nvram_done:
5867 return rc;
5868 }
5869
5870 static int
5871 bnx2_test_link(struct bnx2 *bp)
5872 {
5873 u32 bmsr;
5874
5875 if (!netif_running(bp->dev))
5876 return -ENODEV;
5877
5878 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5879 if (bp->link_up)
5880 return 0;
5881 return -ENODEV;
5882 }
5883 spin_lock_bh(&bp->phy_lock);
5884 bnx2_enable_bmsr1(bp);
5885 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5886 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5887 bnx2_disable_bmsr1(bp);
5888 spin_unlock_bh(&bp->phy_lock);
5889
5890 if (bmsr & BMSR_LSTATUS) {
5891 return 0;
5892 }
5893 return -ENODEV;
5894 }
5895
5896 static int
5897 bnx2_test_intr(struct bnx2 *bp)
5898 {
5899 int i;
5900 u16 status_idx;
5901
5902 if (!netif_running(bp->dev))
5903 return -ENODEV;
5904
5905 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5906
5907 /* This register is not touched during run-time. */
5908 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5909 REG_RD(bp, BNX2_HC_COMMAND);
5910
5911 for (i = 0; i < 10; i++) {
5912 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5913 status_idx) {
5914
5915 break;
5916 }
5917
5918 msleep_interruptible(10);
5919 }
5920 if (i < 10)
5921 return 0;
5922
5923 return -ENODEV;
5924 }
5925
5926 /* Determining link for parallel detection. */
5927 static int
5928 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5929 {
5930 u32 mode_ctl, an_dbg, exp;
5931
5932 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5933 return 0;
5934
5935 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5936 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5937
5938 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5939 return 0;
5940
5941 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5942 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5943 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5944
5945 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5946 return 0;
5947
5948 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5949 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5950 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5951
5952 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5953 return 0;
5954
5955 return 1;
5956 }
5957
5958 static void
5959 bnx2_5706_serdes_timer(struct bnx2 *bp)
5960 {
5961 int check_link = 1;
5962
5963 spin_lock(&bp->phy_lock);
5964 if (bp->serdes_an_pending) {
5965 bp->serdes_an_pending--;
5966 check_link = 0;
5967 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5968 u32 bmcr;
5969
5970 bp->current_interval = BNX2_TIMER_INTERVAL;
5971
5972 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5973
5974 if (bmcr & BMCR_ANENABLE) {
5975 if (bnx2_5706_serdes_has_link(bp)) {
5976 bmcr &= ~BMCR_ANENABLE;
5977 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5978 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5979 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5980 }
5981 }
5982 }
5983 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5984 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5985 u32 phy2;
5986
5987 bnx2_write_phy(bp, 0x17, 0x0f01);
5988 bnx2_read_phy(bp, 0x15, &phy2);
5989 if (phy2 & 0x20) {
5990 u32 bmcr;
5991
5992 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5993 bmcr |= BMCR_ANENABLE;
5994 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5995
5996 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5997 }
5998 } else
5999 bp->current_interval = BNX2_TIMER_INTERVAL;
6000
6001 if (check_link) {
6002 u32 val;
6003
6004 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6005 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6006 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6007
6008 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6009 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6010 bnx2_5706s_force_link_dn(bp, 1);
6011 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6012 } else
6013 bnx2_set_link(bp);
6014 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6015 bnx2_set_link(bp);
6016 }
6017 spin_unlock(&bp->phy_lock);
6018 }
6019
6020 static void
6021 bnx2_5708_serdes_timer(struct bnx2 *bp)
6022 {
6023 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6024 return;
6025
6026 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6027 bp->serdes_an_pending = 0;
6028 return;
6029 }
6030
6031 spin_lock(&bp->phy_lock);
6032 if (bp->serdes_an_pending)
6033 bp->serdes_an_pending--;
6034 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6035 u32 bmcr;
6036
6037 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6038 if (bmcr & BMCR_ANENABLE) {
6039 bnx2_enable_forced_2g5(bp);
6040 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6041 } else {
6042 bnx2_disable_forced_2g5(bp);
6043 bp->serdes_an_pending = 2;
6044 bp->current_interval = BNX2_TIMER_INTERVAL;
6045 }
6046
6047 } else
6048 bp->current_interval = BNX2_TIMER_INTERVAL;
6049
6050 spin_unlock(&bp->phy_lock);
6051 }
6052
6053 static void
6054 bnx2_timer(unsigned long data)
6055 {
6056 struct bnx2 *bp = (struct bnx2 *) data;
6057
6058 if (!netif_running(bp->dev))
6059 return;
6060
6061 if (atomic_read(&bp->intr_sem) != 0)
6062 goto bnx2_restart_timer;
6063
6064 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6065 BNX2_FLAG_USING_MSI)
6066 bnx2_chk_missed_msi(bp);
6067
6068 bnx2_send_heart_beat(bp);
6069
6070 bp->stats_blk->stat_FwRxDrop =
6071 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6072
6073 /* workaround occasional corrupted counters */
6074 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6075 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6076 BNX2_HC_COMMAND_STATS_NOW);
6077
6078 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6079 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6080 bnx2_5706_serdes_timer(bp);
6081 else
6082 bnx2_5708_serdes_timer(bp);
6083 }
6084
6085 bnx2_restart_timer:
6086 mod_timer(&bp->timer, jiffies + bp->current_interval);
6087 }
6088
6089 static int
6090 bnx2_request_irq(struct bnx2 *bp)
6091 {
6092 unsigned long flags;
6093 struct bnx2_irq *irq;
6094 int rc = 0, i;
6095
6096 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6097 flags = 0;
6098 else
6099 flags = IRQF_SHARED;
6100
6101 for (i = 0; i < bp->irq_nvecs; i++) {
6102 irq = &bp->irq_tbl[i];
6103 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6104 &bp->bnx2_napi[i]);
6105 if (rc)
6106 break;
6107 irq->requested = 1;
6108 }
6109 return rc;
6110 }
6111
6112 static void
6113 bnx2_free_irq(struct bnx2 *bp)
6114 {
6115 struct bnx2_irq *irq;
6116 int i;
6117
6118 for (i = 0; i < bp->irq_nvecs; i++) {
6119 irq = &bp->irq_tbl[i];
6120 if (irq->requested)
6121 free_irq(irq->vector, &bp->bnx2_napi[i]);
6122 irq->requested = 0;
6123 }
6124 if (bp->flags & BNX2_FLAG_USING_MSI)
6125 pci_disable_msi(bp->pdev);
6126 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6127 pci_disable_msix(bp->pdev);
6128
6129 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6130 }
6131
6132 static void
6133 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6134 {
6135 int i, rc;
6136 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6137 struct net_device *dev = bp->dev;
6138 const int len = sizeof(bp->irq_tbl[0].name);
6139
6140 bnx2_setup_msix_tbl(bp);
6141 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6142 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6143 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6144
6145 /* Need to flush the previous three writes to ensure MSI-X
6146 * is setup properly */
6147 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6148
6149 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6150 msix_ent[i].entry = i;
6151 msix_ent[i].vector = 0;
6152 }
6153
6154 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6155 if (rc != 0)
6156 return;
6157
6158 bp->irq_nvecs = msix_vecs;
6159 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6160 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6161 bp->irq_tbl[i].vector = msix_ent[i].vector;
6162 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6163 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6164 }
6165 }
6166
6167 static void
6168 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6169 {
6170 int cpus = num_online_cpus();
6171 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6172
6173 bp->irq_tbl[0].handler = bnx2_interrupt;
6174 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6175 bp->irq_nvecs = 1;
6176 bp->irq_tbl[0].vector = bp->pdev->irq;
6177
6178 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6179 bnx2_enable_msix(bp, msix_vecs);
6180
6181 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6182 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6183 if (pci_enable_msi(bp->pdev) == 0) {
6184 bp->flags |= BNX2_FLAG_USING_MSI;
6185 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6186 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6187 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6188 } else
6189 bp->irq_tbl[0].handler = bnx2_msi;
6190
6191 bp->irq_tbl[0].vector = bp->pdev->irq;
6192 }
6193 }
6194
6195 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6196 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6197
6198 bp->num_rx_rings = bp->irq_nvecs;
6199 }
6200
6201 /* Called with rtnl_lock */
6202 static int
6203 bnx2_open(struct net_device *dev)
6204 {
6205 struct bnx2 *bp = netdev_priv(dev);
6206 int rc;
6207
6208 netif_carrier_off(dev);
6209
6210 bnx2_set_power_state(bp, PCI_D0);
6211 bnx2_disable_int(bp);
6212
6213 bnx2_setup_int_mode(bp, disable_msi);
6214 bnx2_init_napi(bp);
6215 bnx2_napi_enable(bp);
6216 rc = bnx2_alloc_mem(bp);
6217 if (rc)
6218 goto open_err;
6219
6220 rc = bnx2_request_irq(bp);
6221 if (rc)
6222 goto open_err;
6223
6224 rc = bnx2_init_nic(bp, 1);
6225 if (rc)
6226 goto open_err;
6227
6228 mod_timer(&bp->timer, jiffies + bp->current_interval);
6229
6230 atomic_set(&bp->intr_sem, 0);
6231
6232 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6233
6234 bnx2_enable_int(bp);
6235
6236 if (bp->flags & BNX2_FLAG_USING_MSI) {
6237 /* Test MSI to make sure it is working
6238 * If MSI test fails, go back to INTx mode
6239 */
6240 if (bnx2_test_intr(bp) != 0) {
6241 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6242
6243 bnx2_disable_int(bp);
6244 bnx2_free_irq(bp);
6245
6246 bnx2_setup_int_mode(bp, 1);
6247
6248 rc = bnx2_init_nic(bp, 0);
6249
6250 if (!rc)
6251 rc = bnx2_request_irq(bp);
6252
6253 if (rc) {
6254 del_timer_sync(&bp->timer);
6255 goto open_err;
6256 }
6257 bnx2_enable_int(bp);
6258 }
6259 }
6260 if (bp->flags & BNX2_FLAG_USING_MSI)
6261 netdev_info(dev, "using MSI\n");
6262 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6263 netdev_info(dev, "using MSIX\n");
6264
6265 netif_tx_start_all_queues(dev);
6266
6267 return 0;
6268
6269 open_err:
6270 bnx2_napi_disable(bp);
6271 bnx2_free_skbs(bp);
6272 bnx2_free_irq(bp);
6273 bnx2_free_mem(bp);
6274 bnx2_del_napi(bp);
6275 return rc;
6276 }
6277
6278 static void
6279 bnx2_reset_task(struct work_struct *work)
6280 {
6281 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6282
6283 rtnl_lock();
6284 if (!netif_running(bp->dev)) {
6285 rtnl_unlock();
6286 return;
6287 }
6288
6289 bnx2_netif_stop(bp, true);
6290
6291 bnx2_init_nic(bp, 1);
6292
6293 atomic_set(&bp->intr_sem, 1);
6294 bnx2_netif_start(bp, true);
6295 rtnl_unlock();
6296 }
6297
6298 static void
6299 bnx2_dump_state(struct bnx2 *bp)
6300 {
6301 struct net_device *dev = bp->dev;
6302 u32 mcp_p0, mcp_p1;
6303
6304 netdev_err(dev, "DEBUG: intr_sem[%x]\n", atomic_read(&bp->intr_sem));
6305 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
6306 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6307 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6308 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
6309 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6310 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6311 mcp_p0 = BNX2_MCP_STATE_P0;
6312 mcp_p1 = BNX2_MCP_STATE_P1;
6313 } else {
6314 mcp_p0 = BNX2_MCP_STATE_P0_5708;
6315 mcp_p1 = BNX2_MCP_STATE_P1_5708;
6316 }
6317 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
6318 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
6319 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6320 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6321 if (bp->flags & BNX2_FLAG_USING_MSIX)
6322 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6323 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6324 }
6325
6326 static void
6327 bnx2_tx_timeout(struct net_device *dev)
6328 {
6329 struct bnx2 *bp = netdev_priv(dev);
6330
6331 bnx2_dump_state(bp);
6332
6333 /* This allows the netif to be shutdown gracefully before resetting */
6334 schedule_work(&bp->reset_task);
6335 }
6336
6337 #ifdef BCM_VLAN
6338 /* Called with rtnl_lock */
6339 static void
6340 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6341 {
6342 struct bnx2 *bp = netdev_priv(dev);
6343
6344 if (netif_running(dev))
6345 bnx2_netif_stop(bp, false);
6346
6347 bp->vlgrp = vlgrp;
6348
6349 if (!netif_running(dev))
6350 return;
6351
6352 bnx2_set_rx_mode(dev);
6353 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6354 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6355
6356 bnx2_netif_start(bp, false);
6357 }
6358 #endif
6359
6360 /* Called with netif_tx_lock.
6361 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6362 * netif_wake_queue().
6363 */
6364 static netdev_tx_t
6365 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6366 {
6367 struct bnx2 *bp = netdev_priv(dev);
6368 dma_addr_t mapping;
6369 struct tx_bd *txbd;
6370 struct sw_tx_bd *tx_buf;
6371 u32 len, vlan_tag_flags, last_frag, mss;
6372 u16 prod, ring_prod;
6373 int i;
6374 struct bnx2_napi *bnapi;
6375 struct bnx2_tx_ring_info *txr;
6376 struct netdev_queue *txq;
6377
6378 /* Determine which tx ring we will be placed on */
6379 i = skb_get_queue_mapping(skb);
6380 bnapi = &bp->bnx2_napi[i];
6381 txr = &bnapi->tx_ring;
6382 txq = netdev_get_tx_queue(dev, i);
6383
6384 if (unlikely(bnx2_tx_avail(bp, txr) <
6385 (skb_shinfo(skb)->nr_frags + 1))) {
6386 netif_tx_stop_queue(txq);
6387 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6388
6389 return NETDEV_TX_BUSY;
6390 }
6391 len = skb_headlen(skb);
6392 prod = txr->tx_prod;
6393 ring_prod = TX_RING_IDX(prod);
6394
6395 vlan_tag_flags = 0;
6396 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6397 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6398 }
6399
6400 #ifdef BCM_VLAN
6401 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6402 vlan_tag_flags |=
6403 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6404 }
6405 #endif
6406 if ((mss = skb_shinfo(skb)->gso_size)) {
6407 u32 tcp_opt_len;
6408 struct iphdr *iph;
6409
6410 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6411
6412 tcp_opt_len = tcp_optlen(skb);
6413
6414 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6415 u32 tcp_off = skb_transport_offset(skb) -
6416 sizeof(struct ipv6hdr) - ETH_HLEN;
6417
6418 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6419 TX_BD_FLAGS_SW_FLAGS;
6420 if (likely(tcp_off == 0))
6421 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6422 else {
6423 tcp_off >>= 3;
6424 vlan_tag_flags |= ((tcp_off & 0x3) <<
6425 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6426 ((tcp_off & 0x10) <<
6427 TX_BD_FLAGS_TCP6_OFF4_SHL);
6428 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6429 }
6430 } else {
6431 iph = ip_hdr(skb);
6432 if (tcp_opt_len || (iph->ihl > 5)) {
6433 vlan_tag_flags |= ((iph->ihl - 5) +
6434 (tcp_opt_len >> 2)) << 8;
6435 }
6436 }
6437 } else
6438 mss = 0;
6439
6440 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6441 if (pci_dma_mapping_error(bp->pdev, mapping)) {
6442 dev_kfree_skb(skb);
6443 return NETDEV_TX_OK;
6444 }
6445
6446 tx_buf = &txr->tx_buf_ring[ring_prod];
6447 tx_buf->skb = skb;
6448 dma_unmap_addr_set(tx_buf, mapping, mapping);
6449
6450 txbd = &txr->tx_desc_ring[ring_prod];
6451
6452 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6453 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6454 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6455 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6456
6457 last_frag = skb_shinfo(skb)->nr_frags;
6458 tx_buf->nr_frags = last_frag;
6459 tx_buf->is_gso = skb_is_gso(skb);
6460
6461 for (i = 0; i < last_frag; i++) {
6462 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6463
6464 prod = NEXT_TX_BD(prod);
6465 ring_prod = TX_RING_IDX(prod);
6466 txbd = &txr->tx_desc_ring[ring_prod];
6467
6468 len = frag->size;
6469 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6470 len, PCI_DMA_TODEVICE);
6471 if (pci_dma_mapping_error(bp->pdev, mapping))
6472 goto dma_error;
6473 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6474 mapping);
6475
6476 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6477 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6478 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6479 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6480
6481 }
6482 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6483
6484 prod = NEXT_TX_BD(prod);
6485 txr->tx_prod_bseq += skb->len;
6486
6487 REG_WR16(bp, txr->tx_bidx_addr, prod);
6488 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6489
6490 mmiowb();
6491
6492 txr->tx_prod = prod;
6493
6494 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6495 netif_tx_stop_queue(txq);
6496 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6497 netif_tx_wake_queue(txq);
6498 }
6499
6500 return NETDEV_TX_OK;
6501 dma_error:
6502 /* save value of frag that failed */
6503 last_frag = i;
6504
6505 /* start back at beginning and unmap skb */
6506 prod = txr->tx_prod;
6507 ring_prod = TX_RING_IDX(prod);
6508 tx_buf = &txr->tx_buf_ring[ring_prod];
6509 tx_buf->skb = NULL;
6510 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
6511 skb_headlen(skb), PCI_DMA_TODEVICE);
6512
6513 /* unmap remaining mapped pages */
6514 for (i = 0; i < last_frag; i++) {
6515 prod = NEXT_TX_BD(prod);
6516 ring_prod = TX_RING_IDX(prod);
6517 tx_buf = &txr->tx_buf_ring[ring_prod];
6518 pci_unmap_page(bp->pdev, dma_unmap_addr(tx_buf, mapping),
6519 skb_shinfo(skb)->frags[i].size,
6520 PCI_DMA_TODEVICE);
6521 }
6522
6523 dev_kfree_skb(skb);
6524 return NETDEV_TX_OK;
6525 }
6526
6527 /* Called with rtnl_lock */
6528 static int
6529 bnx2_close(struct net_device *dev)
6530 {
6531 struct bnx2 *bp = netdev_priv(dev);
6532
6533 cancel_work_sync(&bp->reset_task);
6534
6535 bnx2_disable_int_sync(bp);
6536 bnx2_napi_disable(bp);
6537 del_timer_sync(&bp->timer);
6538 bnx2_shutdown_chip(bp);
6539 bnx2_free_irq(bp);
6540 bnx2_free_skbs(bp);
6541 bnx2_free_mem(bp);
6542 bnx2_del_napi(bp);
6543 bp->link_up = 0;
6544 netif_carrier_off(bp->dev);
6545 bnx2_set_power_state(bp, PCI_D3hot);
6546 return 0;
6547 }
6548
6549 static void
6550 bnx2_save_stats(struct bnx2 *bp)
6551 {
6552 u32 *hw_stats = (u32 *) bp->stats_blk;
6553 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6554 int i;
6555
6556 /* The 1st 10 counters are 64-bit counters */
6557 for (i = 0; i < 20; i += 2) {
6558 u32 hi;
6559 u64 lo;
6560
6561 hi = temp_stats[i] + hw_stats[i];
6562 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6563 if (lo > 0xffffffff)
6564 hi++;
6565 temp_stats[i] = hi;
6566 temp_stats[i + 1] = lo & 0xffffffff;
6567 }
6568
6569 for ( ; i < sizeof(struct statistics_block) / 4; i++)
6570 temp_stats[i] += hw_stats[i];
6571 }
6572
6573 #define GET_64BIT_NET_STATS64(ctr) \
6574 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6575 (unsigned long) (ctr##_lo)
6576
6577 #define GET_64BIT_NET_STATS32(ctr) \
6578 (ctr##_lo)
6579
6580 #if (BITS_PER_LONG == 64)
6581 #define GET_64BIT_NET_STATS(ctr) \
6582 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6583 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6584 #else
6585 #define GET_64BIT_NET_STATS(ctr) \
6586 GET_64BIT_NET_STATS32(bp->stats_blk->ctr) + \
6587 GET_64BIT_NET_STATS32(bp->temp_stats_blk->ctr)
6588 #endif
6589
6590 #define GET_32BIT_NET_STATS(ctr) \
6591 (unsigned long) (bp->stats_blk->ctr + \
6592 bp->temp_stats_blk->ctr)
6593
6594 static struct net_device_stats *
6595 bnx2_get_stats(struct net_device *dev)
6596 {
6597 struct bnx2 *bp = netdev_priv(dev);
6598 struct net_device_stats *net_stats = &dev->stats;
6599
6600 if (bp->stats_blk == NULL) {
6601 return net_stats;
6602 }
6603 net_stats->rx_packets =
6604 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6605 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6606 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6607
6608 net_stats->tx_packets =
6609 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6610 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6611 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6612
6613 net_stats->rx_bytes =
6614 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6615
6616 net_stats->tx_bytes =
6617 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6618
6619 net_stats->multicast =
6620 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts);
6621
6622 net_stats->collisions =
6623 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6624
6625 net_stats->rx_length_errors =
6626 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6627 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6628
6629 net_stats->rx_over_errors =
6630 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6631 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6632
6633 net_stats->rx_frame_errors =
6634 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6635
6636 net_stats->rx_crc_errors =
6637 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6638
6639 net_stats->rx_errors = net_stats->rx_length_errors +
6640 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6641 net_stats->rx_crc_errors;
6642
6643 net_stats->tx_aborted_errors =
6644 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6645 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6646
6647 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6648 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6649 net_stats->tx_carrier_errors = 0;
6650 else {
6651 net_stats->tx_carrier_errors =
6652 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6653 }
6654
6655 net_stats->tx_errors =
6656 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6657 net_stats->tx_aborted_errors +
6658 net_stats->tx_carrier_errors;
6659
6660 net_stats->rx_missed_errors =
6661 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6662 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6663 GET_32BIT_NET_STATS(stat_FwRxDrop);
6664
6665 return net_stats;
6666 }
6667
6668 /* All ethtool functions called with rtnl_lock */
6669
6670 static int
6671 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6672 {
6673 struct bnx2 *bp = netdev_priv(dev);
6674 int support_serdes = 0, support_copper = 0;
6675
6676 cmd->supported = SUPPORTED_Autoneg;
6677 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6678 support_serdes = 1;
6679 support_copper = 1;
6680 } else if (bp->phy_port == PORT_FIBRE)
6681 support_serdes = 1;
6682 else
6683 support_copper = 1;
6684
6685 if (support_serdes) {
6686 cmd->supported |= SUPPORTED_1000baseT_Full |
6687 SUPPORTED_FIBRE;
6688 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6689 cmd->supported |= SUPPORTED_2500baseX_Full;
6690
6691 }
6692 if (support_copper) {
6693 cmd->supported |= SUPPORTED_10baseT_Half |
6694 SUPPORTED_10baseT_Full |
6695 SUPPORTED_100baseT_Half |
6696 SUPPORTED_100baseT_Full |
6697 SUPPORTED_1000baseT_Full |
6698 SUPPORTED_TP;
6699
6700 }
6701
6702 spin_lock_bh(&bp->phy_lock);
6703 cmd->port = bp->phy_port;
6704 cmd->advertising = bp->advertising;
6705
6706 if (bp->autoneg & AUTONEG_SPEED) {
6707 cmd->autoneg = AUTONEG_ENABLE;
6708 }
6709 else {
6710 cmd->autoneg = AUTONEG_DISABLE;
6711 }
6712
6713 if (netif_carrier_ok(dev)) {
6714 cmd->speed = bp->line_speed;
6715 cmd->duplex = bp->duplex;
6716 }
6717 else {
6718 cmd->speed = -1;
6719 cmd->duplex = -1;
6720 }
6721 spin_unlock_bh(&bp->phy_lock);
6722
6723 cmd->transceiver = XCVR_INTERNAL;
6724 cmd->phy_address = bp->phy_addr;
6725
6726 return 0;
6727 }
6728
6729 static int
6730 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6731 {
6732 struct bnx2 *bp = netdev_priv(dev);
6733 u8 autoneg = bp->autoneg;
6734 u8 req_duplex = bp->req_duplex;
6735 u16 req_line_speed = bp->req_line_speed;
6736 u32 advertising = bp->advertising;
6737 int err = -EINVAL;
6738
6739 spin_lock_bh(&bp->phy_lock);
6740
6741 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6742 goto err_out_unlock;
6743
6744 if (cmd->port != bp->phy_port &&
6745 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6746 goto err_out_unlock;
6747
6748 /* If device is down, we can store the settings only if the user
6749 * is setting the currently active port.
6750 */
6751 if (!netif_running(dev) && cmd->port != bp->phy_port)
6752 goto err_out_unlock;
6753
6754 if (cmd->autoneg == AUTONEG_ENABLE) {
6755 autoneg |= AUTONEG_SPEED;
6756
6757 advertising = cmd->advertising;
6758 if (cmd->port == PORT_TP) {
6759 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6760 if (!advertising)
6761 advertising = ETHTOOL_ALL_COPPER_SPEED;
6762 } else {
6763 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6764 if (!advertising)
6765 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6766 }
6767 advertising |= ADVERTISED_Autoneg;
6768 }
6769 else {
6770 if (cmd->port == PORT_FIBRE) {
6771 if ((cmd->speed != SPEED_1000 &&
6772 cmd->speed != SPEED_2500) ||
6773 (cmd->duplex != DUPLEX_FULL))
6774 goto err_out_unlock;
6775
6776 if (cmd->speed == SPEED_2500 &&
6777 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6778 goto err_out_unlock;
6779 }
6780 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6781 goto err_out_unlock;
6782
6783 autoneg &= ~AUTONEG_SPEED;
6784 req_line_speed = cmd->speed;
6785 req_duplex = cmd->duplex;
6786 advertising = 0;
6787 }
6788
6789 bp->autoneg = autoneg;
6790 bp->advertising = advertising;
6791 bp->req_line_speed = req_line_speed;
6792 bp->req_duplex = req_duplex;
6793
6794 err = 0;
6795 /* If device is down, the new settings will be picked up when it is
6796 * brought up.
6797 */
6798 if (netif_running(dev))
6799 err = bnx2_setup_phy(bp, cmd->port);
6800
6801 err_out_unlock:
6802 spin_unlock_bh(&bp->phy_lock);
6803
6804 return err;
6805 }
6806
6807 static void
6808 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6809 {
6810 struct bnx2 *bp = netdev_priv(dev);
6811
6812 strcpy(info->driver, DRV_MODULE_NAME);
6813 strcpy(info->version, DRV_MODULE_VERSION);
6814 strcpy(info->bus_info, pci_name(bp->pdev));
6815 strcpy(info->fw_version, bp->fw_version);
6816 }
6817
6818 #define BNX2_REGDUMP_LEN (32 * 1024)
6819
6820 static int
6821 bnx2_get_regs_len(struct net_device *dev)
6822 {
6823 return BNX2_REGDUMP_LEN;
6824 }
6825
6826 static void
6827 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6828 {
6829 u32 *p = _p, i, offset;
6830 u8 *orig_p = _p;
6831 struct bnx2 *bp = netdev_priv(dev);
6832 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6833 0x0800, 0x0880, 0x0c00, 0x0c10,
6834 0x0c30, 0x0d08, 0x1000, 0x101c,
6835 0x1040, 0x1048, 0x1080, 0x10a4,
6836 0x1400, 0x1490, 0x1498, 0x14f0,
6837 0x1500, 0x155c, 0x1580, 0x15dc,
6838 0x1600, 0x1658, 0x1680, 0x16d8,
6839 0x1800, 0x1820, 0x1840, 0x1854,
6840 0x1880, 0x1894, 0x1900, 0x1984,
6841 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6842 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6843 0x2000, 0x2030, 0x23c0, 0x2400,
6844 0x2800, 0x2820, 0x2830, 0x2850,
6845 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6846 0x3c00, 0x3c94, 0x4000, 0x4010,
6847 0x4080, 0x4090, 0x43c0, 0x4458,
6848 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6849 0x4fc0, 0x5010, 0x53c0, 0x5444,
6850 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6851 0x5fc0, 0x6000, 0x6400, 0x6428,
6852 0x6800, 0x6848, 0x684c, 0x6860,
6853 0x6888, 0x6910, 0x8000 };
6854
6855 regs->version = 0;
6856
6857 memset(p, 0, BNX2_REGDUMP_LEN);
6858
6859 if (!netif_running(bp->dev))
6860 return;
6861
6862 i = 0;
6863 offset = reg_boundaries[0];
6864 p += offset;
6865 while (offset < BNX2_REGDUMP_LEN) {
6866 *p++ = REG_RD(bp, offset);
6867 offset += 4;
6868 if (offset == reg_boundaries[i + 1]) {
6869 offset = reg_boundaries[i + 2];
6870 p = (u32 *) (orig_p + offset);
6871 i += 2;
6872 }
6873 }
6874 }
6875
6876 static void
6877 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6878 {
6879 struct bnx2 *bp = netdev_priv(dev);
6880
6881 if (bp->flags & BNX2_FLAG_NO_WOL) {
6882 wol->supported = 0;
6883 wol->wolopts = 0;
6884 }
6885 else {
6886 wol->supported = WAKE_MAGIC;
6887 if (bp->wol)
6888 wol->wolopts = WAKE_MAGIC;
6889 else
6890 wol->wolopts = 0;
6891 }
6892 memset(&wol->sopass, 0, sizeof(wol->sopass));
6893 }
6894
6895 static int
6896 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6897 {
6898 struct bnx2 *bp = netdev_priv(dev);
6899
6900 if (wol->wolopts & ~WAKE_MAGIC)
6901 return -EINVAL;
6902
6903 if (wol->wolopts & WAKE_MAGIC) {
6904 if (bp->flags & BNX2_FLAG_NO_WOL)
6905 return -EINVAL;
6906
6907 bp->wol = 1;
6908 }
6909 else {
6910 bp->wol = 0;
6911 }
6912 return 0;
6913 }
6914
6915 static int
6916 bnx2_nway_reset(struct net_device *dev)
6917 {
6918 struct bnx2 *bp = netdev_priv(dev);
6919 u32 bmcr;
6920
6921 if (!netif_running(dev))
6922 return -EAGAIN;
6923
6924 if (!(bp->autoneg & AUTONEG_SPEED)) {
6925 return -EINVAL;
6926 }
6927
6928 spin_lock_bh(&bp->phy_lock);
6929
6930 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6931 int rc;
6932
6933 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6934 spin_unlock_bh(&bp->phy_lock);
6935 return rc;
6936 }
6937
6938 /* Force a link down visible on the other side */
6939 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6940 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6941 spin_unlock_bh(&bp->phy_lock);
6942
6943 msleep(20);
6944
6945 spin_lock_bh(&bp->phy_lock);
6946
6947 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6948 bp->serdes_an_pending = 1;
6949 mod_timer(&bp->timer, jiffies + bp->current_interval);
6950 }
6951
6952 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6953 bmcr &= ~BMCR_LOOPBACK;
6954 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6955
6956 spin_unlock_bh(&bp->phy_lock);
6957
6958 return 0;
6959 }
6960
6961 static u32
6962 bnx2_get_link(struct net_device *dev)
6963 {
6964 struct bnx2 *bp = netdev_priv(dev);
6965
6966 return bp->link_up;
6967 }
6968
6969 static int
6970 bnx2_get_eeprom_len(struct net_device *dev)
6971 {
6972 struct bnx2 *bp = netdev_priv(dev);
6973
6974 if (bp->flash_info == NULL)
6975 return 0;
6976
6977 return (int) bp->flash_size;
6978 }
6979
6980 static int
6981 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6982 u8 *eebuf)
6983 {
6984 struct bnx2 *bp = netdev_priv(dev);
6985 int rc;
6986
6987 if (!netif_running(dev))
6988 return -EAGAIN;
6989
6990 /* parameters already validated in ethtool_get_eeprom */
6991
6992 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6993
6994 return rc;
6995 }
6996
6997 static int
6998 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6999 u8 *eebuf)
7000 {
7001 struct bnx2 *bp = netdev_priv(dev);
7002 int rc;
7003
7004 if (!netif_running(dev))
7005 return -EAGAIN;
7006
7007 /* parameters already validated in ethtool_set_eeprom */
7008
7009 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7010
7011 return rc;
7012 }
7013
7014 static int
7015 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7016 {
7017 struct bnx2 *bp = netdev_priv(dev);
7018
7019 memset(coal, 0, sizeof(struct ethtool_coalesce));
7020
7021 coal->rx_coalesce_usecs = bp->rx_ticks;
7022 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7023 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7024 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7025
7026 coal->tx_coalesce_usecs = bp->tx_ticks;
7027 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7028 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7029 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7030
7031 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7032
7033 return 0;
7034 }
7035
7036 static int
7037 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7038 {
7039 struct bnx2 *bp = netdev_priv(dev);
7040
7041 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7042 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7043
7044 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7045 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7046
7047 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7048 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7049
7050 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7051 if (bp->rx_quick_cons_trip_int > 0xff)
7052 bp->rx_quick_cons_trip_int = 0xff;
7053
7054 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7055 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7056
7057 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7058 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7059
7060 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7061 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7062
7063 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7064 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7065 0xff;
7066
7067 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7068 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7069 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7070 bp->stats_ticks = USEC_PER_SEC;
7071 }
7072 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7073 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7074 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7075
7076 if (netif_running(bp->dev)) {
7077 bnx2_netif_stop(bp, true);
7078 bnx2_init_nic(bp, 0);
7079 bnx2_netif_start(bp, true);
7080 }
7081
7082 return 0;
7083 }
7084
7085 static void
7086 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7087 {
7088 struct bnx2 *bp = netdev_priv(dev);
7089
7090 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7091 ering->rx_mini_max_pending = 0;
7092 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7093
7094 ering->rx_pending = bp->rx_ring_size;
7095 ering->rx_mini_pending = 0;
7096 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7097
7098 ering->tx_max_pending = MAX_TX_DESC_CNT;
7099 ering->tx_pending = bp->tx_ring_size;
7100 }
7101
7102 static int
7103 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7104 {
7105 if (netif_running(bp->dev)) {
7106 /* Reset will erase chipset stats; save them */
7107 bnx2_save_stats(bp);
7108
7109 bnx2_netif_stop(bp, true);
7110 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7111 bnx2_free_skbs(bp);
7112 bnx2_free_mem(bp);
7113 }
7114
7115 bnx2_set_rx_ring_size(bp, rx);
7116 bp->tx_ring_size = tx;
7117
7118 if (netif_running(bp->dev)) {
7119 int rc;
7120
7121 rc = bnx2_alloc_mem(bp);
7122 if (!rc)
7123 rc = bnx2_init_nic(bp, 0);
7124
7125 if (rc) {
7126 bnx2_napi_enable(bp);
7127 dev_close(bp->dev);
7128 return rc;
7129 }
7130 #ifdef BCM_CNIC
7131 mutex_lock(&bp->cnic_lock);
7132 /* Let cnic know about the new status block. */
7133 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7134 bnx2_setup_cnic_irq_info(bp);
7135 mutex_unlock(&bp->cnic_lock);
7136 #endif
7137 bnx2_netif_start(bp, true);
7138 }
7139 return 0;
7140 }
7141
7142 static int
7143 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7144 {
7145 struct bnx2 *bp = netdev_priv(dev);
7146 int rc;
7147
7148 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7149 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7150 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7151
7152 return -EINVAL;
7153 }
7154 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7155 return rc;
7156 }
7157
7158 static void
7159 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7160 {
7161 struct bnx2 *bp = netdev_priv(dev);
7162
7163 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7164 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7165 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7166 }
7167
7168 static int
7169 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7170 {
7171 struct bnx2 *bp = netdev_priv(dev);
7172
7173 bp->req_flow_ctrl = 0;
7174 if (epause->rx_pause)
7175 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7176 if (epause->tx_pause)
7177 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7178
7179 if (epause->autoneg) {
7180 bp->autoneg |= AUTONEG_FLOW_CTRL;
7181 }
7182 else {
7183 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7184 }
7185
7186 if (netif_running(dev)) {
7187 spin_lock_bh(&bp->phy_lock);
7188 bnx2_setup_phy(bp, bp->phy_port);
7189 spin_unlock_bh(&bp->phy_lock);
7190 }
7191
7192 return 0;
7193 }
7194
7195 static u32
7196 bnx2_get_rx_csum(struct net_device *dev)
7197 {
7198 struct bnx2 *bp = netdev_priv(dev);
7199
7200 return bp->rx_csum;
7201 }
7202
7203 static int
7204 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7205 {
7206 struct bnx2 *bp = netdev_priv(dev);
7207
7208 bp->rx_csum = data;
7209 return 0;
7210 }
7211
7212 static int
7213 bnx2_set_tso(struct net_device *dev, u32 data)
7214 {
7215 struct bnx2 *bp = netdev_priv(dev);
7216
7217 if (data) {
7218 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7219 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7220 dev->features |= NETIF_F_TSO6;
7221 } else
7222 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7223 NETIF_F_TSO_ECN);
7224 return 0;
7225 }
7226
7227 static struct {
7228 char string[ETH_GSTRING_LEN];
7229 } bnx2_stats_str_arr[] = {
7230 { "rx_bytes" },
7231 { "rx_error_bytes" },
7232 { "tx_bytes" },
7233 { "tx_error_bytes" },
7234 { "rx_ucast_packets" },
7235 { "rx_mcast_packets" },
7236 { "rx_bcast_packets" },
7237 { "tx_ucast_packets" },
7238 { "tx_mcast_packets" },
7239 { "tx_bcast_packets" },
7240 { "tx_mac_errors" },
7241 { "tx_carrier_errors" },
7242 { "rx_crc_errors" },
7243 { "rx_align_errors" },
7244 { "tx_single_collisions" },
7245 { "tx_multi_collisions" },
7246 { "tx_deferred" },
7247 { "tx_excess_collisions" },
7248 { "tx_late_collisions" },
7249 { "tx_total_collisions" },
7250 { "rx_fragments" },
7251 { "rx_jabbers" },
7252 { "rx_undersize_packets" },
7253 { "rx_oversize_packets" },
7254 { "rx_64_byte_packets" },
7255 { "rx_65_to_127_byte_packets" },
7256 { "rx_128_to_255_byte_packets" },
7257 { "rx_256_to_511_byte_packets" },
7258 { "rx_512_to_1023_byte_packets" },
7259 { "rx_1024_to_1522_byte_packets" },
7260 { "rx_1523_to_9022_byte_packets" },
7261 { "tx_64_byte_packets" },
7262 { "tx_65_to_127_byte_packets" },
7263 { "tx_128_to_255_byte_packets" },
7264 { "tx_256_to_511_byte_packets" },
7265 { "tx_512_to_1023_byte_packets" },
7266 { "tx_1024_to_1522_byte_packets" },
7267 { "tx_1523_to_9022_byte_packets" },
7268 { "rx_xon_frames" },
7269 { "rx_xoff_frames" },
7270 { "tx_xon_frames" },
7271 { "tx_xoff_frames" },
7272 { "rx_mac_ctrl_frames" },
7273 { "rx_filtered_packets" },
7274 { "rx_ftq_discards" },
7275 { "rx_discards" },
7276 { "rx_fw_discards" },
7277 };
7278
7279 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7280 sizeof(bnx2_stats_str_arr[0]))
7281
7282 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7283
7284 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7285 STATS_OFFSET32(stat_IfHCInOctets_hi),
7286 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7287 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7288 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7289 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7290 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7291 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7292 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7293 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7294 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7295 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7296 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7297 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7298 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7299 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7300 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7301 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7302 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7303 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7304 STATS_OFFSET32(stat_EtherStatsCollisions),
7305 STATS_OFFSET32(stat_EtherStatsFragments),
7306 STATS_OFFSET32(stat_EtherStatsJabbers),
7307 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7308 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7309 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7310 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7311 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7312 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7313 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7314 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7315 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7316 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7317 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7318 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7319 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7320 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7321 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7322 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7323 STATS_OFFSET32(stat_XonPauseFramesReceived),
7324 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7325 STATS_OFFSET32(stat_OutXonSent),
7326 STATS_OFFSET32(stat_OutXoffSent),
7327 STATS_OFFSET32(stat_MacControlFramesReceived),
7328 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7329 STATS_OFFSET32(stat_IfInFTQDiscards),
7330 STATS_OFFSET32(stat_IfInMBUFDiscards),
7331 STATS_OFFSET32(stat_FwRxDrop),
7332 };
7333
7334 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7335 * skipped because of errata.
7336 */
7337 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7338 8,0,8,8,8,8,8,8,8,8,
7339 4,0,4,4,4,4,4,4,4,4,
7340 4,4,4,4,4,4,4,4,4,4,
7341 4,4,4,4,4,4,4,4,4,4,
7342 4,4,4,4,4,4,4,
7343 };
7344
7345 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7346 8,0,8,8,8,8,8,8,8,8,
7347 4,4,4,4,4,4,4,4,4,4,
7348 4,4,4,4,4,4,4,4,4,4,
7349 4,4,4,4,4,4,4,4,4,4,
7350 4,4,4,4,4,4,4,
7351 };
7352
7353 #define BNX2_NUM_TESTS 6
7354
7355 static struct {
7356 char string[ETH_GSTRING_LEN];
7357 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7358 { "register_test (offline)" },
7359 { "memory_test (offline)" },
7360 { "loopback_test (offline)" },
7361 { "nvram_test (online)" },
7362 { "interrupt_test (online)" },
7363 { "link_test (online)" },
7364 };
7365
7366 static int
7367 bnx2_get_sset_count(struct net_device *dev, int sset)
7368 {
7369 switch (sset) {
7370 case ETH_SS_TEST:
7371 return BNX2_NUM_TESTS;
7372 case ETH_SS_STATS:
7373 return BNX2_NUM_STATS;
7374 default:
7375 return -EOPNOTSUPP;
7376 }
7377 }
7378
7379 static void
7380 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7381 {
7382 struct bnx2 *bp = netdev_priv(dev);
7383
7384 bnx2_set_power_state(bp, PCI_D0);
7385
7386 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7387 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7388 int i;
7389
7390 bnx2_netif_stop(bp, true);
7391 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7392 bnx2_free_skbs(bp);
7393
7394 if (bnx2_test_registers(bp) != 0) {
7395 buf[0] = 1;
7396 etest->flags |= ETH_TEST_FL_FAILED;
7397 }
7398 if (bnx2_test_memory(bp) != 0) {
7399 buf[1] = 1;
7400 etest->flags |= ETH_TEST_FL_FAILED;
7401 }
7402 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7403 etest->flags |= ETH_TEST_FL_FAILED;
7404
7405 if (!netif_running(bp->dev))
7406 bnx2_shutdown_chip(bp);
7407 else {
7408 bnx2_init_nic(bp, 1);
7409 bnx2_netif_start(bp, true);
7410 }
7411
7412 /* wait for link up */
7413 for (i = 0; i < 7; i++) {
7414 if (bp->link_up)
7415 break;
7416 msleep_interruptible(1000);
7417 }
7418 }
7419
7420 if (bnx2_test_nvram(bp) != 0) {
7421 buf[3] = 1;
7422 etest->flags |= ETH_TEST_FL_FAILED;
7423 }
7424 if (bnx2_test_intr(bp) != 0) {
7425 buf[4] = 1;
7426 etest->flags |= ETH_TEST_FL_FAILED;
7427 }
7428
7429 if (bnx2_test_link(bp) != 0) {
7430 buf[5] = 1;
7431 etest->flags |= ETH_TEST_FL_FAILED;
7432
7433 }
7434 if (!netif_running(bp->dev))
7435 bnx2_set_power_state(bp, PCI_D3hot);
7436 }
7437
7438 static void
7439 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7440 {
7441 switch (stringset) {
7442 case ETH_SS_STATS:
7443 memcpy(buf, bnx2_stats_str_arr,
7444 sizeof(bnx2_stats_str_arr));
7445 break;
7446 case ETH_SS_TEST:
7447 memcpy(buf, bnx2_tests_str_arr,
7448 sizeof(bnx2_tests_str_arr));
7449 break;
7450 }
7451 }
7452
7453 static void
7454 bnx2_get_ethtool_stats(struct net_device *dev,
7455 struct ethtool_stats *stats, u64 *buf)
7456 {
7457 struct bnx2 *bp = netdev_priv(dev);
7458 int i;
7459 u32 *hw_stats = (u32 *) bp->stats_blk;
7460 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7461 u8 *stats_len_arr = NULL;
7462
7463 if (hw_stats == NULL) {
7464 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7465 return;
7466 }
7467
7468 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7469 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7470 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7471 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7472 stats_len_arr = bnx2_5706_stats_len_arr;
7473 else
7474 stats_len_arr = bnx2_5708_stats_len_arr;
7475
7476 for (i = 0; i < BNX2_NUM_STATS; i++) {
7477 unsigned long offset;
7478
7479 if (stats_len_arr[i] == 0) {
7480 /* skip this counter */
7481 buf[i] = 0;
7482 continue;
7483 }
7484
7485 offset = bnx2_stats_offset_arr[i];
7486 if (stats_len_arr[i] == 4) {
7487 /* 4-byte counter */
7488 buf[i] = (u64) *(hw_stats + offset) +
7489 *(temp_stats + offset);
7490 continue;
7491 }
7492 /* 8-byte counter */
7493 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7494 *(hw_stats + offset + 1) +
7495 (((u64) *(temp_stats + offset)) << 32) +
7496 *(temp_stats + offset + 1);
7497 }
7498 }
7499
7500 static int
7501 bnx2_phys_id(struct net_device *dev, u32 data)
7502 {
7503 struct bnx2 *bp = netdev_priv(dev);
7504 int i;
7505 u32 save;
7506
7507 bnx2_set_power_state(bp, PCI_D0);
7508
7509 if (data == 0)
7510 data = 2;
7511
7512 save = REG_RD(bp, BNX2_MISC_CFG);
7513 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7514
7515 for (i = 0; i < (data * 2); i++) {
7516 if ((i % 2) == 0) {
7517 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7518 }
7519 else {
7520 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7521 BNX2_EMAC_LED_1000MB_OVERRIDE |
7522 BNX2_EMAC_LED_100MB_OVERRIDE |
7523 BNX2_EMAC_LED_10MB_OVERRIDE |
7524 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7525 BNX2_EMAC_LED_TRAFFIC);
7526 }
7527 msleep_interruptible(500);
7528 if (signal_pending(current))
7529 break;
7530 }
7531 REG_WR(bp, BNX2_EMAC_LED, 0);
7532 REG_WR(bp, BNX2_MISC_CFG, save);
7533
7534 if (!netif_running(dev))
7535 bnx2_set_power_state(bp, PCI_D3hot);
7536
7537 return 0;
7538 }
7539
7540 static int
7541 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7542 {
7543 struct bnx2 *bp = netdev_priv(dev);
7544
7545 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7546 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7547 else
7548 return (ethtool_op_set_tx_csum(dev, data));
7549 }
7550
7551 static const struct ethtool_ops bnx2_ethtool_ops = {
7552 .get_settings = bnx2_get_settings,
7553 .set_settings = bnx2_set_settings,
7554 .get_drvinfo = bnx2_get_drvinfo,
7555 .get_regs_len = bnx2_get_regs_len,
7556 .get_regs = bnx2_get_regs,
7557 .get_wol = bnx2_get_wol,
7558 .set_wol = bnx2_set_wol,
7559 .nway_reset = bnx2_nway_reset,
7560 .get_link = bnx2_get_link,
7561 .get_eeprom_len = bnx2_get_eeprom_len,
7562 .get_eeprom = bnx2_get_eeprom,
7563 .set_eeprom = bnx2_set_eeprom,
7564 .get_coalesce = bnx2_get_coalesce,
7565 .set_coalesce = bnx2_set_coalesce,
7566 .get_ringparam = bnx2_get_ringparam,
7567 .set_ringparam = bnx2_set_ringparam,
7568 .get_pauseparam = bnx2_get_pauseparam,
7569 .set_pauseparam = bnx2_set_pauseparam,
7570 .get_rx_csum = bnx2_get_rx_csum,
7571 .set_rx_csum = bnx2_set_rx_csum,
7572 .set_tx_csum = bnx2_set_tx_csum,
7573 .set_sg = ethtool_op_set_sg,
7574 .set_tso = bnx2_set_tso,
7575 .self_test = bnx2_self_test,
7576 .get_strings = bnx2_get_strings,
7577 .phys_id = bnx2_phys_id,
7578 .get_ethtool_stats = bnx2_get_ethtool_stats,
7579 .get_sset_count = bnx2_get_sset_count,
7580 };
7581
7582 /* Called with rtnl_lock */
7583 static int
7584 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7585 {
7586 struct mii_ioctl_data *data = if_mii(ifr);
7587 struct bnx2 *bp = netdev_priv(dev);
7588 int err;
7589
7590 switch(cmd) {
7591 case SIOCGMIIPHY:
7592 data->phy_id = bp->phy_addr;
7593
7594 /* fallthru */
7595 case SIOCGMIIREG: {
7596 u32 mii_regval;
7597
7598 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7599 return -EOPNOTSUPP;
7600
7601 if (!netif_running(dev))
7602 return -EAGAIN;
7603
7604 spin_lock_bh(&bp->phy_lock);
7605 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7606 spin_unlock_bh(&bp->phy_lock);
7607
7608 data->val_out = mii_regval;
7609
7610 return err;
7611 }
7612
7613 case SIOCSMIIREG:
7614 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7615 return -EOPNOTSUPP;
7616
7617 if (!netif_running(dev))
7618 return -EAGAIN;
7619
7620 spin_lock_bh(&bp->phy_lock);
7621 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7622 spin_unlock_bh(&bp->phy_lock);
7623
7624 return err;
7625
7626 default:
7627 /* do nothing */
7628 break;
7629 }
7630 return -EOPNOTSUPP;
7631 }
7632
7633 /* Called with rtnl_lock */
7634 static int
7635 bnx2_change_mac_addr(struct net_device *dev, void *p)
7636 {
7637 struct sockaddr *addr = p;
7638 struct bnx2 *bp = netdev_priv(dev);
7639
7640 if (!is_valid_ether_addr(addr->sa_data))
7641 return -EINVAL;
7642
7643 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7644 if (netif_running(dev))
7645 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7646
7647 return 0;
7648 }
7649
7650 /* Called with rtnl_lock */
7651 static int
7652 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7653 {
7654 struct bnx2 *bp = netdev_priv(dev);
7655
7656 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7657 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7658 return -EINVAL;
7659
7660 dev->mtu = new_mtu;
7661 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7662 }
7663
7664 #ifdef CONFIG_NET_POLL_CONTROLLER
7665 static void
7666 poll_bnx2(struct net_device *dev)
7667 {
7668 struct bnx2 *bp = netdev_priv(dev);
7669 int i;
7670
7671 for (i = 0; i < bp->irq_nvecs; i++) {
7672 struct bnx2_irq *irq = &bp->irq_tbl[i];
7673
7674 disable_irq(irq->vector);
7675 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7676 enable_irq(irq->vector);
7677 }
7678 }
7679 #endif
7680
7681 static void __devinit
7682 bnx2_get_5709_media(struct bnx2 *bp)
7683 {
7684 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7685 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7686 u32 strap;
7687
7688 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7689 return;
7690 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7691 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7692 return;
7693 }
7694
7695 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7696 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7697 else
7698 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7699
7700 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7701 switch (strap) {
7702 case 0x4:
7703 case 0x5:
7704 case 0x6:
7705 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7706 return;
7707 }
7708 } else {
7709 switch (strap) {
7710 case 0x1:
7711 case 0x2:
7712 case 0x4:
7713 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7714 return;
7715 }
7716 }
7717 }
7718
7719 static void __devinit
7720 bnx2_get_pci_speed(struct bnx2 *bp)
7721 {
7722 u32 reg;
7723
7724 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7725 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7726 u32 clkreg;
7727
7728 bp->flags |= BNX2_FLAG_PCIX;
7729
7730 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7731
7732 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7733 switch (clkreg) {
7734 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7735 bp->bus_speed_mhz = 133;
7736 break;
7737
7738 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7739 bp->bus_speed_mhz = 100;
7740 break;
7741
7742 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7743 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7744 bp->bus_speed_mhz = 66;
7745 break;
7746
7747 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7748 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7749 bp->bus_speed_mhz = 50;
7750 break;
7751
7752 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7753 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7754 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7755 bp->bus_speed_mhz = 33;
7756 break;
7757 }
7758 }
7759 else {
7760 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7761 bp->bus_speed_mhz = 66;
7762 else
7763 bp->bus_speed_mhz = 33;
7764 }
7765
7766 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7767 bp->flags |= BNX2_FLAG_PCI_32BIT;
7768
7769 }
7770
7771 static void __devinit
7772 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7773 {
7774 int rc, i, j;
7775 u8 *data;
7776 unsigned int block_end, rosize, len;
7777
7778 #define BNX2_VPD_NVRAM_OFFSET 0x300
7779 #define BNX2_VPD_LEN 128
7780 #define BNX2_MAX_VER_SLEN 30
7781
7782 data = kmalloc(256, GFP_KERNEL);
7783 if (!data)
7784 return;
7785
7786 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7787 BNX2_VPD_LEN);
7788 if (rc)
7789 goto vpd_done;
7790
7791 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7792 data[i] = data[i + BNX2_VPD_LEN + 3];
7793 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7794 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7795 data[i + 3] = data[i + BNX2_VPD_LEN];
7796 }
7797
7798 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7799 if (i < 0)
7800 goto vpd_done;
7801
7802 rosize = pci_vpd_lrdt_size(&data[i]);
7803 i += PCI_VPD_LRDT_TAG_SIZE;
7804 block_end = i + rosize;
7805
7806 if (block_end > BNX2_VPD_LEN)
7807 goto vpd_done;
7808
7809 j = pci_vpd_find_info_keyword(data, i, rosize,
7810 PCI_VPD_RO_KEYWORD_MFR_ID);
7811 if (j < 0)
7812 goto vpd_done;
7813
7814 len = pci_vpd_info_field_size(&data[j]);
7815
7816 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7817 if (j + len > block_end || len != 4 ||
7818 memcmp(&data[j], "1028", 4))
7819 goto vpd_done;
7820
7821 j = pci_vpd_find_info_keyword(data, i, rosize,
7822 PCI_VPD_RO_KEYWORD_VENDOR0);
7823 if (j < 0)
7824 goto vpd_done;
7825
7826 len = pci_vpd_info_field_size(&data[j]);
7827
7828 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7829 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
7830 goto vpd_done;
7831
7832 memcpy(bp->fw_version, &data[j], len);
7833 bp->fw_version[len] = ' ';
7834
7835 vpd_done:
7836 kfree(data);
7837 }
7838
7839 static int __devinit
7840 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7841 {
7842 struct bnx2 *bp;
7843 unsigned long mem_len;
7844 int rc, i, j;
7845 u32 reg;
7846 u64 dma_mask, persist_dma_mask;
7847
7848 SET_NETDEV_DEV(dev, &pdev->dev);
7849 bp = netdev_priv(dev);
7850
7851 bp->flags = 0;
7852 bp->phy_flags = 0;
7853
7854 bp->temp_stats_blk =
7855 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7856
7857 if (bp->temp_stats_blk == NULL) {
7858 rc = -ENOMEM;
7859 goto err_out;
7860 }
7861
7862 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7863 rc = pci_enable_device(pdev);
7864 if (rc) {
7865 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7866 goto err_out;
7867 }
7868
7869 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7870 dev_err(&pdev->dev,
7871 "Cannot find PCI device base address, aborting\n");
7872 rc = -ENODEV;
7873 goto err_out_disable;
7874 }
7875
7876 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7877 if (rc) {
7878 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7879 goto err_out_disable;
7880 }
7881
7882 pci_set_master(pdev);
7883 pci_save_state(pdev);
7884
7885 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7886 if (bp->pm_cap == 0) {
7887 dev_err(&pdev->dev,
7888 "Cannot find power management capability, aborting\n");
7889 rc = -EIO;
7890 goto err_out_release;
7891 }
7892
7893 bp->dev = dev;
7894 bp->pdev = pdev;
7895
7896 spin_lock_init(&bp->phy_lock);
7897 spin_lock_init(&bp->indirect_lock);
7898 #ifdef BCM_CNIC
7899 mutex_init(&bp->cnic_lock);
7900 #endif
7901 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7902
7903 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7904 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7905 dev->mem_end = dev->mem_start + mem_len;
7906 dev->irq = pdev->irq;
7907
7908 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7909
7910 if (!bp->regview) {
7911 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
7912 rc = -ENOMEM;
7913 goto err_out_release;
7914 }
7915
7916 /* Configure byte swap and enable write to the reg_window registers.
7917 * Rely on CPU to do target byte swapping on big endian systems
7918 * The chip's target access swapping will not swap all accesses
7919 */
7920 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7921 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7922 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7923
7924 bnx2_set_power_state(bp, PCI_D0);
7925
7926 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7927
7928 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7929 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7930 dev_err(&pdev->dev,
7931 "Cannot find PCIE capability, aborting\n");
7932 rc = -EIO;
7933 goto err_out_unmap;
7934 }
7935 bp->flags |= BNX2_FLAG_PCIE;
7936 if (CHIP_REV(bp) == CHIP_REV_Ax)
7937 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7938 } else {
7939 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7940 if (bp->pcix_cap == 0) {
7941 dev_err(&pdev->dev,
7942 "Cannot find PCIX capability, aborting\n");
7943 rc = -EIO;
7944 goto err_out_unmap;
7945 }
7946 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7947 }
7948
7949 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7950 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7951 bp->flags |= BNX2_FLAG_MSIX_CAP;
7952 }
7953
7954 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7955 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7956 bp->flags |= BNX2_FLAG_MSI_CAP;
7957 }
7958
7959 /* 5708 cannot support DMA addresses > 40-bit. */
7960 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7961 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7962 else
7963 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7964
7965 /* Configure DMA attributes. */
7966 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7967 dev->features |= NETIF_F_HIGHDMA;
7968 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7969 if (rc) {
7970 dev_err(&pdev->dev,
7971 "pci_set_consistent_dma_mask failed, aborting\n");
7972 goto err_out_unmap;
7973 }
7974 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7975 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7976 goto err_out_unmap;
7977 }
7978
7979 if (!(bp->flags & BNX2_FLAG_PCIE))
7980 bnx2_get_pci_speed(bp);
7981
7982 /* 5706A0 may falsely detect SERR and PERR. */
7983 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7984 reg = REG_RD(bp, PCI_COMMAND);
7985 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7986 REG_WR(bp, PCI_COMMAND, reg);
7987 }
7988 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7989 !(bp->flags & BNX2_FLAG_PCIX)) {
7990
7991 dev_err(&pdev->dev,
7992 "5706 A1 can only be used in a PCIX bus, aborting\n");
7993 goto err_out_unmap;
7994 }
7995
7996 bnx2_init_nvram(bp);
7997
7998 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7999
8000 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
8001 BNX2_SHM_HDR_SIGNATURE_SIG) {
8002 u32 off = PCI_FUNC(pdev->devfn) << 2;
8003
8004 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8005 } else
8006 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8007
8008 /* Get the permanent MAC address. First we need to make sure the
8009 * firmware is actually running.
8010 */
8011 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8012
8013 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8014 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
8015 dev_err(&pdev->dev, "Firmware not running, aborting\n");
8016 rc = -ENODEV;
8017 goto err_out_unmap;
8018 }
8019
8020 bnx2_read_vpd_fw_ver(bp);
8021
8022 j = strlen(bp->fw_version);
8023 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8024 for (i = 0; i < 3 && j < 24; i++) {
8025 u8 num, k, skip0;
8026
8027 if (i == 0) {
8028 bp->fw_version[j++] = 'b';
8029 bp->fw_version[j++] = 'c';
8030 bp->fw_version[j++] = ' ';
8031 }
8032 num = (u8) (reg >> (24 - (i * 8)));
8033 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8034 if (num >= k || !skip0 || k == 1) {
8035 bp->fw_version[j++] = (num / k) + '0';
8036 skip0 = 0;
8037 }
8038 }
8039 if (i != 2)
8040 bp->fw_version[j++] = '.';
8041 }
8042 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8043 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8044 bp->wol = 1;
8045
8046 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8047 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8048
8049 for (i = 0; i < 30; i++) {
8050 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8051 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8052 break;
8053 msleep(10);
8054 }
8055 }
8056 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8057 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8058 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8059 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8060 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8061
8062 if (j < 32)
8063 bp->fw_version[j++] = ' ';
8064 for (i = 0; i < 3 && j < 28; i++) {
8065 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8066 reg = swab32(reg);
8067 memcpy(&bp->fw_version[j], &reg, 4);
8068 j += 4;
8069 }
8070 }
8071
8072 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8073 bp->mac_addr[0] = (u8) (reg >> 8);
8074 bp->mac_addr[1] = (u8) reg;
8075
8076 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8077 bp->mac_addr[2] = (u8) (reg >> 24);
8078 bp->mac_addr[3] = (u8) (reg >> 16);
8079 bp->mac_addr[4] = (u8) (reg >> 8);
8080 bp->mac_addr[5] = (u8) reg;
8081
8082 bp->tx_ring_size = MAX_TX_DESC_CNT;
8083 bnx2_set_rx_ring_size(bp, 255);
8084
8085 bp->rx_csum = 1;
8086
8087 bp->tx_quick_cons_trip_int = 2;
8088 bp->tx_quick_cons_trip = 20;
8089 bp->tx_ticks_int = 18;
8090 bp->tx_ticks = 80;
8091
8092 bp->rx_quick_cons_trip_int = 2;
8093 bp->rx_quick_cons_trip = 12;
8094 bp->rx_ticks_int = 18;
8095 bp->rx_ticks = 18;
8096
8097 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8098
8099 bp->current_interval = BNX2_TIMER_INTERVAL;
8100
8101 bp->phy_addr = 1;
8102
8103 /* Disable WOL support if we are running on a SERDES chip. */
8104 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8105 bnx2_get_5709_media(bp);
8106 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8107 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8108
8109 bp->phy_port = PORT_TP;
8110 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8111 bp->phy_port = PORT_FIBRE;
8112 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8113 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8114 bp->flags |= BNX2_FLAG_NO_WOL;
8115 bp->wol = 0;
8116 }
8117 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8118 /* Don't do parallel detect on this board because of
8119 * some board problems. The link will not go down
8120 * if we do parallel detect.
8121 */
8122 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8123 pdev->subsystem_device == 0x310c)
8124 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8125 } else {
8126 bp->phy_addr = 2;
8127 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8128 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8129 }
8130 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8131 CHIP_NUM(bp) == CHIP_NUM_5708)
8132 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8133 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8134 (CHIP_REV(bp) == CHIP_REV_Ax ||
8135 CHIP_REV(bp) == CHIP_REV_Bx))
8136 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8137
8138 bnx2_init_fw_cap(bp);
8139
8140 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8141 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8142 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8143 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8144 bp->flags |= BNX2_FLAG_NO_WOL;
8145 bp->wol = 0;
8146 }
8147
8148 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8149 bp->tx_quick_cons_trip_int =
8150 bp->tx_quick_cons_trip;
8151 bp->tx_ticks_int = bp->tx_ticks;
8152 bp->rx_quick_cons_trip_int =
8153 bp->rx_quick_cons_trip;
8154 bp->rx_ticks_int = bp->rx_ticks;
8155 bp->comp_prod_trip_int = bp->comp_prod_trip;
8156 bp->com_ticks_int = bp->com_ticks;
8157 bp->cmd_ticks_int = bp->cmd_ticks;
8158 }
8159
8160 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8161 *
8162 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8163 * with byte enables disabled on the unused 32-bit word. This is legal
8164 * but causes problems on the AMD 8132 which will eventually stop
8165 * responding after a while.
8166 *
8167 * AMD believes this incompatibility is unique to the 5706, and
8168 * prefers to locally disable MSI rather than globally disabling it.
8169 */
8170 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8171 struct pci_dev *amd_8132 = NULL;
8172
8173 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8174 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8175 amd_8132))) {
8176
8177 if (amd_8132->revision >= 0x10 &&
8178 amd_8132->revision <= 0x13) {
8179 disable_msi = 1;
8180 pci_dev_put(amd_8132);
8181 break;
8182 }
8183 }
8184 }
8185
8186 bnx2_set_default_link(bp);
8187 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8188
8189 init_timer(&bp->timer);
8190 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8191 bp->timer.data = (unsigned long) bp;
8192 bp->timer.function = bnx2_timer;
8193
8194 return 0;
8195
8196 err_out_unmap:
8197 if (bp->regview) {
8198 iounmap(bp->regview);
8199 bp->regview = NULL;
8200 }
8201
8202 err_out_release:
8203 pci_release_regions(pdev);
8204
8205 err_out_disable:
8206 pci_disable_device(pdev);
8207 pci_set_drvdata(pdev, NULL);
8208
8209 err_out:
8210 return rc;
8211 }
8212
8213 static char * __devinit
8214 bnx2_bus_string(struct bnx2 *bp, char *str)
8215 {
8216 char *s = str;
8217
8218 if (bp->flags & BNX2_FLAG_PCIE) {
8219 s += sprintf(s, "PCI Express");
8220 } else {
8221 s += sprintf(s, "PCI");
8222 if (bp->flags & BNX2_FLAG_PCIX)
8223 s += sprintf(s, "-X");
8224 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8225 s += sprintf(s, " 32-bit");
8226 else
8227 s += sprintf(s, " 64-bit");
8228 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8229 }
8230 return str;
8231 }
8232
8233 static void
8234 bnx2_del_napi(struct bnx2 *bp)
8235 {
8236 int i;
8237
8238 for (i = 0; i < bp->irq_nvecs; i++)
8239 netif_napi_del(&bp->bnx2_napi[i].napi);
8240 }
8241
8242 static void
8243 bnx2_init_napi(struct bnx2 *bp)
8244 {
8245 int i;
8246
8247 for (i = 0; i < bp->irq_nvecs; i++) {
8248 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8249 int (*poll)(struct napi_struct *, int);
8250
8251 if (i == 0)
8252 poll = bnx2_poll;
8253 else
8254 poll = bnx2_poll_msix;
8255
8256 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8257 bnapi->bp = bp;
8258 }
8259 }
8260
8261 static const struct net_device_ops bnx2_netdev_ops = {
8262 .ndo_open = bnx2_open,
8263 .ndo_start_xmit = bnx2_start_xmit,
8264 .ndo_stop = bnx2_close,
8265 .ndo_get_stats = bnx2_get_stats,
8266 .ndo_set_rx_mode = bnx2_set_rx_mode,
8267 .ndo_do_ioctl = bnx2_ioctl,
8268 .ndo_validate_addr = eth_validate_addr,
8269 .ndo_set_mac_address = bnx2_change_mac_addr,
8270 .ndo_change_mtu = bnx2_change_mtu,
8271 .ndo_tx_timeout = bnx2_tx_timeout,
8272 #ifdef BCM_VLAN
8273 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8274 #endif
8275 #ifdef CONFIG_NET_POLL_CONTROLLER
8276 .ndo_poll_controller = poll_bnx2,
8277 #endif
8278 };
8279
8280 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8281 {
8282 #ifdef BCM_VLAN
8283 dev->vlan_features |= flags;
8284 #endif
8285 }
8286
8287 static int __devinit
8288 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8289 {
8290 static int version_printed = 0;
8291 struct net_device *dev = NULL;
8292 struct bnx2 *bp;
8293 int rc;
8294 char str[40];
8295
8296 if (version_printed++ == 0)
8297 pr_info("%s", version);
8298
8299 /* dev zeroed in init_etherdev */
8300 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8301
8302 if (!dev)
8303 return -ENOMEM;
8304
8305 rc = bnx2_init_board(pdev, dev);
8306 if (rc < 0) {
8307 free_netdev(dev);
8308 return rc;
8309 }
8310
8311 dev->netdev_ops = &bnx2_netdev_ops;
8312 dev->watchdog_timeo = TX_TIMEOUT;
8313 dev->ethtool_ops = &bnx2_ethtool_ops;
8314
8315 bp = netdev_priv(dev);
8316
8317 pci_set_drvdata(pdev, dev);
8318
8319 rc = bnx2_request_firmware(bp);
8320 if (rc)
8321 goto error;
8322
8323 memcpy(dev->dev_addr, bp->mac_addr, 6);
8324 memcpy(dev->perm_addr, bp->mac_addr, 6);
8325
8326 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
8327 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8328 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8329 dev->features |= NETIF_F_IPV6_CSUM;
8330 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8331 }
8332 #ifdef BCM_VLAN
8333 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8334 #endif
8335 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8336 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8337 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8338 dev->features |= NETIF_F_TSO6;
8339 vlan_features_add(dev, NETIF_F_TSO6);
8340 }
8341 if ((rc = register_netdev(dev))) {
8342 dev_err(&pdev->dev, "Cannot register net device\n");
8343 goto error;
8344 }
8345
8346 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8347 board_info[ent->driver_data].name,
8348 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8349 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8350 bnx2_bus_string(bp, str),
8351 dev->base_addr,
8352 bp->pdev->irq, dev->dev_addr);
8353
8354 return 0;
8355
8356 error:
8357 if (bp->mips_firmware)
8358 release_firmware(bp->mips_firmware);
8359 if (bp->rv2p_firmware)
8360 release_firmware(bp->rv2p_firmware);
8361
8362 if (bp->regview)
8363 iounmap(bp->regview);
8364 pci_release_regions(pdev);
8365 pci_disable_device(pdev);
8366 pci_set_drvdata(pdev, NULL);
8367 free_netdev(dev);
8368 return rc;
8369 }
8370
8371 static void __devexit
8372 bnx2_remove_one(struct pci_dev *pdev)
8373 {
8374 struct net_device *dev = pci_get_drvdata(pdev);
8375 struct bnx2 *bp = netdev_priv(dev);
8376
8377 flush_scheduled_work();
8378
8379 unregister_netdev(dev);
8380
8381 if (bp->mips_firmware)
8382 release_firmware(bp->mips_firmware);
8383 if (bp->rv2p_firmware)
8384 release_firmware(bp->rv2p_firmware);
8385
8386 if (bp->regview)
8387 iounmap(bp->regview);
8388
8389 kfree(bp->temp_stats_blk);
8390
8391 free_netdev(dev);
8392 pci_release_regions(pdev);
8393 pci_disable_device(pdev);
8394 pci_set_drvdata(pdev, NULL);
8395 }
8396
8397 static int
8398 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8399 {
8400 struct net_device *dev = pci_get_drvdata(pdev);
8401 struct bnx2 *bp = netdev_priv(dev);
8402
8403 /* PCI register 4 needs to be saved whether netif_running() or not.
8404 * MSI address and data need to be saved if using MSI and
8405 * netif_running().
8406 */
8407 pci_save_state(pdev);
8408 if (!netif_running(dev))
8409 return 0;
8410
8411 flush_scheduled_work();
8412 bnx2_netif_stop(bp, true);
8413 netif_device_detach(dev);
8414 del_timer_sync(&bp->timer);
8415 bnx2_shutdown_chip(bp);
8416 bnx2_free_skbs(bp);
8417 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8418 return 0;
8419 }
8420
8421 static int
8422 bnx2_resume(struct pci_dev *pdev)
8423 {
8424 struct net_device *dev = pci_get_drvdata(pdev);
8425 struct bnx2 *bp = netdev_priv(dev);
8426
8427 pci_restore_state(pdev);
8428 if (!netif_running(dev))
8429 return 0;
8430
8431 bnx2_set_power_state(bp, PCI_D0);
8432 netif_device_attach(dev);
8433 bnx2_init_nic(bp, 1);
8434 bnx2_netif_start(bp, true);
8435 return 0;
8436 }
8437
8438 /**
8439 * bnx2_io_error_detected - called when PCI error is detected
8440 * @pdev: Pointer to PCI device
8441 * @state: The current pci connection state
8442 *
8443 * This function is called after a PCI bus error affecting
8444 * this device has been detected.
8445 */
8446 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8447 pci_channel_state_t state)
8448 {
8449 struct net_device *dev = pci_get_drvdata(pdev);
8450 struct bnx2 *bp = netdev_priv(dev);
8451
8452 rtnl_lock();
8453 netif_device_detach(dev);
8454
8455 if (state == pci_channel_io_perm_failure) {
8456 rtnl_unlock();
8457 return PCI_ERS_RESULT_DISCONNECT;
8458 }
8459
8460 if (netif_running(dev)) {
8461 bnx2_netif_stop(bp, true);
8462 del_timer_sync(&bp->timer);
8463 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8464 }
8465
8466 pci_disable_device(pdev);
8467 rtnl_unlock();
8468
8469 /* Request a slot slot reset. */
8470 return PCI_ERS_RESULT_NEED_RESET;
8471 }
8472
8473 /**
8474 * bnx2_io_slot_reset - called after the pci bus has been reset.
8475 * @pdev: Pointer to PCI device
8476 *
8477 * Restart the card from scratch, as if from a cold-boot.
8478 */
8479 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8480 {
8481 struct net_device *dev = pci_get_drvdata(pdev);
8482 struct bnx2 *bp = netdev_priv(dev);
8483
8484 rtnl_lock();
8485 if (pci_enable_device(pdev)) {
8486 dev_err(&pdev->dev,
8487 "Cannot re-enable PCI device after reset\n");
8488 rtnl_unlock();
8489 return PCI_ERS_RESULT_DISCONNECT;
8490 }
8491 pci_set_master(pdev);
8492 pci_restore_state(pdev);
8493 pci_save_state(pdev);
8494
8495 if (netif_running(dev)) {
8496 bnx2_set_power_state(bp, PCI_D0);
8497 bnx2_init_nic(bp, 1);
8498 }
8499
8500 rtnl_unlock();
8501 return PCI_ERS_RESULT_RECOVERED;
8502 }
8503
8504 /**
8505 * bnx2_io_resume - called when traffic can start flowing again.
8506 * @pdev: Pointer to PCI device
8507 *
8508 * This callback is called when the error recovery driver tells us that
8509 * its OK to resume normal operation.
8510 */
8511 static void bnx2_io_resume(struct pci_dev *pdev)
8512 {
8513 struct net_device *dev = pci_get_drvdata(pdev);
8514 struct bnx2 *bp = netdev_priv(dev);
8515
8516 rtnl_lock();
8517 if (netif_running(dev))
8518 bnx2_netif_start(bp, true);
8519
8520 netif_device_attach(dev);
8521 rtnl_unlock();
8522 }
8523
8524 static struct pci_error_handlers bnx2_err_handler = {
8525 .error_detected = bnx2_io_error_detected,
8526 .slot_reset = bnx2_io_slot_reset,
8527 .resume = bnx2_io_resume,
8528 };
8529
8530 static struct pci_driver bnx2_pci_driver = {
8531 .name = DRV_MODULE_NAME,
8532 .id_table = bnx2_pci_tbl,
8533 .probe = bnx2_init_one,
8534 .remove = __devexit_p(bnx2_remove_one),
8535 .suspend = bnx2_suspend,
8536 .resume = bnx2_resume,
8537 .err_handler = &bnx2_err_handler,
8538 };
8539
8540 static int __init bnx2_init(void)
8541 {
8542 return pci_register_driver(&bnx2_pci_driver);
8543 }
8544
8545 static void __exit bnx2_cleanup(void)
8546 {
8547 pci_unregister_driver(&bnx2_pci_driver);
8548 }
8549
8550 module_init(bnx2_init);
8551 module_exit(bnx2_cleanup);
8552
8553
8554
Linux with added FPC-III support