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Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs
[linux/fpc-iii.git] / drivers / net / jme.c
blob99f24f5cac53f6c6a70e25681253593b3b485a6e
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <linux/slab.h>
41 #include <net/ip6_checksum.h>
42 #include "jme.h"
43
44 static int force_pseudohp = -1;
45 static int no_pseudohp = -1;
46 static int no_extplug = -1;
47 module_param(force_pseudohp, int, 0);
48 MODULE_PARM_DESC(force_pseudohp,
49 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
50 module_param(no_pseudohp, int, 0);
51 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
52 module_param(no_extplug, int, 0);
53 MODULE_PARM_DESC(no_extplug,
54 "Do not use external plug signal for pseudo hot-plug.");
55
56 static int
57 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 {
59 struct jme_adapter *jme = netdev_priv(netdev);
60 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
61
62 read_again:
63 jwrite32(jme, JME_SMI, SMI_OP_REQ |
64 smi_phy_addr(phy) |
65 smi_reg_addr(reg));
66
67 wmb();
68 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69 udelay(20);
70 val = jread32(jme, JME_SMI);
71 if ((val & SMI_OP_REQ) == 0)
72 break;
73 }
74
75 if (i == 0) {
76 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
77 return 0;
78 }
79
80 if (again--)
81 goto read_again;
82
83 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
84 }
85
86 static void
87 jme_mdio_write(struct net_device *netdev,
88 int phy, int reg, int val)
89 {
90 struct jme_adapter *jme = netdev_priv(netdev);
91 int i;
92
93 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
94 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
95 smi_phy_addr(phy) | smi_reg_addr(reg));
96
97 wmb();
98 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 udelay(20);
100 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
101 break;
102 }
103
104 if (i == 0)
105 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
106 }
107
108 static inline void
109 jme_reset_phy_processor(struct jme_adapter *jme)
110 {
111 u32 val;
112
113 jme_mdio_write(jme->dev,
114 jme->mii_if.phy_id,
115 MII_ADVERTISE, ADVERTISE_ALL |
116 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
117
118 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_CTRL1000,
122 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
123
124 val = jme_mdio_read(jme->dev,
125 jme->mii_if.phy_id,
126 MII_BMCR);
127
128 jme_mdio_write(jme->dev,
129 jme->mii_if.phy_id,
130 MII_BMCR, val | BMCR_RESET);
131 }
132
133 static void
134 jme_setup_wakeup_frame(struct jme_adapter *jme,
135 u32 *mask, u32 crc, int fnr)
136 {
137 int i;
138
139 /*
140 * Setup CRC pattern
141 */
142 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
143 wmb();
144 jwrite32(jme, JME_WFODP, crc);
145 wmb();
146
147 /*
148 * Setup Mask
149 */
150 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
151 jwrite32(jme, JME_WFOI,
152 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
153 (fnr & WFOI_FRAME_SEL));
154 wmb();
155 jwrite32(jme, JME_WFODP, mask[i]);
156 wmb();
157 }
158 }
159
160 static inline void
161 jme_reset_mac_processor(struct jme_adapter *jme)
162 {
163 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
164 u32 crc = 0xCDCDCDCD;
165 u32 gpreg0;
166 int i;
167
168 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
169 udelay(2);
170 jwrite32(jme, JME_GHC, jme->reg_ghc);
171
172 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
173 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
174 jwrite32(jme, JME_RXQDC, 0x00000000);
175 jwrite32(jme, JME_RXNDA, 0x00000000);
176 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
177 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
178 jwrite32(jme, JME_TXQDC, 0x00000000);
179 jwrite32(jme, JME_TXNDA, 0x00000000);
180
181 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
182 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
183 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
184 jme_setup_wakeup_frame(jme, mask, crc, i);
185 if (jme->fpgaver)
186 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
187 else
188 gpreg0 = GPREG0_DEFAULT;
189 jwrite32(jme, JME_GPREG0, gpreg0);
190 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
191 }
192
193 static inline void
194 jme_reset_ghc_speed(struct jme_adapter *jme)
195 {
196 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
197 jwrite32(jme, JME_GHC, jme->reg_ghc);
198 }
199
200 static inline void
201 jme_clear_pm(struct jme_adapter *jme)
202 {
203 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
204 pci_set_power_state(jme->pdev, PCI_D0);
205 pci_enable_wake(jme->pdev, PCI_D0, false);
206 }
207
208 static int
209 jme_reload_eeprom(struct jme_adapter *jme)
210 {
211 u32 val;
212 int i;
213
214 val = jread32(jme, JME_SMBCSR);
215
216 if (val & SMBCSR_EEPROMD) {
217 val |= SMBCSR_CNACK;
218 jwrite32(jme, JME_SMBCSR, val);
219 val |= SMBCSR_RELOAD;
220 jwrite32(jme, JME_SMBCSR, val);
221 mdelay(12);
222
223 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
224 mdelay(1);
225 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
226 break;
227 }
228
229 if (i == 0) {
230 jeprintk(jme->pdev, "eeprom reload timeout\n");
231 return -EIO;
232 }
233 }
234
235 return 0;
236 }
237
238 static void
239 jme_load_macaddr(struct net_device *netdev)
240 {
241 struct jme_adapter *jme = netdev_priv(netdev);
242 unsigned char macaddr[6];
243 u32 val;
244
245 spin_lock_bh(&jme->macaddr_lock);
246 val = jread32(jme, JME_RXUMA_LO);
247 macaddr[0] = (val >> 0) & 0xFF;
248 macaddr[1] = (val >> 8) & 0xFF;
249 macaddr[2] = (val >> 16) & 0xFF;
250 macaddr[3] = (val >> 24) & 0xFF;
251 val = jread32(jme, JME_RXUMA_HI);
252 macaddr[4] = (val >> 0) & 0xFF;
253 macaddr[5] = (val >> 8) & 0xFF;
254 memcpy(netdev->dev_addr, macaddr, 6);
255 spin_unlock_bh(&jme->macaddr_lock);
256 }
257
258 static inline void
259 jme_set_rx_pcc(struct jme_adapter *jme, int p)
260 {
261 switch (p) {
262 case PCC_OFF:
263 jwrite32(jme, JME_PCCRX0,
264 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
265 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
266 break;
267 case PCC_P1:
268 jwrite32(jme, JME_PCCRX0,
269 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
270 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 break;
272 case PCC_P2:
273 jwrite32(jme, JME_PCCRX0,
274 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
275 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 break;
277 case PCC_P3:
278 jwrite32(jme, JME_PCCRX0,
279 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
280 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 break;
282 default:
283 break;
284 }
285 wmb();
286
287 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
288 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
289 }
290
291 static void
292 jme_start_irq(struct jme_adapter *jme)
293 {
294 register struct dynpcc_info *dpi = &(jme->dpi);
295
296 jme_set_rx_pcc(jme, PCC_P1);
297 dpi->cur = PCC_P1;
298 dpi->attempt = PCC_P1;
299 dpi->cnt = 0;
300
301 jwrite32(jme, JME_PCCTX,
302 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
303 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
304 PCCTXQ0_EN
305 );
306
307 /*
308 * Enable Interrupts
309 */
310 jwrite32(jme, JME_IENS, INTR_ENABLE);
311 }
312
313 static inline void
314 jme_stop_irq(struct jme_adapter *jme)
315 {
316 /*
317 * Disable Interrupts
318 */
319 jwrite32f(jme, JME_IENC, INTR_ENABLE);
320 }
321
322 static u32
323 jme_linkstat_from_phy(struct jme_adapter *jme)
324 {
325 u32 phylink, bmsr;
326
327 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
328 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
329 if (bmsr & BMSR_ANCOMP)
330 phylink |= PHY_LINK_AUTONEG_COMPLETE;
331
332 return phylink;
333 }
334
335 static inline void
336 jme_set_phyfifoa(struct jme_adapter *jme)
337 {
338 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
339 }
340
341 static inline void
342 jme_set_phyfifob(struct jme_adapter *jme)
343 {
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
345 }
346
347 static int
348 jme_check_link(struct net_device *netdev, int testonly)
349 {
350 struct jme_adapter *jme = netdev_priv(netdev);
351 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
352 char linkmsg[64];
353 int rc = 0;
354
355 linkmsg[0] = '\0';
356
357 if (jme->fpgaver)
358 phylink = jme_linkstat_from_phy(jme);
359 else
360 phylink = jread32(jme, JME_PHY_LINK);
361
362 if (phylink & PHY_LINK_UP) {
363 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
364 /*
365 * If we did not enable AN
366 * Speed/Duplex Info should be obtained from SMI
367 */
368 phylink = PHY_LINK_UP;
369
370 bmcr = jme_mdio_read(jme->dev,
371 jme->mii_if.phy_id,
372 MII_BMCR);
373
374 phylink |= ((bmcr & BMCR_SPEED1000) &&
375 (bmcr & BMCR_SPEED100) == 0) ?
376 PHY_LINK_SPEED_1000M :
377 (bmcr & BMCR_SPEED100) ?
378 PHY_LINK_SPEED_100M :
379 PHY_LINK_SPEED_10M;
380
381 phylink |= (bmcr & BMCR_FULLDPLX) ?
382 PHY_LINK_DUPLEX : 0;
383
384 strcat(linkmsg, "Forced: ");
385 } else {
386 /*
387 * Keep polling for speed/duplex resolve complete
388 */
389 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
390 --cnt) {
391
392 udelay(1);
393
394 if (jme->fpgaver)
395 phylink = jme_linkstat_from_phy(jme);
396 else
397 phylink = jread32(jme, JME_PHY_LINK);
398 }
399 if (!cnt)
400 jeprintk(jme->pdev,
401 "Waiting speed resolve timeout.\n");
402
403 strcat(linkmsg, "ANed: ");
404 }
405
406 if (jme->phylink == phylink) {
407 rc = 1;
408 goto out;
409 }
410 if (testonly)
411 goto out;
412
413 jme->phylink = phylink;
414
415 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
416 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
417 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
418 switch (phylink & PHY_LINK_SPEED_MASK) {
419 case PHY_LINK_SPEED_10M:
420 ghc |= GHC_SPEED_10M |
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
422 strcat(linkmsg, "10 Mbps, ");
423 break;
424 case PHY_LINK_SPEED_100M:
425 ghc |= GHC_SPEED_100M |
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
427 strcat(linkmsg, "100 Mbps, ");
428 break;
429 case PHY_LINK_SPEED_1000M:
430 ghc |= GHC_SPEED_1000M |
431 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
432 strcat(linkmsg, "1000 Mbps, ");
433 break;
434 default:
435 break;
436 }
437
438 if (phylink & PHY_LINK_DUPLEX) {
439 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
440 ghc |= GHC_DPX;
441 } else {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
443 TXMCS_BACKOFF |
444 TXMCS_CARRIERSENSE |
445 TXMCS_COLLISION);
446 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
447 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
448 TXTRHD_TXREN |
449 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
450 }
451
452 gpreg1 = GPREG1_DEFAULT;
453 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
454 if (!(phylink & PHY_LINK_DUPLEX))
455 gpreg1 |= GPREG1_HALFMODEPATCH;
456 switch (phylink & PHY_LINK_SPEED_MASK) {
457 case PHY_LINK_SPEED_10M:
458 jme_set_phyfifoa(jme);
459 gpreg1 |= GPREG1_RSSPATCH;
460 break;
461 case PHY_LINK_SPEED_100M:
462 jme_set_phyfifob(jme);
463 gpreg1 |= GPREG1_RSSPATCH;
464 break;
465 case PHY_LINK_SPEED_1000M:
466 jme_set_phyfifoa(jme);
467 break;
468 default:
469 break;
470 }
471 }
472
473 jwrite32(jme, JME_GPREG1, gpreg1);
474 jwrite32(jme, JME_GHC, ghc);
475 jme->reg_ghc = ghc;
476
477 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
478 "Full-Duplex, " :
479 "Half-Duplex, ");
480 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
481 "MDI-X" :
482 "MDI");
483 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
484 netif_carrier_on(netdev);
485 } else {
486 if (testonly)
487 goto out;
488
489 netif_info(jme, link, jme->dev, "Link is down.\n");
490 jme->phylink = 0;
491 netif_carrier_off(netdev);
492 }
493
494 out:
495 return rc;
496 }
497
498 static int
499 jme_setup_tx_resources(struct jme_adapter *jme)
500 {
501 struct jme_ring *txring = &(jme->txring[0]);
502
503 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
504 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
505 &(txring->dmaalloc),
506 GFP_ATOMIC);
507
508 if (!txring->alloc)
509 goto err_set_null;
510
511 /*
512 * 16 Bytes align
513 */
514 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
515 RING_DESC_ALIGN);
516 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
517 txring->next_to_use = 0;
518 atomic_set(&txring->next_to_clean, 0);
519 atomic_set(&txring->nr_free, jme->tx_ring_size);
520
521 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
522 jme->tx_ring_size, GFP_ATOMIC);
523 if (unlikely(!(txring->bufinf)))
524 goto err_free_txring;
525
526 /*
527 * Initialize Transmit Descriptors
528 */
529 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
530 memset(txring->bufinf, 0,
531 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
532
533 return 0;
534
535 err_free_txring:
536 dma_free_coherent(&(jme->pdev->dev),
537 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
538 txring->alloc,
539 txring->dmaalloc);
540
541 err_set_null:
542 txring->desc = NULL;
543 txring->dmaalloc = 0;
544 txring->dma = 0;
545 txring->bufinf = NULL;
546
547 return -ENOMEM;
548 }
549
550 static void
551 jme_free_tx_resources(struct jme_adapter *jme)
552 {
553 int i;
554 struct jme_ring *txring = &(jme->txring[0]);
555 struct jme_buffer_info *txbi;
556
557 if (txring->alloc) {
558 if (txring->bufinf) {
559 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
560 txbi = txring->bufinf + i;
561 if (txbi->skb) {
562 dev_kfree_skb(txbi->skb);
563 txbi->skb = NULL;
564 }
565 txbi->mapping = 0;
566 txbi->len = 0;
567 txbi->nr_desc = 0;
568 txbi->start_xmit = 0;
569 }
570 kfree(txring->bufinf);
571 }
572
573 dma_free_coherent(&(jme->pdev->dev),
574 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
575 txring->alloc,
576 txring->dmaalloc);
577
578 txring->alloc = NULL;
579 txring->desc = NULL;
580 txring->dmaalloc = 0;
581 txring->dma = 0;
582 txring->bufinf = NULL;
583 }
584 txring->next_to_use = 0;
585 atomic_set(&txring->next_to_clean, 0);
586 atomic_set(&txring->nr_free, 0);
587 }
588
589 static inline void
590 jme_enable_tx_engine(struct jme_adapter *jme)
591 {
592 /*
593 * Select Queue 0
594 */
595 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
596 wmb();
597
598 /*
599 * Setup TX Queue 0 DMA Bass Address
600 */
601 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
602 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
603 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
604
605 /*
606 * Setup TX Descptor Count
607 */
608 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
609
610 /*
611 * Enable TX Engine
612 */
613 wmb();
614 jwrite32(jme, JME_TXCS, jme->reg_txcs |
615 TXCS_SELECT_QUEUE0 |
616 TXCS_ENABLE);
617
618 }
619
620 static inline void
621 jme_restart_tx_engine(struct jme_adapter *jme)
622 {
623 /*
624 * Restart TX Engine
625 */
626 jwrite32(jme, JME_TXCS, jme->reg_txcs |
627 TXCS_SELECT_QUEUE0 |
628 TXCS_ENABLE);
629 }
630
631 static inline void
632 jme_disable_tx_engine(struct jme_adapter *jme)
633 {
634 int i;
635 u32 val;
636
637 /*
638 * Disable TX Engine
639 */
640 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
641 wmb();
642
643 val = jread32(jme, JME_TXCS);
644 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
645 mdelay(1);
646 val = jread32(jme, JME_TXCS);
647 rmb();
648 }
649
650 if (!i)
651 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
652 }
653
654 static void
655 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
656 {
657 struct jme_ring *rxring = &(jme->rxring[0]);
658 register struct rxdesc *rxdesc = rxring->desc;
659 struct jme_buffer_info *rxbi = rxring->bufinf;
660 rxdesc += i;
661 rxbi += i;
662
663 rxdesc->dw[0] = 0;
664 rxdesc->dw[1] = 0;
665 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
666 rxdesc->desc1.bufaddrl = cpu_to_le32(
667 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
668 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
669 if (jme->dev->features & NETIF_F_HIGHDMA)
670 rxdesc->desc1.flags = RXFLAG_64BIT;
671 wmb();
672 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
673 }
674
675 static int
676 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
677 {
678 struct jme_ring *rxring = &(jme->rxring[0]);
679 struct jme_buffer_info *rxbi = rxring->bufinf + i;
680 struct sk_buff *skb;
681
682 skb = netdev_alloc_skb(jme->dev,
683 jme->dev->mtu + RX_EXTRA_LEN);
684 if (unlikely(!skb))
685 return -ENOMEM;
686
687 rxbi->skb = skb;
688 rxbi->len = skb_tailroom(skb);
689 rxbi->mapping = pci_map_page(jme->pdev,
690 virt_to_page(skb->data),
691 offset_in_page(skb->data),
692 rxbi->len,
693 PCI_DMA_FROMDEVICE);
694
695 return 0;
696 }
697
698 static void
699 jme_free_rx_buf(struct jme_adapter *jme, int i)
700 {
701 struct jme_ring *rxring = &(jme->rxring[0]);
702 struct jme_buffer_info *rxbi = rxring->bufinf;
703 rxbi += i;
704
705 if (rxbi->skb) {
706 pci_unmap_page(jme->pdev,
707 rxbi->mapping,
708 rxbi->len,
709 PCI_DMA_FROMDEVICE);
710 dev_kfree_skb(rxbi->skb);
711 rxbi->skb = NULL;
712 rxbi->mapping = 0;
713 rxbi->len = 0;
714 }
715 }
716
717 static void
718 jme_free_rx_resources(struct jme_adapter *jme)
719 {
720 int i;
721 struct jme_ring *rxring = &(jme->rxring[0]);
722
723 if (rxring->alloc) {
724 if (rxring->bufinf) {
725 for (i = 0 ; i < jme->rx_ring_size ; ++i)
726 jme_free_rx_buf(jme, i);
727 kfree(rxring->bufinf);
728 }
729
730 dma_free_coherent(&(jme->pdev->dev),
731 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
732 rxring->alloc,
733 rxring->dmaalloc);
734 rxring->alloc = NULL;
735 rxring->desc = NULL;
736 rxring->dmaalloc = 0;
737 rxring->dma = 0;
738 rxring->bufinf = NULL;
739 }
740 rxring->next_to_use = 0;
741 atomic_set(&rxring->next_to_clean, 0);
742 }
743
744 static int
745 jme_setup_rx_resources(struct jme_adapter *jme)
746 {
747 int i;
748 struct jme_ring *rxring = &(jme->rxring[0]);
749
750 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
751 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
752 &(rxring->dmaalloc),
753 GFP_ATOMIC);
754 if (!rxring->alloc)
755 goto err_set_null;
756
757 /*
758 * 16 Bytes align
759 */
760 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
761 RING_DESC_ALIGN);
762 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
763 rxring->next_to_use = 0;
764 atomic_set(&rxring->next_to_clean, 0);
765
766 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
767 jme->rx_ring_size, GFP_ATOMIC);
768 if (unlikely(!(rxring->bufinf)))
769 goto err_free_rxring;
770
771 /*
772 * Initiallize Receive Descriptors
773 */
774 memset(rxring->bufinf, 0,
775 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
776 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
777 if (unlikely(jme_make_new_rx_buf(jme, i))) {
778 jme_free_rx_resources(jme);
779 return -ENOMEM;
780 }
781
782 jme_set_clean_rxdesc(jme, i);
783 }
784
785 return 0;
786
787 err_free_rxring:
788 dma_free_coherent(&(jme->pdev->dev),
789 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
790 rxring->alloc,
791 rxring->dmaalloc);
792 err_set_null:
793 rxring->desc = NULL;
794 rxring->dmaalloc = 0;
795 rxring->dma = 0;
796 rxring->bufinf = NULL;
797
798 return -ENOMEM;
799 }
800
801 static inline void
802 jme_enable_rx_engine(struct jme_adapter *jme)
803 {
804 /*
805 * Select Queue 0
806 */
807 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
808 RXCS_QUEUESEL_Q0);
809 wmb();
810
811 /*
812 * Setup RX DMA Bass Address
813 */
814 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
815 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
816 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
817
818 /*
819 * Setup RX Descriptor Count
820 */
821 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
822
823 /*
824 * Setup Unicast Filter
825 */
826 jme_set_multi(jme->dev);
827
828 /*
829 * Enable RX Engine
830 */
831 wmb();
832 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
833 RXCS_QUEUESEL_Q0 |
834 RXCS_ENABLE |
835 RXCS_QST);
836 }
837
838 static inline void
839 jme_restart_rx_engine(struct jme_adapter *jme)
840 {
841 /*
842 * Start RX Engine
843 */
844 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
845 RXCS_QUEUESEL_Q0 |
846 RXCS_ENABLE |
847 RXCS_QST);
848 }
849
850 static inline void
851 jme_disable_rx_engine(struct jme_adapter *jme)
852 {
853 int i;
854 u32 val;
855
856 /*
857 * Disable RX Engine
858 */
859 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
860 wmb();
861
862 val = jread32(jme, JME_RXCS);
863 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
864 mdelay(1);
865 val = jread32(jme, JME_RXCS);
866 rmb();
867 }
868
869 if (!i)
870 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
871
872 }
873
874 static int
875 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
876 {
877 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
878 return false;
879
880 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
881 == RXWBFLAG_TCPON)) {
882 if (flags & RXWBFLAG_IPV4)
883 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
884 return false;
885 }
886
887 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
888 == RXWBFLAG_UDPON)) {
889 if (flags & RXWBFLAG_IPV4)
890 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
891 return false;
892 }
893
894 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
895 == RXWBFLAG_IPV4)) {
896 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
897 return false;
898 }
899
900 return true;
901 }
902
903 static void
904 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
905 {
906 struct jme_ring *rxring = &(jme->rxring[0]);
907 struct rxdesc *rxdesc = rxring->desc;
908 struct jme_buffer_info *rxbi = rxring->bufinf;
909 struct sk_buff *skb;
910 int framesize;
911
912 rxdesc += idx;
913 rxbi += idx;
914
915 skb = rxbi->skb;
916 pci_dma_sync_single_for_cpu(jme->pdev,
917 rxbi->mapping,
918 rxbi->len,
919 PCI_DMA_FROMDEVICE);
920
921 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
922 pci_dma_sync_single_for_device(jme->pdev,
923 rxbi->mapping,
924 rxbi->len,
925 PCI_DMA_FROMDEVICE);
926
927 ++(NET_STAT(jme).rx_dropped);
928 } else {
929 framesize = le16_to_cpu(rxdesc->descwb.framesize)
930 - RX_PREPAD_SIZE;
931
932 skb_reserve(skb, RX_PREPAD_SIZE);
933 skb_put(skb, framesize);
934 skb->protocol = eth_type_trans(skb, jme->dev);
935
936 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
937 skb->ip_summed = CHECKSUM_UNNECESSARY;
938 else
939 skb->ip_summed = CHECKSUM_NONE;
940
941 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
942 if (jme->vlgrp) {
943 jme->jme_vlan_rx(skb, jme->vlgrp,
944 le16_to_cpu(rxdesc->descwb.vlan));
945 NET_STAT(jme).rx_bytes += 4;
946 } else {
947 dev_kfree_skb(skb);
948 }
949 } else {
950 jme->jme_rx(skb);
951 }
952
953 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
954 cpu_to_le16(RXWBFLAG_DEST_MUL))
955 ++(NET_STAT(jme).multicast);
956
957 NET_STAT(jme).rx_bytes += framesize;
958 ++(NET_STAT(jme).rx_packets);
959 }
960
961 jme_set_clean_rxdesc(jme, idx);
962
963 }
964
965 static int
966 jme_process_receive(struct jme_adapter *jme, int limit)
967 {
968 struct jme_ring *rxring = &(jme->rxring[0]);
969 struct rxdesc *rxdesc = rxring->desc;
970 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
971
972 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
973 goto out_inc;
974
975 if (unlikely(atomic_read(&jme->link_changing) != 1))
976 goto out_inc;
977
978 if (unlikely(!netif_carrier_ok(jme->dev)))
979 goto out_inc;
980
981 i = atomic_read(&rxring->next_to_clean);
982 while (limit > 0) {
983 rxdesc = rxring->desc;
984 rxdesc += i;
985
986 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
987 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
988 goto out;
989 --limit;
990
991 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
992
993 if (unlikely(desccnt > 1 ||
994 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
995
996 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
997 ++(NET_STAT(jme).rx_crc_errors);
998 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
999 ++(NET_STAT(jme).rx_fifo_errors);
1000 else
1001 ++(NET_STAT(jme).rx_errors);
1002
1003 if (desccnt > 1)
1004 limit -= desccnt - 1;
1005
1006 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1007 jme_set_clean_rxdesc(jme, j);
1008 j = (j + 1) & (mask);
1009 }
1010
1011 } else {
1012 jme_alloc_and_feed_skb(jme, i);
1013 }
1014
1015 i = (i + desccnt) & (mask);
1016 }
1017
1018 out:
1019 atomic_set(&rxring->next_to_clean, i);
1020
1021 out_inc:
1022 atomic_inc(&jme->rx_cleaning);
1023
1024 return limit > 0 ? limit : 0;
1025
1026 }
1027
1028 static void
1029 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1030 {
1031 if (likely(atmp == dpi->cur)) {
1032 dpi->cnt = 0;
1033 return;
1034 }
1035
1036 if (dpi->attempt == atmp) {
1037 ++(dpi->cnt);
1038 } else {
1039 dpi->attempt = atmp;
1040 dpi->cnt = 0;
1041 }
1042
1043 }
1044
1045 static void
1046 jme_dynamic_pcc(struct jme_adapter *jme)
1047 {
1048 register struct dynpcc_info *dpi = &(jme->dpi);
1049
1050 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1051 jme_attempt_pcc(dpi, PCC_P3);
1052 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1053 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1054 jme_attempt_pcc(dpi, PCC_P2);
1055 else
1056 jme_attempt_pcc(dpi, PCC_P1);
1057
1058 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1059 if (dpi->attempt < dpi->cur)
1060 tasklet_schedule(&jme->rxclean_task);
1061 jme_set_rx_pcc(jme, dpi->attempt);
1062 dpi->cur = dpi->attempt;
1063 dpi->cnt = 0;
1064 }
1065 }
1066
1067 static void
1068 jme_start_pcc_timer(struct jme_adapter *jme)
1069 {
1070 struct dynpcc_info *dpi = &(jme->dpi);
1071 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1072 dpi->last_pkts = NET_STAT(jme).rx_packets;
1073 dpi->intr_cnt = 0;
1074 jwrite32(jme, JME_TMCSR,
1075 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1076 }
1077
1078 static inline void
1079 jme_stop_pcc_timer(struct jme_adapter *jme)
1080 {
1081 jwrite32(jme, JME_TMCSR, 0);
1082 }
1083
1084 static void
1085 jme_shutdown_nic(struct jme_adapter *jme)
1086 {
1087 u32 phylink;
1088
1089 phylink = jme_linkstat_from_phy(jme);
1090
1091 if (!(phylink & PHY_LINK_UP)) {
1092 /*
1093 * Disable all interrupt before issue timer
1094 */
1095 jme_stop_irq(jme);
1096 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1097 }
1098 }
1099
1100 static void
1101 jme_pcc_tasklet(unsigned long arg)
1102 {
1103 struct jme_adapter *jme = (struct jme_adapter *)arg;
1104 struct net_device *netdev = jme->dev;
1105
1106 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1107 jme_shutdown_nic(jme);
1108 return;
1109 }
1110
1111 if (unlikely(!netif_carrier_ok(netdev) ||
1112 (atomic_read(&jme->link_changing) != 1)
1113 )) {
1114 jme_stop_pcc_timer(jme);
1115 return;
1116 }
1117
1118 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1119 jme_dynamic_pcc(jme);
1120
1121 jme_start_pcc_timer(jme);
1122 }
1123
1124 static inline void
1125 jme_polling_mode(struct jme_adapter *jme)
1126 {
1127 jme_set_rx_pcc(jme, PCC_OFF);
1128 }
1129
1130 static inline void
1131 jme_interrupt_mode(struct jme_adapter *jme)
1132 {
1133 jme_set_rx_pcc(jme, PCC_P1);
1134 }
1135
1136 static inline int
1137 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1138 {
1139 u32 apmc;
1140 apmc = jread32(jme, JME_APMC);
1141 return apmc & JME_APMC_PSEUDO_HP_EN;
1142 }
1143
1144 static void
1145 jme_start_shutdown_timer(struct jme_adapter *jme)
1146 {
1147 u32 apmc;
1148
1149 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1150 apmc &= ~JME_APMC_EPIEN_CTRL;
1151 if (!no_extplug) {
1152 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1153 wmb();
1154 }
1155 jwrite32f(jme, JME_APMC, apmc);
1156
1157 jwrite32f(jme, JME_TIMER2, 0);
1158 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1159 jwrite32(jme, JME_TMCSR,
1160 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1161 }
1162
1163 static void
1164 jme_stop_shutdown_timer(struct jme_adapter *jme)
1165 {
1166 u32 apmc;
1167
1168 jwrite32f(jme, JME_TMCSR, 0);
1169 jwrite32f(jme, JME_TIMER2, 0);
1170 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1171
1172 apmc = jread32(jme, JME_APMC);
1173 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1174 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1175 wmb();
1176 jwrite32f(jme, JME_APMC, apmc);
1177 }
1178
1179 static void
1180 jme_link_change_tasklet(unsigned long arg)
1181 {
1182 struct jme_adapter *jme = (struct jme_adapter *)arg;
1183 struct net_device *netdev = jme->dev;
1184 int rc;
1185
1186 while (!atomic_dec_and_test(&jme->link_changing)) {
1187 atomic_inc(&jme->link_changing);
1188 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
1189 while (atomic_read(&jme->link_changing) != 1)
1190 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
1191 }
1192
1193 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1194 goto out;
1195
1196 jme->old_mtu = netdev->mtu;
1197 netif_stop_queue(netdev);
1198 if (jme_pseudo_hotplug_enabled(jme))
1199 jme_stop_shutdown_timer(jme);
1200
1201 jme_stop_pcc_timer(jme);
1202 tasklet_disable(&jme->txclean_task);
1203 tasklet_disable(&jme->rxclean_task);
1204 tasklet_disable(&jme->rxempty_task);
1205
1206 if (netif_carrier_ok(netdev)) {
1207 jme_reset_ghc_speed(jme);
1208 jme_disable_rx_engine(jme);
1209 jme_disable_tx_engine(jme);
1210 jme_reset_mac_processor(jme);
1211 jme_free_rx_resources(jme);
1212 jme_free_tx_resources(jme);
1213
1214 if (test_bit(JME_FLAG_POLL, &jme->flags))
1215 jme_polling_mode(jme);
1216
1217 netif_carrier_off(netdev);
1218 }
1219
1220 jme_check_link(netdev, 0);
1221 if (netif_carrier_ok(netdev)) {
1222 rc = jme_setup_rx_resources(jme);
1223 if (rc) {
1224 jeprintk(jme->pdev, "Allocating resources for RX error"
1225 ", Device STOPPED!\n");
1226 goto out_enable_tasklet;
1227 }
1228
1229 rc = jme_setup_tx_resources(jme);
1230 if (rc) {
1231 jeprintk(jme->pdev, "Allocating resources for TX error"
1232 ", Device STOPPED!\n");
1233 goto err_out_free_rx_resources;
1234 }
1235
1236 jme_enable_rx_engine(jme);
1237 jme_enable_tx_engine(jme);
1238
1239 netif_start_queue(netdev);
1240
1241 if (test_bit(JME_FLAG_POLL, &jme->flags))
1242 jme_interrupt_mode(jme);
1243
1244 jme_start_pcc_timer(jme);
1245 } else if (jme_pseudo_hotplug_enabled(jme)) {
1246 jme_start_shutdown_timer(jme);
1247 }
1248
1249 goto out_enable_tasklet;
1250
1251 err_out_free_rx_resources:
1252 jme_free_rx_resources(jme);
1253 out_enable_tasklet:
1254 tasklet_enable(&jme->txclean_task);
1255 tasklet_hi_enable(&jme->rxclean_task);
1256 tasklet_hi_enable(&jme->rxempty_task);
1257 out:
1258 atomic_inc(&jme->link_changing);
1259 }
1260
1261 static void
1262 jme_rx_clean_tasklet(unsigned long arg)
1263 {
1264 struct jme_adapter *jme = (struct jme_adapter *)arg;
1265 struct dynpcc_info *dpi = &(jme->dpi);
1266
1267 jme_process_receive(jme, jme->rx_ring_size);
1268 ++(dpi->intr_cnt);
1269
1270 }
1271
1272 static int
1273 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1274 {
1275 struct jme_adapter *jme = jme_napi_priv(holder);
1276 int rest;
1277
1278 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1279
1280 while (atomic_read(&jme->rx_empty) > 0) {
1281 atomic_dec(&jme->rx_empty);
1282 ++(NET_STAT(jme).rx_dropped);
1283 jme_restart_rx_engine(jme);
1284 }
1285 atomic_inc(&jme->rx_empty);
1286
1287 if (rest) {
1288 JME_RX_COMPLETE(netdev, holder);
1289 jme_interrupt_mode(jme);
1290 }
1291
1292 JME_NAPI_WEIGHT_SET(budget, rest);
1293 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1294 }
1295
1296 static void
1297 jme_rx_empty_tasklet(unsigned long arg)
1298 {
1299 struct jme_adapter *jme = (struct jme_adapter *)arg;
1300
1301 if (unlikely(atomic_read(&jme->link_changing) != 1))
1302 return;
1303
1304 if (unlikely(!netif_carrier_ok(jme->dev)))
1305 return;
1306
1307 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1308
1309 jme_rx_clean_tasklet(arg);
1310
1311 while (atomic_read(&jme->rx_empty) > 0) {
1312 atomic_dec(&jme->rx_empty);
1313 ++(NET_STAT(jme).rx_dropped);
1314 jme_restart_rx_engine(jme);
1315 }
1316 atomic_inc(&jme->rx_empty);
1317 }
1318
1319 static void
1320 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1321 {
1322 struct jme_ring *txring = &(jme->txring[0]);
1323
1324 smp_wmb();
1325 if (unlikely(netif_queue_stopped(jme->dev) &&
1326 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1327 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
1328 netif_wake_queue(jme->dev);
1329 }
1330
1331 }
1332
1333 static void
1334 jme_tx_clean_tasklet(unsigned long arg)
1335 {
1336 struct jme_adapter *jme = (struct jme_adapter *)arg;
1337 struct jme_ring *txring = &(jme->txring[0]);
1338 struct txdesc *txdesc = txring->desc;
1339 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1340 int i, j, cnt = 0, max, err, mask;
1341
1342 tx_dbg(jme, "Into txclean.\n");
1343
1344 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1345 goto out;
1346
1347 if (unlikely(atomic_read(&jme->link_changing) != 1))
1348 goto out;
1349
1350 if (unlikely(!netif_carrier_ok(jme->dev)))
1351 goto out;
1352
1353 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1354 mask = jme->tx_ring_mask;
1355
1356 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1357
1358 ctxbi = txbi + i;
1359
1360 if (likely(ctxbi->skb &&
1361 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1362
1363 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1364 i, ctxbi->nr_desc, jiffies);
1365
1366 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1367
1368 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1369 ttxbi = txbi + ((i + j) & (mask));
1370 txdesc[(i + j) & (mask)].dw[0] = 0;
1371
1372 pci_unmap_page(jme->pdev,
1373 ttxbi->mapping,
1374 ttxbi->len,
1375 PCI_DMA_TODEVICE);
1376
1377 ttxbi->mapping = 0;
1378 ttxbi->len = 0;
1379 }
1380
1381 dev_kfree_skb(ctxbi->skb);
1382
1383 cnt += ctxbi->nr_desc;
1384
1385 if (unlikely(err)) {
1386 ++(NET_STAT(jme).tx_carrier_errors);
1387 } else {
1388 ++(NET_STAT(jme).tx_packets);
1389 NET_STAT(jme).tx_bytes += ctxbi->len;
1390 }
1391
1392 ctxbi->skb = NULL;
1393 ctxbi->len = 0;
1394 ctxbi->start_xmit = 0;
1395
1396 } else {
1397 break;
1398 }
1399
1400 i = (i + ctxbi->nr_desc) & mask;
1401
1402 ctxbi->nr_desc = 0;
1403 }
1404
1405 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1406 atomic_set(&txring->next_to_clean, i);
1407 atomic_add(cnt, &txring->nr_free);
1408
1409 jme_wake_queue_if_stopped(jme);
1410
1411 out:
1412 atomic_inc(&jme->tx_cleaning);
1413 }
1414
1415 static void
1416 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1417 {
1418 /*
1419 * Disable interrupt
1420 */
1421 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1422
1423 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1424 /*
1425 * Link change event is critical
1426 * all other events are ignored
1427 */
1428 jwrite32(jme, JME_IEVE, intrstat);
1429 tasklet_schedule(&jme->linkch_task);
1430 goto out_reenable;
1431 }
1432
1433 if (intrstat & INTR_TMINTR) {
1434 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1435 tasklet_schedule(&jme->pcc_task);
1436 }
1437
1438 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1439 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1440 tasklet_schedule(&jme->txclean_task);
1441 }
1442
1443 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1444 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1445 INTR_PCCRX0 |
1446 INTR_RX0EMP)) |
1447 INTR_RX0);
1448 }
1449
1450 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1451 if (intrstat & INTR_RX0EMP)
1452 atomic_inc(&jme->rx_empty);
1453
1454 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1455 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1456 jme_polling_mode(jme);
1457 JME_RX_SCHEDULE(jme);
1458 }
1459 }
1460 } else {
1461 if (intrstat & INTR_RX0EMP) {
1462 atomic_inc(&jme->rx_empty);
1463 tasklet_hi_schedule(&jme->rxempty_task);
1464 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1465 tasklet_hi_schedule(&jme->rxclean_task);
1466 }
1467 }
1468
1469 out_reenable:
1470 /*
1471 * Re-enable interrupt
1472 */
1473 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1474 }
1475
1476 static irqreturn_t
1477 jme_intr(int irq, void *dev_id)
1478 {
1479 struct net_device *netdev = dev_id;
1480 struct jme_adapter *jme = netdev_priv(netdev);
1481 u32 intrstat;
1482
1483 intrstat = jread32(jme, JME_IEVE);
1484
1485 /*
1486 * Check if it's really an interrupt for us
1487 */
1488 if (unlikely((intrstat & INTR_ENABLE) == 0))
1489 return IRQ_NONE;
1490
1491 /*
1492 * Check if the device still exist
1493 */
1494 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1495 return IRQ_NONE;
1496
1497 jme_intr_msi(jme, intrstat);
1498
1499 return IRQ_HANDLED;
1500 }
1501
1502 static irqreturn_t
1503 jme_msi(int irq, void *dev_id)
1504 {
1505 struct net_device *netdev = dev_id;
1506 struct jme_adapter *jme = netdev_priv(netdev);
1507 u32 intrstat;
1508
1509 intrstat = jread32(jme, JME_IEVE);
1510
1511 jme_intr_msi(jme, intrstat);
1512
1513 return IRQ_HANDLED;
1514 }
1515
1516 static void
1517 jme_reset_link(struct jme_adapter *jme)
1518 {
1519 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1520 }
1521
1522 static void
1523 jme_restart_an(struct jme_adapter *jme)
1524 {
1525 u32 bmcr;
1526
1527 spin_lock_bh(&jme->phy_lock);
1528 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1529 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1530 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1531 spin_unlock_bh(&jme->phy_lock);
1532 }
1533
1534 static int
1535 jme_request_irq(struct jme_adapter *jme)
1536 {
1537 int rc;
1538 struct net_device *netdev = jme->dev;
1539 irq_handler_t handler = jme_intr;
1540 int irq_flags = IRQF_SHARED;
1541
1542 if (!pci_enable_msi(jme->pdev)) {
1543 set_bit(JME_FLAG_MSI, &jme->flags);
1544 handler = jme_msi;
1545 irq_flags = 0;
1546 }
1547
1548 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1549 netdev);
1550 if (rc) {
1551 jeprintk(jme->pdev,
1552 "Unable to request %s interrupt (return: %d)\n",
1553 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1554 rc);
1555
1556 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1557 pci_disable_msi(jme->pdev);
1558 clear_bit(JME_FLAG_MSI, &jme->flags);
1559 }
1560 } else {
1561 netdev->irq = jme->pdev->irq;
1562 }
1563
1564 return rc;
1565 }
1566
1567 static void
1568 jme_free_irq(struct jme_adapter *jme)
1569 {
1570 free_irq(jme->pdev->irq, jme->dev);
1571 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1572 pci_disable_msi(jme->pdev);
1573 clear_bit(JME_FLAG_MSI, &jme->flags);
1574 jme->dev->irq = jme->pdev->irq;
1575 }
1576 }
1577
1578 static int
1579 jme_open(struct net_device *netdev)
1580 {
1581 struct jme_adapter *jme = netdev_priv(netdev);
1582 int rc;
1583
1584 jme_clear_pm(jme);
1585 JME_NAPI_ENABLE(jme);
1586
1587 tasklet_enable(&jme->linkch_task);
1588 tasklet_enable(&jme->txclean_task);
1589 tasklet_hi_enable(&jme->rxclean_task);
1590 tasklet_hi_enable(&jme->rxempty_task);
1591
1592 rc = jme_request_irq(jme);
1593 if (rc)
1594 goto err_out;
1595
1596 jme_start_irq(jme);
1597
1598 if (test_bit(JME_FLAG_SSET, &jme->flags))
1599 jme_set_settings(netdev, &jme->old_ecmd);
1600 else
1601 jme_reset_phy_processor(jme);
1602
1603 jme_reset_link(jme);
1604
1605 return 0;
1606
1607 err_out:
1608 netif_stop_queue(netdev);
1609 netif_carrier_off(netdev);
1610 return rc;
1611 }
1612
1613 #ifdef CONFIG_PM
1614 static void
1615 jme_set_100m_half(struct jme_adapter *jme)
1616 {
1617 u32 bmcr, tmp;
1618
1619 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1620 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1621 BMCR_SPEED1000 | BMCR_FULLDPLX);
1622 tmp |= BMCR_SPEED100;
1623
1624 if (bmcr != tmp)
1625 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1626
1627 if (jme->fpgaver)
1628 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1629 else
1630 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1631 }
1632
1633 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1634 static void
1635 jme_wait_link(struct jme_adapter *jme)
1636 {
1637 u32 phylink, to = JME_WAIT_LINK_TIME;
1638
1639 mdelay(1000);
1640 phylink = jme_linkstat_from_phy(jme);
1641 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1642 mdelay(10);
1643 phylink = jme_linkstat_from_phy(jme);
1644 }
1645 }
1646 #endif
1647
1648 static inline void
1649 jme_phy_off(struct jme_adapter *jme)
1650 {
1651 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1652 }
1653
1654 static int
1655 jme_close(struct net_device *netdev)
1656 {
1657 struct jme_adapter *jme = netdev_priv(netdev);
1658
1659 netif_stop_queue(netdev);
1660 netif_carrier_off(netdev);
1661
1662 jme_stop_irq(jme);
1663 jme_free_irq(jme);
1664
1665 JME_NAPI_DISABLE(jme);
1666
1667 tasklet_disable(&jme->linkch_task);
1668 tasklet_disable(&jme->txclean_task);
1669 tasklet_disable(&jme->rxclean_task);
1670 tasklet_disable(&jme->rxempty_task);
1671
1672 jme_reset_ghc_speed(jme);
1673 jme_disable_rx_engine(jme);
1674 jme_disable_tx_engine(jme);
1675 jme_reset_mac_processor(jme);
1676 jme_free_rx_resources(jme);
1677 jme_free_tx_resources(jme);
1678 jme->phylink = 0;
1679 jme_phy_off(jme);
1680
1681 return 0;
1682 }
1683
1684 static int
1685 jme_alloc_txdesc(struct jme_adapter *jme,
1686 struct sk_buff *skb)
1687 {
1688 struct jme_ring *txring = &(jme->txring[0]);
1689 int idx, nr_alloc, mask = jme->tx_ring_mask;
1690
1691 idx = txring->next_to_use;
1692 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1693
1694 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1695 return -1;
1696
1697 atomic_sub(nr_alloc, &txring->nr_free);
1698
1699 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1700
1701 return idx;
1702 }
1703
1704 static void
1705 jme_fill_tx_map(struct pci_dev *pdev,
1706 struct txdesc *txdesc,
1707 struct jme_buffer_info *txbi,
1708 struct page *page,
1709 u32 page_offset,
1710 u32 len,
1711 u8 hidma)
1712 {
1713 dma_addr_t dmaaddr;
1714
1715 dmaaddr = pci_map_page(pdev,
1716 page,
1717 page_offset,
1718 len,
1719 PCI_DMA_TODEVICE);
1720
1721 pci_dma_sync_single_for_device(pdev,
1722 dmaaddr,
1723 len,
1724 PCI_DMA_TODEVICE);
1725
1726 txdesc->dw[0] = 0;
1727 txdesc->dw[1] = 0;
1728 txdesc->desc2.flags = TXFLAG_OWN;
1729 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1730 txdesc->desc2.datalen = cpu_to_le16(len);
1731 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1732 txdesc->desc2.bufaddrl = cpu_to_le32(
1733 (__u64)dmaaddr & 0xFFFFFFFFUL);
1734
1735 txbi->mapping = dmaaddr;
1736 txbi->len = len;
1737 }
1738
1739 static void
1740 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1741 {
1742 struct jme_ring *txring = &(jme->txring[0]);
1743 struct txdesc *txdesc = txring->desc, *ctxdesc;
1744 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1745 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1746 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1747 int mask = jme->tx_ring_mask;
1748 struct skb_frag_struct *frag;
1749 u32 len;
1750
1751 for (i = 0 ; i < nr_frags ; ++i) {
1752 frag = &skb_shinfo(skb)->frags[i];
1753 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1754 ctxbi = txbi + ((idx + i + 2) & (mask));
1755
1756 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1757 frag->page_offset, frag->size, hidma);
1758 }
1759
1760 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1761 ctxdesc = txdesc + ((idx + 1) & (mask));
1762 ctxbi = txbi + ((idx + 1) & (mask));
1763 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1764 offset_in_page(skb->data), len, hidma);
1765
1766 }
1767
1768 static int
1769 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1770 {
1771 if (unlikely(skb_shinfo(skb)->gso_size &&
1772 skb_header_cloned(skb) &&
1773 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1774 dev_kfree_skb(skb);
1775 return -1;
1776 }
1777
1778 return 0;
1779 }
1780
1781 static int
1782 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1783 {
1784 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1785 if (*mss) {
1786 *flags |= TXFLAG_LSEN;
1787
1788 if (skb->protocol == htons(ETH_P_IP)) {
1789 struct iphdr *iph = ip_hdr(skb);
1790
1791 iph->check = 0;
1792 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1793 iph->daddr, 0,
1794 IPPROTO_TCP,
1795 0);
1796 } else {
1797 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1798
1799 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1800 &ip6h->daddr, 0,
1801 IPPROTO_TCP,
1802 0);
1803 }
1804
1805 return 0;
1806 }
1807
1808 return 1;
1809 }
1810
1811 static void
1812 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1813 {
1814 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1815 u8 ip_proto;
1816
1817 switch (skb->protocol) {
1818 case htons(ETH_P_IP):
1819 ip_proto = ip_hdr(skb)->protocol;
1820 break;
1821 case htons(ETH_P_IPV6):
1822 ip_proto = ipv6_hdr(skb)->nexthdr;
1823 break;
1824 default:
1825 ip_proto = 0;
1826 break;
1827 }
1828
1829 switch (ip_proto) {
1830 case IPPROTO_TCP:
1831 *flags |= TXFLAG_TCPCS;
1832 break;
1833 case IPPROTO_UDP:
1834 *flags |= TXFLAG_UDPCS;
1835 break;
1836 default:
1837 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
1838 break;
1839 }
1840 }
1841 }
1842
1843 static inline void
1844 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1845 {
1846 if (vlan_tx_tag_present(skb)) {
1847 *flags |= TXFLAG_TAGON;
1848 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1849 }
1850 }
1851
1852 static int
1853 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1854 {
1855 struct jme_ring *txring = &(jme->txring[0]);
1856 struct txdesc *txdesc;
1857 struct jme_buffer_info *txbi;
1858 u8 flags;
1859
1860 txdesc = (struct txdesc *)txring->desc + idx;
1861 txbi = txring->bufinf + idx;
1862
1863 txdesc->dw[0] = 0;
1864 txdesc->dw[1] = 0;
1865 txdesc->dw[2] = 0;
1866 txdesc->dw[3] = 0;
1867 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1868 /*
1869 * Set OWN bit at final.
1870 * When kernel transmit faster than NIC.
1871 * And NIC trying to send this descriptor before we tell
1872 * it to start sending this TX queue.
1873 * Other fields are already filled correctly.
1874 */
1875 wmb();
1876 flags = TXFLAG_OWN | TXFLAG_INT;
1877 /*
1878 * Set checksum flags while not tso
1879 */
1880 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1881 jme_tx_csum(jme, skb, &flags);
1882 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1883 jme_map_tx_skb(jme, skb, idx);
1884 txdesc->desc1.flags = flags;
1885 /*
1886 * Set tx buffer info after telling NIC to send
1887 * For better tx_clean timing
1888 */
1889 wmb();
1890 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1891 txbi->skb = skb;
1892 txbi->len = skb->len;
1893 txbi->start_xmit = jiffies;
1894 if (!txbi->start_xmit)
1895 txbi->start_xmit = (0UL-1);
1896
1897 return 0;
1898 }
1899
1900 static void
1901 jme_stop_queue_if_full(struct jme_adapter *jme)
1902 {
1903 struct jme_ring *txring = &(jme->txring[0]);
1904 struct jme_buffer_info *txbi = txring->bufinf;
1905 int idx = atomic_read(&txring->next_to_clean);
1906
1907 txbi += idx;
1908
1909 smp_wmb();
1910 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1911 netif_stop_queue(jme->dev);
1912 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
1913 smp_wmb();
1914 if (atomic_read(&txring->nr_free)
1915 >= (jme->tx_wake_threshold)) {
1916 netif_wake_queue(jme->dev);
1917 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
1918 }
1919 }
1920
1921 if (unlikely(txbi->start_xmit &&
1922 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1923 txbi->skb)) {
1924 netif_stop_queue(jme->dev);
1925 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1926 }
1927 }
1928
1929 /*
1930 * This function is already protected by netif_tx_lock()
1931 */
1932
1933 static netdev_tx_t
1934 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1935 {
1936 struct jme_adapter *jme = netdev_priv(netdev);
1937 int idx;
1938
1939 if (unlikely(jme_expand_header(jme, skb))) {
1940 ++(NET_STAT(jme).tx_dropped);
1941 return NETDEV_TX_OK;
1942 }
1943
1944 idx = jme_alloc_txdesc(jme, skb);
1945
1946 if (unlikely(idx < 0)) {
1947 netif_stop_queue(netdev);
1948 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
1949
1950 return NETDEV_TX_BUSY;
1951 }
1952
1953 jme_fill_tx_desc(jme, skb, idx);
1954
1955 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1956 TXCS_SELECT_QUEUE0 |
1957 TXCS_QUEUE0S |
1958 TXCS_ENABLE);
1959
1960 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1961 skb_shinfo(skb)->nr_frags + 2,
1962 jiffies);
1963 jme_stop_queue_if_full(jme);
1964
1965 return NETDEV_TX_OK;
1966 }
1967
1968 static int
1969 jme_set_macaddr(struct net_device *netdev, void *p)
1970 {
1971 struct jme_adapter *jme = netdev_priv(netdev);
1972 struct sockaddr *addr = p;
1973 u32 val;
1974
1975 if (netif_running(netdev))
1976 return -EBUSY;
1977
1978 spin_lock_bh(&jme->macaddr_lock);
1979 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1980
1981 val = (addr->sa_data[3] & 0xff) << 24 |
1982 (addr->sa_data[2] & 0xff) << 16 |
1983 (addr->sa_data[1] & 0xff) << 8 |
1984 (addr->sa_data[0] & 0xff);
1985 jwrite32(jme, JME_RXUMA_LO, val);
1986 val = (addr->sa_data[5] & 0xff) << 8 |
1987 (addr->sa_data[4] & 0xff);
1988 jwrite32(jme, JME_RXUMA_HI, val);
1989 spin_unlock_bh(&jme->macaddr_lock);
1990
1991 return 0;
1992 }
1993
1994 static void
1995 jme_set_multi(struct net_device *netdev)
1996 {
1997 struct jme_adapter *jme = netdev_priv(netdev);
1998 u32 mc_hash[2] = {};
1999
2000 spin_lock_bh(&jme->rxmcs_lock);
2001
2002 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2003
2004 if (netdev->flags & IFF_PROMISC) {
2005 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2006 } else if (netdev->flags & IFF_ALLMULTI) {
2007 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2008 } else if (netdev->flags & IFF_MULTICAST) {
2009 struct netdev_hw_addr *ha;
2010 int bit_nr;
2011
2012 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2013 netdev_for_each_mc_addr(ha, netdev) {
2014 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2015 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2016 }
2017
2018 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2019 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2020 }
2021
2022 wmb();
2023 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2024
2025 spin_unlock_bh(&jme->rxmcs_lock);
2026 }
2027
2028 static int
2029 jme_change_mtu(struct net_device *netdev, int new_mtu)
2030 {
2031 struct jme_adapter *jme = netdev_priv(netdev);
2032
2033 if (new_mtu == jme->old_mtu)
2034 return 0;
2035
2036 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2037 ((new_mtu) < IPV6_MIN_MTU))
2038 return -EINVAL;
2039
2040 if (new_mtu > 4000) {
2041 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2042 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2043 jme_restart_rx_engine(jme);
2044 } else {
2045 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2046 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2047 jme_restart_rx_engine(jme);
2048 }
2049
2050 if (new_mtu > 1900) {
2051 netdev->features &= ~(NETIF_F_HW_CSUM |
2052 NETIF_F_TSO |
2053 NETIF_F_TSO6);
2054 } else {
2055 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2056 netdev->features |= NETIF_F_HW_CSUM;
2057 if (test_bit(JME_FLAG_TSO, &jme->flags))
2058 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2059 }
2060
2061 netdev->mtu = new_mtu;
2062 jme_reset_link(jme);
2063
2064 return 0;
2065 }
2066
2067 static void
2068 jme_tx_timeout(struct net_device *netdev)
2069 {
2070 struct jme_adapter *jme = netdev_priv(netdev);
2071
2072 jme->phylink = 0;
2073 jme_reset_phy_processor(jme);
2074 if (test_bit(JME_FLAG_SSET, &jme->flags))
2075 jme_set_settings(netdev, &jme->old_ecmd);
2076
2077 /*
2078 * Force to Reset the link again
2079 */
2080 jme_reset_link(jme);
2081 }
2082
2083 static inline void jme_pause_rx(struct jme_adapter *jme)
2084 {
2085 atomic_dec(&jme->link_changing);
2086
2087 jme_set_rx_pcc(jme, PCC_OFF);
2088 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2089 JME_NAPI_DISABLE(jme);
2090 } else {
2091 tasklet_disable(&jme->rxclean_task);
2092 tasklet_disable(&jme->rxempty_task);
2093 }
2094 }
2095
2096 static inline void jme_resume_rx(struct jme_adapter *jme)
2097 {
2098 struct dynpcc_info *dpi = &(jme->dpi);
2099
2100 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2101 JME_NAPI_ENABLE(jme);
2102 } else {
2103 tasklet_hi_enable(&jme->rxclean_task);
2104 tasklet_hi_enable(&jme->rxempty_task);
2105 }
2106 dpi->cur = PCC_P1;
2107 dpi->attempt = PCC_P1;
2108 dpi->cnt = 0;
2109 jme_set_rx_pcc(jme, PCC_P1);
2110
2111 atomic_inc(&jme->link_changing);
2112 }
2113
2114 static void
2115 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2116 {
2117 struct jme_adapter *jme = netdev_priv(netdev);
2118
2119 jme_pause_rx(jme);
2120 jme->vlgrp = grp;
2121 jme_resume_rx(jme);
2122 }
2123
2124 static void
2125 jme_get_drvinfo(struct net_device *netdev,
2126 struct ethtool_drvinfo *info)
2127 {
2128 struct jme_adapter *jme = netdev_priv(netdev);
2129
2130 strcpy(info->driver, DRV_NAME);
2131 strcpy(info->version, DRV_VERSION);
2132 strcpy(info->bus_info, pci_name(jme->pdev));
2133 }
2134
2135 static int
2136 jme_get_regs_len(struct net_device *netdev)
2137 {
2138 return JME_REG_LEN;
2139 }
2140
2141 static void
2142 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2143 {
2144 int i;
2145
2146 for (i = 0 ; i < len ; i += 4)
2147 p[i >> 2] = jread32(jme, reg + i);
2148 }
2149
2150 static void
2151 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2152 {
2153 int i;
2154 u16 *p16 = (u16 *)p;
2155
2156 for (i = 0 ; i < reg_nr ; ++i)
2157 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2158 }
2159
2160 static void
2161 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2162 {
2163 struct jme_adapter *jme = netdev_priv(netdev);
2164 u32 *p32 = (u32 *)p;
2165
2166 memset(p, 0xFF, JME_REG_LEN);
2167
2168 regs->version = 1;
2169 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2170
2171 p32 += 0x100 >> 2;
2172 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2173
2174 p32 += 0x100 >> 2;
2175 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2176
2177 p32 += 0x100 >> 2;
2178 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2179
2180 p32 += 0x100 >> 2;
2181 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2182 }
2183
2184 static int
2185 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2186 {
2187 struct jme_adapter *jme = netdev_priv(netdev);
2188
2189 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2190 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2191
2192 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2193 ecmd->use_adaptive_rx_coalesce = false;
2194 ecmd->rx_coalesce_usecs = 0;
2195 ecmd->rx_max_coalesced_frames = 0;
2196 return 0;
2197 }
2198
2199 ecmd->use_adaptive_rx_coalesce = true;
2200
2201 switch (jme->dpi.cur) {
2202 case PCC_P1:
2203 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2204 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2205 break;
2206 case PCC_P2:
2207 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2208 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2209 break;
2210 case PCC_P3:
2211 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2212 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2213 break;
2214 default:
2215 break;
2216 }
2217
2218 return 0;
2219 }
2220
2221 static int
2222 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2223 {
2224 struct jme_adapter *jme = netdev_priv(netdev);
2225 struct dynpcc_info *dpi = &(jme->dpi);
2226
2227 if (netif_running(netdev))
2228 return -EBUSY;
2229
2230 if (ecmd->use_adaptive_rx_coalesce &&
2231 test_bit(JME_FLAG_POLL, &jme->flags)) {
2232 clear_bit(JME_FLAG_POLL, &jme->flags);
2233 jme->jme_rx = netif_rx;
2234 jme->jme_vlan_rx = vlan_hwaccel_rx;
2235 dpi->cur = PCC_P1;
2236 dpi->attempt = PCC_P1;
2237 dpi->cnt = 0;
2238 jme_set_rx_pcc(jme, PCC_P1);
2239 jme_interrupt_mode(jme);
2240 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2241 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2242 set_bit(JME_FLAG_POLL, &jme->flags);
2243 jme->jme_rx = netif_receive_skb;
2244 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2245 jme_interrupt_mode(jme);
2246 }
2247
2248 return 0;
2249 }
2250
2251 static void
2252 jme_get_pauseparam(struct net_device *netdev,
2253 struct ethtool_pauseparam *ecmd)
2254 {
2255 struct jme_adapter *jme = netdev_priv(netdev);
2256 u32 val;
2257
2258 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2259 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2260
2261 spin_lock_bh(&jme->phy_lock);
2262 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2263 spin_unlock_bh(&jme->phy_lock);
2264
2265 ecmd->autoneg =
2266 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2267 }
2268
2269 static int
2270 jme_set_pauseparam(struct net_device *netdev,
2271 struct ethtool_pauseparam *ecmd)
2272 {
2273 struct jme_adapter *jme = netdev_priv(netdev);
2274 u32 val;
2275
2276 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2277 (ecmd->tx_pause != 0)) {
2278
2279 if (ecmd->tx_pause)
2280 jme->reg_txpfc |= TXPFC_PF_EN;
2281 else
2282 jme->reg_txpfc &= ~TXPFC_PF_EN;
2283
2284 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2285 }
2286
2287 spin_lock_bh(&jme->rxmcs_lock);
2288 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2289 (ecmd->rx_pause != 0)) {
2290
2291 if (ecmd->rx_pause)
2292 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2293 else
2294 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2295
2296 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2297 }
2298 spin_unlock_bh(&jme->rxmcs_lock);
2299
2300 spin_lock_bh(&jme->phy_lock);
2301 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2302 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2303 (ecmd->autoneg != 0)) {
2304
2305 if (ecmd->autoneg)
2306 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2307 else
2308 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2309
2310 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2311 MII_ADVERTISE, val);
2312 }
2313 spin_unlock_bh(&jme->phy_lock);
2314
2315 return 0;
2316 }
2317
2318 static void
2319 jme_get_wol(struct net_device *netdev,
2320 struct ethtool_wolinfo *wol)
2321 {
2322 struct jme_adapter *jme = netdev_priv(netdev);
2323
2324 wol->supported = WAKE_MAGIC | WAKE_PHY;
2325
2326 wol->wolopts = 0;
2327
2328 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2329 wol->wolopts |= WAKE_PHY;
2330
2331 if (jme->reg_pmcs & PMCS_MFEN)
2332 wol->wolopts |= WAKE_MAGIC;
2333
2334 }
2335
2336 static int
2337 jme_set_wol(struct net_device *netdev,
2338 struct ethtool_wolinfo *wol)
2339 {
2340 struct jme_adapter *jme = netdev_priv(netdev);
2341
2342 if (wol->wolopts & (WAKE_MAGICSECURE |
2343 WAKE_UCAST |
2344 WAKE_MCAST |
2345 WAKE_BCAST |
2346 WAKE_ARP))
2347 return -EOPNOTSUPP;
2348
2349 jme->reg_pmcs = 0;
2350
2351 if (wol->wolopts & WAKE_PHY)
2352 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2353
2354 if (wol->wolopts & WAKE_MAGIC)
2355 jme->reg_pmcs |= PMCS_MFEN;
2356
2357 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2358
2359 return 0;
2360 }
2361
2362 static int
2363 jme_get_settings(struct net_device *netdev,
2364 struct ethtool_cmd *ecmd)
2365 {
2366 struct jme_adapter *jme = netdev_priv(netdev);
2367 int rc;
2368
2369 spin_lock_bh(&jme->phy_lock);
2370 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2371 spin_unlock_bh(&jme->phy_lock);
2372 return rc;
2373 }
2374
2375 static int
2376 jme_set_settings(struct net_device *netdev,
2377 struct ethtool_cmd *ecmd)
2378 {
2379 struct jme_adapter *jme = netdev_priv(netdev);
2380 int rc, fdc = 0;
2381
2382 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2383 return -EINVAL;
2384
2385 if (jme->mii_if.force_media &&
2386 ecmd->autoneg != AUTONEG_ENABLE &&
2387 (jme->mii_if.full_duplex != ecmd->duplex))
2388 fdc = 1;
2389
2390 spin_lock_bh(&jme->phy_lock);
2391 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2392 spin_unlock_bh(&jme->phy_lock);
2393
2394 if (!rc && fdc)
2395 jme_reset_link(jme);
2396
2397 if (!rc) {
2398 set_bit(JME_FLAG_SSET, &jme->flags);
2399 jme->old_ecmd = *ecmd;
2400 }
2401
2402 return rc;
2403 }
2404
2405 static u32
2406 jme_get_link(struct net_device *netdev)
2407 {
2408 struct jme_adapter *jme = netdev_priv(netdev);
2409 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2410 }
2411
2412 static u32
2413 jme_get_msglevel(struct net_device *netdev)
2414 {
2415 struct jme_adapter *jme = netdev_priv(netdev);
2416 return jme->msg_enable;
2417 }
2418
2419 static void
2420 jme_set_msglevel(struct net_device *netdev, u32 value)
2421 {
2422 struct jme_adapter *jme = netdev_priv(netdev);
2423 jme->msg_enable = value;
2424 }
2425
2426 static u32
2427 jme_get_rx_csum(struct net_device *netdev)
2428 {
2429 struct jme_adapter *jme = netdev_priv(netdev);
2430 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2431 }
2432
2433 static int
2434 jme_set_rx_csum(struct net_device *netdev, u32 on)
2435 {
2436 struct jme_adapter *jme = netdev_priv(netdev);
2437
2438 spin_lock_bh(&jme->rxmcs_lock);
2439 if (on)
2440 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2441 else
2442 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2443 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2444 spin_unlock_bh(&jme->rxmcs_lock);
2445
2446 return 0;
2447 }
2448
2449 static int
2450 jme_set_tx_csum(struct net_device *netdev, u32 on)
2451 {
2452 struct jme_adapter *jme = netdev_priv(netdev);
2453
2454 if (on) {
2455 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2456 if (netdev->mtu <= 1900)
2457 netdev->features |= NETIF_F_HW_CSUM;
2458 } else {
2459 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2460 netdev->features &= ~NETIF_F_HW_CSUM;
2461 }
2462
2463 return 0;
2464 }
2465
2466 static int
2467 jme_set_tso(struct net_device *netdev, u32 on)
2468 {
2469 struct jme_adapter *jme = netdev_priv(netdev);
2470
2471 if (on) {
2472 set_bit(JME_FLAG_TSO, &jme->flags);
2473 if (netdev->mtu <= 1900)
2474 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2475 } else {
2476 clear_bit(JME_FLAG_TSO, &jme->flags);
2477 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2478 }
2479
2480 return 0;
2481 }
2482
2483 static int
2484 jme_nway_reset(struct net_device *netdev)
2485 {
2486 struct jme_adapter *jme = netdev_priv(netdev);
2487 jme_restart_an(jme);
2488 return 0;
2489 }
2490
2491 static u8
2492 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2493 {
2494 u32 val;
2495 int to;
2496
2497 val = jread32(jme, JME_SMBCSR);
2498 to = JME_SMB_BUSY_TIMEOUT;
2499 while ((val & SMBCSR_BUSY) && --to) {
2500 msleep(1);
2501 val = jread32(jme, JME_SMBCSR);
2502 }
2503 if (!to) {
2504 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2505 return 0xFF;
2506 }
2507
2508 jwrite32(jme, JME_SMBINTF,
2509 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2510 SMBINTF_HWRWN_READ |
2511 SMBINTF_HWCMD);
2512
2513 val = jread32(jme, JME_SMBINTF);
2514 to = JME_SMB_BUSY_TIMEOUT;
2515 while ((val & SMBINTF_HWCMD) && --to) {
2516 msleep(1);
2517 val = jread32(jme, JME_SMBINTF);
2518 }
2519 if (!to) {
2520 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2521 return 0xFF;
2522 }
2523
2524 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2525 }
2526
2527 static void
2528 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2529 {
2530 u32 val;
2531 int to;
2532
2533 val = jread32(jme, JME_SMBCSR);
2534 to = JME_SMB_BUSY_TIMEOUT;
2535 while ((val & SMBCSR_BUSY) && --to) {
2536 msleep(1);
2537 val = jread32(jme, JME_SMBCSR);
2538 }
2539 if (!to) {
2540 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2541 return;
2542 }
2543
2544 jwrite32(jme, JME_SMBINTF,
2545 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2546 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2547 SMBINTF_HWRWN_WRITE |
2548 SMBINTF_HWCMD);
2549
2550 val = jread32(jme, JME_SMBINTF);
2551 to = JME_SMB_BUSY_TIMEOUT;
2552 while ((val & SMBINTF_HWCMD) && --to) {
2553 msleep(1);
2554 val = jread32(jme, JME_SMBINTF);
2555 }
2556 if (!to) {
2557 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2558 return;
2559 }
2560
2561 mdelay(2);
2562 }
2563
2564 static int
2565 jme_get_eeprom_len(struct net_device *netdev)
2566 {
2567 struct jme_adapter *jme = netdev_priv(netdev);
2568 u32 val;
2569 val = jread32(jme, JME_SMBCSR);
2570 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2571 }
2572
2573 static int
2574 jme_get_eeprom(struct net_device *netdev,
2575 struct ethtool_eeprom *eeprom, u8 *data)
2576 {
2577 struct jme_adapter *jme = netdev_priv(netdev);
2578 int i, offset = eeprom->offset, len = eeprom->len;
2579
2580 /*
2581 * ethtool will check the boundary for us
2582 */
2583 eeprom->magic = JME_EEPROM_MAGIC;
2584 for (i = 0 ; i < len ; ++i)
2585 data[i] = jme_smb_read(jme, i + offset);
2586
2587 return 0;
2588 }
2589
2590 static int
2591 jme_set_eeprom(struct net_device *netdev,
2592 struct ethtool_eeprom *eeprom, u8 *data)
2593 {
2594 struct jme_adapter *jme = netdev_priv(netdev);
2595 int i, offset = eeprom->offset, len = eeprom->len;
2596
2597 if (eeprom->magic != JME_EEPROM_MAGIC)
2598 return -EINVAL;
2599
2600 /*
2601 * ethtool will check the boundary for us
2602 */
2603 for (i = 0 ; i < len ; ++i)
2604 jme_smb_write(jme, i + offset, data[i]);
2605
2606 return 0;
2607 }
2608
2609 static const struct ethtool_ops jme_ethtool_ops = {
2610 .get_drvinfo = jme_get_drvinfo,
2611 .get_regs_len = jme_get_regs_len,
2612 .get_regs = jme_get_regs,
2613 .get_coalesce = jme_get_coalesce,
2614 .set_coalesce = jme_set_coalesce,
2615 .get_pauseparam = jme_get_pauseparam,
2616 .set_pauseparam = jme_set_pauseparam,
2617 .get_wol = jme_get_wol,
2618 .set_wol = jme_set_wol,
2619 .get_settings = jme_get_settings,
2620 .set_settings = jme_set_settings,
2621 .get_link = jme_get_link,
2622 .get_msglevel = jme_get_msglevel,
2623 .set_msglevel = jme_set_msglevel,
2624 .get_rx_csum = jme_get_rx_csum,
2625 .set_rx_csum = jme_set_rx_csum,
2626 .set_tx_csum = jme_set_tx_csum,
2627 .set_tso = jme_set_tso,
2628 .set_sg = ethtool_op_set_sg,
2629 .nway_reset = jme_nway_reset,
2630 .get_eeprom_len = jme_get_eeprom_len,
2631 .get_eeprom = jme_get_eeprom,
2632 .set_eeprom = jme_set_eeprom,
2633 };
2634
2635 static int
2636 jme_pci_dma64(struct pci_dev *pdev)
2637 {
2638 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2639 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2640 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2641 return 1;
2642
2643 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2644 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2645 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2646 return 1;
2647
2648 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2649 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2650 return 0;
2651
2652 return -1;
2653 }
2654
2655 static inline void
2656 jme_phy_init(struct jme_adapter *jme)
2657 {
2658 u16 reg26;
2659
2660 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2661 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2662 }
2663
2664 static inline void
2665 jme_check_hw_ver(struct jme_adapter *jme)
2666 {
2667 u32 chipmode;
2668
2669 chipmode = jread32(jme, JME_CHIPMODE);
2670
2671 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2672 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2673 }
2674
2675 static const struct net_device_ops jme_netdev_ops = {
2676 .ndo_open = jme_open,
2677 .ndo_stop = jme_close,
2678 .ndo_validate_addr = eth_validate_addr,
2679 .ndo_start_xmit = jme_start_xmit,
2680 .ndo_set_mac_address = jme_set_macaddr,
2681 .ndo_set_multicast_list = jme_set_multi,
2682 .ndo_change_mtu = jme_change_mtu,
2683 .ndo_tx_timeout = jme_tx_timeout,
2684 .ndo_vlan_rx_register = jme_vlan_rx_register,
2685 };
2686
2687 static int __devinit
2688 jme_init_one(struct pci_dev *pdev,
2689 const struct pci_device_id *ent)
2690 {
2691 int rc = 0, using_dac, i;
2692 struct net_device *netdev;
2693 struct jme_adapter *jme;
2694 u16 bmcr, bmsr;
2695 u32 apmc;
2696
2697 /*
2698 * set up PCI device basics
2699 */
2700 rc = pci_enable_device(pdev);
2701 if (rc) {
2702 jeprintk(pdev, "Cannot enable PCI device.\n");
2703 goto err_out;
2704 }
2705
2706 using_dac = jme_pci_dma64(pdev);
2707 if (using_dac < 0) {
2708 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2709 rc = -EIO;
2710 goto err_out_disable_pdev;
2711 }
2712
2713 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2714 jeprintk(pdev, "No PCI resource region found.\n");
2715 rc = -ENOMEM;
2716 goto err_out_disable_pdev;
2717 }
2718
2719 rc = pci_request_regions(pdev, DRV_NAME);
2720 if (rc) {
2721 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2722 goto err_out_disable_pdev;
2723 }
2724
2725 pci_set_master(pdev);
2726
2727 /*
2728 * alloc and init net device
2729 */
2730 netdev = alloc_etherdev(sizeof(*jme));
2731 if (!netdev) {
2732 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2733 rc = -ENOMEM;
2734 goto err_out_release_regions;
2735 }
2736 netdev->netdev_ops = &jme_netdev_ops;
2737 netdev->ethtool_ops = &jme_ethtool_ops;
2738 netdev->watchdog_timeo = TX_TIMEOUT;
2739 netdev->features = NETIF_F_HW_CSUM |
2740 NETIF_F_SG |
2741 NETIF_F_TSO |
2742 NETIF_F_TSO6 |
2743 NETIF_F_HW_VLAN_TX |
2744 NETIF_F_HW_VLAN_RX;
2745 if (using_dac)
2746 netdev->features |= NETIF_F_HIGHDMA;
2747
2748 SET_NETDEV_DEV(netdev, &pdev->dev);
2749 pci_set_drvdata(pdev, netdev);
2750
2751 /*
2752 * init adapter info
2753 */
2754 jme = netdev_priv(netdev);
2755 jme->pdev = pdev;
2756 jme->dev = netdev;
2757 jme->jme_rx = netif_rx;
2758 jme->jme_vlan_rx = vlan_hwaccel_rx;
2759 jme->old_mtu = netdev->mtu = 1500;
2760 jme->phylink = 0;
2761 jme->tx_ring_size = 1 << 10;
2762 jme->tx_ring_mask = jme->tx_ring_size - 1;
2763 jme->tx_wake_threshold = 1 << 9;
2764 jme->rx_ring_size = 1 << 9;
2765 jme->rx_ring_mask = jme->rx_ring_size - 1;
2766 jme->msg_enable = JME_DEF_MSG_ENABLE;
2767 jme->regs = ioremap(pci_resource_start(pdev, 0),
2768 pci_resource_len(pdev, 0));
2769 if (!(jme->regs)) {
2770 jeprintk(pdev, "Mapping PCI resource region error.\n");
2771 rc = -ENOMEM;
2772 goto err_out_free_netdev;
2773 }
2774
2775 if (no_pseudohp) {
2776 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2777 jwrite32(jme, JME_APMC, apmc);
2778 } else if (force_pseudohp) {
2779 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2780 jwrite32(jme, JME_APMC, apmc);
2781 }
2782
2783 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2784
2785 spin_lock_init(&jme->phy_lock);
2786 spin_lock_init(&jme->macaddr_lock);
2787 spin_lock_init(&jme->rxmcs_lock);
2788
2789 atomic_set(&jme->link_changing, 1);
2790 atomic_set(&jme->rx_cleaning, 1);
2791 atomic_set(&jme->tx_cleaning, 1);
2792 atomic_set(&jme->rx_empty, 1);
2793
2794 tasklet_init(&jme->pcc_task,
2795 jme_pcc_tasklet,
2796 (unsigned long) jme);
2797 tasklet_init(&jme->linkch_task,
2798 jme_link_change_tasklet,
2799 (unsigned long) jme);
2800 tasklet_init(&jme->txclean_task,
2801 jme_tx_clean_tasklet,
2802 (unsigned long) jme);
2803 tasklet_init(&jme->rxclean_task,
2804 jme_rx_clean_tasklet,
2805 (unsigned long) jme);
2806 tasklet_init(&jme->rxempty_task,
2807 jme_rx_empty_tasklet,
2808 (unsigned long) jme);
2809 tasklet_disable_nosync(&jme->linkch_task);
2810 tasklet_disable_nosync(&jme->txclean_task);
2811 tasklet_disable_nosync(&jme->rxclean_task);
2812 tasklet_disable_nosync(&jme->rxempty_task);
2813 jme->dpi.cur = PCC_P1;
2814
2815 jme->reg_ghc = 0;
2816 jme->reg_rxcs = RXCS_DEFAULT;
2817 jme->reg_rxmcs = RXMCS_DEFAULT;
2818 jme->reg_txpfc = 0;
2819 jme->reg_pmcs = PMCS_MFEN;
2820 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2821 set_bit(JME_FLAG_TSO, &jme->flags);
2822
2823 /*
2824 * Get Max Read Req Size from PCI Config Space
2825 */
2826 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2827 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2828 switch (jme->mrrs) {
2829 case MRRS_128B:
2830 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2831 break;
2832 case MRRS_256B:
2833 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2834 break;
2835 default:
2836 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2837 break;
2838 }
2839
2840 /*
2841 * Must check before reset_mac_processor
2842 */
2843 jme_check_hw_ver(jme);
2844 jme->mii_if.dev = netdev;
2845 if (jme->fpgaver) {
2846 jme->mii_if.phy_id = 0;
2847 for (i = 1 ; i < 32 ; ++i) {
2848 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2849 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2850 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2851 jme->mii_if.phy_id = i;
2852 break;
2853 }
2854 }
2855
2856 if (!jme->mii_if.phy_id) {
2857 rc = -EIO;
2858 jeprintk(pdev, "Can not find phy_id.\n");
2859 goto err_out_unmap;
2860 }
2861
2862 jme->reg_ghc |= GHC_LINK_POLL;
2863 } else {
2864 jme->mii_if.phy_id = 1;
2865 }
2866 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2867 jme->mii_if.supports_gmii = true;
2868 else
2869 jme->mii_if.supports_gmii = false;
2870 jme->mii_if.mdio_read = jme_mdio_read;
2871 jme->mii_if.mdio_write = jme_mdio_write;
2872
2873 jme_clear_pm(jme);
2874 jme_set_phyfifoa(jme);
2875 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2876 if (!jme->fpgaver)
2877 jme_phy_init(jme);
2878 jme_phy_off(jme);
2879
2880 /*
2881 * Reset MAC processor and reload EEPROM for MAC Address
2882 */
2883 jme_reset_mac_processor(jme);
2884 rc = jme_reload_eeprom(jme);
2885 if (rc) {
2886 jeprintk(pdev,
2887 "Reload eeprom for reading MAC Address error.\n");
2888 goto err_out_unmap;
2889 }
2890 jme_load_macaddr(netdev);
2891
2892 /*
2893 * Tell stack that we are not ready to work until open()
2894 */
2895 netif_carrier_off(netdev);
2896 netif_stop_queue(netdev);
2897
2898 /*
2899 * Register netdev
2900 */
2901 rc = register_netdev(netdev);
2902 if (rc) {
2903 jeprintk(pdev, "Cannot register net device.\n");
2904 goto err_out_unmap;
2905 }
2906
2907 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2908 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2909 "JMC250 Gigabit Ethernet" :
2910 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2911 "JMC260 Fast Ethernet" : "Unknown",
2912 (jme->fpgaver != 0) ? " (FPGA)" : "",
2913 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2914 jme->rev, netdev->dev_addr);
2915
2916 return 0;
2917
2918 err_out_unmap:
2919 iounmap(jme->regs);
2920 err_out_free_netdev:
2921 pci_set_drvdata(pdev, NULL);
2922 free_netdev(netdev);
2923 err_out_release_regions:
2924 pci_release_regions(pdev);
2925 err_out_disable_pdev:
2926 pci_disable_device(pdev);
2927 err_out:
2928 return rc;
2929 }
2930
2931 static void __devexit
2932 jme_remove_one(struct pci_dev *pdev)
2933 {
2934 struct net_device *netdev = pci_get_drvdata(pdev);
2935 struct jme_adapter *jme = netdev_priv(netdev);
2936
2937 unregister_netdev(netdev);
2938 iounmap(jme->regs);
2939 pci_set_drvdata(pdev, NULL);
2940 free_netdev(netdev);
2941 pci_release_regions(pdev);
2942 pci_disable_device(pdev);
2943
2944 }
2945
2946 #ifdef CONFIG_PM
2947 static int
2948 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2949 {
2950 struct net_device *netdev = pci_get_drvdata(pdev);
2951 struct jme_adapter *jme = netdev_priv(netdev);
2952
2953 atomic_dec(&jme->link_changing);
2954
2955 netif_device_detach(netdev);
2956 netif_stop_queue(netdev);
2957 jme_stop_irq(jme);
2958
2959 tasklet_disable(&jme->txclean_task);
2960 tasklet_disable(&jme->rxclean_task);
2961 tasklet_disable(&jme->rxempty_task);
2962
2963 if (netif_carrier_ok(netdev)) {
2964 if (test_bit(JME_FLAG_POLL, &jme->flags))
2965 jme_polling_mode(jme);
2966
2967 jme_stop_pcc_timer(jme);
2968 jme_reset_ghc_speed(jme);
2969 jme_disable_rx_engine(jme);
2970 jme_disable_tx_engine(jme);
2971 jme_reset_mac_processor(jme);
2972 jme_free_rx_resources(jme);
2973 jme_free_tx_resources(jme);
2974 netif_carrier_off(netdev);
2975 jme->phylink = 0;
2976 }
2977
2978 tasklet_enable(&jme->txclean_task);
2979 tasklet_hi_enable(&jme->rxclean_task);
2980 tasklet_hi_enable(&jme->rxempty_task);
2981
2982 pci_save_state(pdev);
2983 if (jme->reg_pmcs) {
2984 jme_set_100m_half(jme);
2985
2986 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2987 jme_wait_link(jme);
2988
2989 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2990
2991 pci_enable_wake(pdev, PCI_D3cold, true);
2992 } else {
2993 jme_phy_off(jme);
2994 }
2995 pci_set_power_state(pdev, PCI_D3cold);
2996
2997 return 0;
2998 }
2999
3000 static int
3001 jme_resume(struct pci_dev *pdev)
3002 {
3003 struct net_device *netdev = pci_get_drvdata(pdev);
3004 struct jme_adapter *jme = netdev_priv(netdev);
3005
3006 jme_clear_pm(jme);
3007 pci_restore_state(pdev);
3008
3009 if (test_bit(JME_FLAG_SSET, &jme->flags))
3010 jme_set_settings(netdev, &jme->old_ecmd);
3011 else
3012 jme_reset_phy_processor(jme);
3013
3014 jme_start_irq(jme);
3015 netif_device_attach(netdev);
3016
3017 atomic_inc(&jme->link_changing);
3018
3019 jme_reset_link(jme);
3020
3021 return 0;
3022 }
3023 #endif
3024
3025 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3026 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3027 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3028 { }
3029 };
3030
3031 static struct pci_driver jme_driver = {
3032 .name = DRV_NAME,
3033 .id_table = jme_pci_tbl,
3034 .probe = jme_init_one,
3035 .remove = __devexit_p(jme_remove_one),
3036 #ifdef CONFIG_PM
3037 .suspend = jme_suspend,
3038 .resume = jme_resume,
3039 #endif /* CONFIG_PM */
3040 };
3041
3042 static int __init
3043 jme_init_module(void)
3044 {
3045 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3046 "driver version %s\n", DRV_VERSION);
3047 return pci_register_driver(&jme_driver);
3048 }
3049
3050 static void __exit
3051 jme_cleanup_module(void)
3052 {
3053 pci_unregister_driver(&jme_driver);
3054 }
3055
3056 module_init(jme_init_module);
3057 module_exit(jme_cleanup_module);
3058
3059 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3060 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3061 MODULE_LICENSE("GPL");
3062 MODULE_VERSION(DRV_VERSION);
3063 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3064
Linux with added FPC-III support