drivers/net/stmmac/dwmac100_dma.c

   1 /*******************************************************************************
   2   This is the driver for the MAC 10/100 on-chip Ethernet controller
   3   currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
   4
   5   DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
   6   this code.
   7
   8   This contains the functions to handle the dma.
   9
  10   Copyright (C) 2007-2009  STMicroelectronics Ltd
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms and conditions of the GNU General Public License,
  14   version 2, as published by the Free Software Foundation.
  15
  16   This program is distributed in the hope it will be useful, but WITHOUT
  17   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19   more details.
  20
  21   You should have received a copy of the GNU General Public License along with
  22   this program; if not, write to the Free Software Foundation, Inc.,
  23   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  24
  25   The full GNU General Public License is included in this distribution in
  26   the file called "COPYING".
  27
  28   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  29 *******************************************************************************/
  30
  31 #include "dwmac100.h"
  32 #include "dwmac_dma.h"
  33
  34 static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
  35                              u32 dma_rx)
  36 {
  37         u32 value = readl(ioaddr + DMA_BUS_MODE);
  38         /* DMA SW reset */
  39         value |= DMA_BUS_MODE_SFT_RESET;
  40         writel(value, ioaddr + DMA_BUS_MODE);
  41         do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
  42
  43         /* Enable Application Access by writing to DMA CSR0 */
  44         writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),
  45                ioaddr + DMA_BUS_MODE);
  46
  47         /* Mask interrupts by writing to CSR7 */
  48         writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
  49
  50         /* The base address of the RX/TX descriptor lists must be written into
  51          * DMA CSR3 and CSR4, respectively. */
  52         writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
  53         writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
  54
  55         return 0;
  56 }
  57
  58 /* Store and Forward capability is not used at all..
  59  * The transmit threshold can be programmed by
  60  * setting the TTC bits in the DMA control register.*/
  61 static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode,
  62                                         int rxmode)
  63 {
  64         u32 csr6 = readl(ioaddr + DMA_CONTROL);
  65
  66         if (txmode <= 32)
  67                 csr6 |= DMA_CONTROL_TTC_32;
  68         else if (txmode <= 64)
  69                 csr6 |= DMA_CONTROL_TTC_64;
  70         else
  71                 csr6 |= DMA_CONTROL_TTC_128;
  72
  73         writel(csr6, ioaddr + DMA_CONTROL);
  74 }
  75
  76 static void dwmac100_dump_dma_regs(unsigned long ioaddr)
  77 {
  78         int i;
  79
  80         CHIP_DBG(KERN_DEBUG "DWMAC 100 DMA CSR\n");
  81         for (i = 0; i < 9; i++)
  82                 pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
  83                        (DMA_BUS_MODE + i * 4),
  84                        readl(ioaddr + DMA_BUS_MODE + i * 4));
  85         CHIP_DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n",
  86             DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
  87         CHIP_DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",
  88             DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
  89 }
  90
  91 /* DMA controller has two counters to track the number of
  92  * the receive missed frames. */
  93 static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
  94                                        unsigned long ioaddr)
  95 {
  96         struct net_device_stats *stats = (struct net_device_stats *)data;
  97         u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
  98
  99         if (unlikely(csr8)) {
 100                 if (csr8 & DMA_MISSED_FRAME_OVE) {
 101                         stats->rx_over_errors += 0x800;
 102                         x->rx_overflow_cntr += 0x800;
 103                 } else {
 104                         unsigned int ove_cntr;
 105                         ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
 106                         stats->rx_over_errors += ove_cntr;
 107                         x->rx_overflow_cntr += ove_cntr;
 108                 }
 109
 110                 if (csr8 & DMA_MISSED_FRAME_OVE_M) {
 111                         stats->rx_missed_errors += 0xffff;
 112                         x->rx_missed_cntr += 0xffff;
 113                 } else {
 114                         unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
 115                         stats->rx_missed_errors += miss_f;
 116                         x->rx_missed_cntr += miss_f;
 117                 }
 118         }
 119 }
 120
 121 struct stmmac_dma_ops dwmac100_dma_ops = {
 122         .init = dwmac100_dma_init,
 123         .dump_regs = dwmac100_dump_dma_regs,
 124         .dma_mode = dwmac100_dma_operation_mode,
 125         .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
 126         .enable_dma_transmission = dwmac_enable_dma_transmission,
 127         .enable_dma_irq = dwmac_enable_dma_irq,
 128         .disable_dma_irq = dwmac_disable_dma_irq,
 129         .start_tx = dwmac_dma_start_tx,
 130         .stop_tx = dwmac_dma_stop_tx,
 131         .start_rx = dwmac_dma_start_rx,
 132         .stop_rx = dwmac_dma_stop_rx,
 133         .dma_interrupt = dwmac_dma_interrupt,
 134 };